Blackfin: unify rotary encoder bitmasks
Avoid duplication and ugly global namespace pollution. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
c385acceb4
commit
3975032405
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@ -2,7 +2,7 @@
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* board initialization should put one of these structures into platform_data
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* and place the bfin-rotary onto platform_bus named "bfin-rotary".
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*
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* Copyright 2008 Analog Devices Inc.
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* Copyright 2008-2010 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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@ -40,4 +40,76 @@ struct bfin_rotary_platform_data {
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unsigned short debounce; /* 0..17 */
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unsigned short mode;
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};
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/* CNT_CONFIG bitmasks */
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#define CNTE (1 << 0) /* Counter Enable */
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#define DEBE (1 << 1) /* Debounce Enable */
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#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */
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#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */
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#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */
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#define CNTMODE_SHIFT 8
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#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */
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#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */
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#define BNDMODE_SHIFT 12
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#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */
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#define INPDIS (1 << 15) /* CUG and CDG Input Disable */
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#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */
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#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */
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#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */
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#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */
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#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */
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#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */
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#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */
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#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */
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#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */
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/* CNT_IMASK bitmasks */
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#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */
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#define UCIE (1 << 1) /* Up count Interrupt Enable */
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#define DCIE (1 << 2) /* Down count Interrupt Enable */
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#define MINCIE (1 << 3) /* Min Count Interrupt Enable */
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#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */
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#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */
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#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */
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#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */
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#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */
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#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */
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#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */
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/* CNT_STATUS bitmasks */
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#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */
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#define UCII (1 << 1) /* Up count Interrupt Identifier */
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#define DCII (1 << 2) /* Down count Interrupt Identifier */
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#define MINCII (1 << 3) /* Min Count Interrupt Identifier */
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#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */
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#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */
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#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */
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#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */
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#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */
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#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */
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#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */
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/* CNT_COMMAND bitmasks */
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#define W1LCNT 0xf /* Load Counter Register */
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#define W1LMIN 0xf0 /* Load Min Register */
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#define W1LMAX 0xf00 /* Load Max Register */
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#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */
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#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */
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#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */
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#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */
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#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */
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#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */
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#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */
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#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */
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#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */
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#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */
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/* CNT_DEBOUNCE bitmasks */
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#define DPRESCALE 0xf /* Load Counter Register */
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#endif
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@ -1576,114 +1576,6 @@
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#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
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/* Bit masks for CNT_CONFIG */
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#define CNTE 0x1 /* Counter Enable */
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#define nCNTE 0x0
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#define DEBE 0x2 /* Debounce Enable */
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#define nDEBE 0x0
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#define CDGINV 0x10 /* CDG Pin Polarity Invert */
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#define nCDGINV 0x0
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#define CUDINV 0x20 /* CUD Pin Polarity Invert */
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#define nCUDINV 0x0
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#define CZMINV 0x40 /* CZM Pin Polarity Invert */
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#define nCZMINV 0x0
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#define CNTMODE 0x700 /* Counter Operating Mode */
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#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
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#define nZMZC 0x0
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#define BNDMODE 0x3000 /* Boundary register Mode */
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#define INPDIS 0x8000 /* CUG and CDG Input Disable */
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#define nINPDIS 0x0
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/* Bit masks for CNT_IMASK */
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#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
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#define nICIE 0x0
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#define UCIE 0x2 /* Up count Interrupt Enable */
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#define nUCIE 0x0
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#define DCIE 0x4 /* Down count Interrupt Enable */
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#define nDCIE 0x0
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#define MINCIE 0x8 /* Min Count Interrupt Enable */
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#define nMINCIE 0x0
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#define MAXCIE 0x10 /* Max Count Interrupt Enable */
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#define nMAXCIE 0x0
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#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
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#define nCOV31IE 0x0
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#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
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#define nCOV15IE 0x0
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#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
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#define nCZEROIE 0x0
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#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
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#define nCZMIE 0x0
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#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
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#define nCZMEIE 0x0
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#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
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#define nCZMZIE 0x0
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/* Bit masks for CNT_STATUS */
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#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
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#define nICII 0x0
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#define UCII 0x2 /* Up count Interrupt Identifier */
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#define nUCII 0x0
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#define DCII 0x4 /* Down count Interrupt Identifier */
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#define nDCII 0x0
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#define MINCII 0x8 /* Min Count Interrupt Identifier */
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#define nMINCII 0x0
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#define MAXCII 0x10 /* Max Count Interrupt Identifier */
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#define nMAXCII 0x0
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#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
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#define nCOV31II 0x0
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#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
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#define nCOV15II 0x0
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#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
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#define nCZEROII 0x0
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#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
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#define nCZMII 0x0
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#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
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#define nCZMEII 0x0
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#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
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#define nCZMZII 0x0
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/* Bit masks for CNT_COMMAND */
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#define W1LCNT 0xf /* Load Counter Register */
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#define W1LMIN 0xf0 /* Load Min Register */
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#define W1LMAX 0xf00 /* Load Max Register */
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#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
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#define nW1ZMONCE 0x0
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/* Bit masks for CNT_DEBOUNCE */
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#define DPRESCALE 0xf /* Load Counter Register */
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/* CNT_COMMAND bit field options */
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#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
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#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
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#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
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#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
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#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
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#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
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#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
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#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
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#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
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/* CNT_CONFIG bit field options */
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#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
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#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
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#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
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#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
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#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
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#define BNDMODE_COMP 0x0000 /* boundary compare mode */
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#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
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#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
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#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
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/* Bit masks for SECURE_SYSSWT */
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#define EMUDABL 0x1 /* Emulation Disable. */
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@ -1589,114 +1589,6 @@
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#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
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/* Bit masks for CNT_CONFIG */
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#define CNTE 0x1 /* Counter Enable */
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#define nCNTE 0x0
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#define DEBE 0x2 /* Debounce Enable */
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#define nDEBE 0x0
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#define CDGINV 0x10 /* CDG Pin Polarity Invert */
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#define nCDGINV 0x0
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#define CUDINV 0x20 /* CUD Pin Polarity Invert */
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#define nCUDINV 0x0
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#define CZMINV 0x40 /* CZM Pin Polarity Invert */
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#define nCZMINV 0x0
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#define CNTMODE 0x700 /* Counter Operating Mode */
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#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
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#define nZMZC 0x0
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#define BNDMODE 0x3000 /* Boundary register Mode */
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#define INPDIS 0x8000 /* CUG and CDG Input Disable */
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#define nINPDIS 0x0
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/* Bit masks for CNT_IMASK */
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#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
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#define nICIE 0x0
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#define UCIE 0x2 /* Up count Interrupt Enable */
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#define nUCIE 0x0
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#define DCIE 0x4 /* Down count Interrupt Enable */
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#define nDCIE 0x0
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#define MINCIE 0x8 /* Min Count Interrupt Enable */
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#define nMINCIE 0x0
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#define MAXCIE 0x10 /* Max Count Interrupt Enable */
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#define nMAXCIE 0x0
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#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
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#define nCOV31IE 0x0
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#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
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#define nCOV15IE 0x0
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#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
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#define nCZEROIE 0x0
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#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
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#define nCZMIE 0x0
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#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
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#define nCZMEIE 0x0
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#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
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#define nCZMZIE 0x0
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/* Bit masks for CNT_STATUS */
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#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
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#define nICII 0x0
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#define UCII 0x2 /* Up count Interrupt Identifier */
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#define nUCII 0x0
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#define DCII 0x4 /* Down count Interrupt Identifier */
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#define nDCII 0x0
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#define MINCII 0x8 /* Min Count Interrupt Identifier */
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#define nMINCII 0x0
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#define MAXCII 0x10 /* Max Count Interrupt Identifier */
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#define nMAXCII 0x0
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#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
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#define nCOV31II 0x0
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#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
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#define nCOV15II 0x0
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#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
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#define nCZEROII 0x0
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#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
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#define nCZMII 0x0
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#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
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#define nCZMEII 0x0
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#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
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#define nCZMZII 0x0
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/* Bit masks for CNT_COMMAND */
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#define W1LCNT 0xf /* Load Counter Register */
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#define W1LMIN 0xf0 /* Load Min Register */
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#define W1LMAX 0xf00 /* Load Max Register */
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#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
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#define nW1ZMONCE 0x0
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/* Bit masks for CNT_DEBOUNCE */
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#define DPRESCALE 0xf /* Load Counter Register */
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/* CNT_COMMAND bit field options */
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#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
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#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
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#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
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#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
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#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
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#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
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#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
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#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
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#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
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/* CNT_CONFIG bit field options */
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#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
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#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
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#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
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#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
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#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
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#define BNDMODE_COMP 0x0000 /* boundary compare mode */
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#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
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#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
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#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
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/* Bit masks for SECURE_SYSSWT */
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#define EMUDABL 0x1 /* Emulation Disable. */
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@ -1958,57 +1958,6 @@
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#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
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#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
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/* Bit masks for CNT_CONFIG */
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#define CNTE 0x1 /* Counter Enable */
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#define DEBE 0x2 /* Debounce Enable */
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#define CDGINV 0x10 /* CDG Pin Polarity Invert */
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#define CUDINV 0x20 /* CUD Pin Polarity Invert */
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#define CZMINV 0x40 /* CZM Pin Polarity Invert */
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#define CNTMODE 0x700 /* Counter Operating Mode */
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#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
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#define BNDMODE 0x3000 /* Boundary register Mode */
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#define INPDIS 0x8000 /* CUG and CDG Input Disable */
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/* Bit masks for CNT_IMASK */
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#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
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#define UCIE 0x2 /* Up count Interrupt Enable */
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#define DCIE 0x4 /* Down count Interrupt Enable */
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#define MINCIE 0x8 /* Min Count Interrupt Enable */
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#define MAXCIE 0x10 /* Max Count Interrupt Enable */
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#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
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#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
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#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
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#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
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#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
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#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
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/* Bit masks for CNT_STATUS */
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#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
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#define UCII 0x2 /* Up count Interrupt Identifier */
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#define DCII 0x4 /* Down count Interrupt Identifier */
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#define MINCII 0x8 /* Min Count Interrupt Identifier */
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#define MAXCII 0x10 /* Max Count Interrupt Identifier */
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#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
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#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
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#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
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#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
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#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
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#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
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/* Bit masks for CNT_COMMAND */
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#define W1LCNT 0xf /* Load Counter Register */
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#define W1LMIN 0xf0 /* Load Min Register */
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#define W1LMAX 0xf00 /* Load Max Register */
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#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
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/* Bit masks for CNT_DEBOUNCE */
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#define DPRESCALE 0xf /* Load Counter Register */
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/* Bit masks for SECURE_SYSSWT */
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#define EMUDABL 0x1 /* Emulation Disable. */
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@ -2412,33 +2361,6 @@
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#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
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#define BCODE_NOBOOT 0x0030 /* always perform full boot */
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/* CNT_COMMAND bit field options */
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#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
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#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
|
||||
#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
|
||||
|
||||
#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
|
||||
#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
|
||||
#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
|
||||
|
||||
#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
|
||||
#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
|
||||
#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
|
||||
|
||||
/* CNT_CONFIG bit field options */
|
||||
|
||||
#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
|
||||
#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
|
||||
#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
|
||||
#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
|
||||
#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
|
||||
|
||||
#define BNDMODE_COMP 0x0000 /* boundary compare mode */
|
||||
#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
|
||||
#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
|
||||
#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
|
||||
|
||||
/* TMODE in TIMERx_CONFIG bit field options */
|
||||
|
||||
#define PWM_OUT 0x0001
|
||||
|
|
|
|||
Reference in New Issue