microblaze: Support unaligned address for put/get_user macros
This patch add support for cases where load/store instruction in put/get_user macro gets unaligned pointer to data and this address is not valid. I prevent all cases which can failed. I had to disable first stage of unaligned handler which is used only for noMMU kernel and the whole work is done when interrupt is enabled. You have enable HW support for detect unaligned access in Microblaze. This patch fixed three LTP tests: getpeername01, getsockname01, socketpair01 Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek
parent
94ad8eb854
commit
3863dbceac
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@ -74,6 +74,7 @@
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/signal.h>
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#include <asm/asm-offsets.h>
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/* Helpful Macros */
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@ -428,19 +429,9 @@ handle_unaligned_ex:
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mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
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nop
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_no_delayslot:
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#endif
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#ifdef CONFIG_MMU
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/* Check if unaligned address is last on a 4k page */
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andi r5, r4, 0xffc
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xori r5, r5, 0xffc
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bnei r5, _unaligned_ex2
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_unaligned_ex1:
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RESTORE_STATE;
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/* Another page must be accessed or physical address not in page table */
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bri unaligned_data_trap
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_unaligned_ex2:
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/* jump to high level unaligned handler */
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RESTORE_STATE;
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bri unaligned_data_trap
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#endif
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andi r6, r3, 0x3E0; /* Mask and extract the register operand */
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srl r6, r6; /* r6 >> 5 */
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@ -450,45 +441,6 @@ _no_delayslot:
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srl r6, r6;
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/* Store the register operand in a temporary location */
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sbi r6, r0, TOPHYS(ex_reg_op);
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#ifdef CONFIG_MMU
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/* Get physical address */
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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ori r5, r0, CONFIG_KERNEL_START
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cmpu r5, r4, r5
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bgti r5, _unaligned_ex3
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ori r5, r0, swapper_pg_dir
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bri _unaligned_ex4
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/* Get the PGD for the current thread. */
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_unaligned_ex3: /* user thread */
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addi r5 ,CURRENT_TASK, TOPHYS(0); /* get current task address */
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lwi r5, r5, TASK_THREAD + PGDIR
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_unaligned_ex4:
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tophys(r5,r5)
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BSRLI(r6,r4,20) /* Create L1 (pgdir/pmd) address */
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andi r6, r6, 0xffc
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/* Assume pgdir aligned on 4K boundary, no need for "andi r5,r5,0xfffff003" */
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or r5, r5, r6
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lwi r6, r5, 0 /* Get L1 entry */
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andi r5, r6, 0xfffff000 /* Extract L2 (pte) base address. */
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beqi r5, _unaligned_ex1 /* Bail if no table */
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tophys(r5,r5)
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BSRLI(r6,r4,10) /* Compute PTE address */
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andi r6, r6, 0xffc
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andi r5, r5, 0xfffff003
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or r5, r5, r6
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lwi r5, r5, 0 /* Get Linux PTE */
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andi r6, r5, _PAGE_PRESENT
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beqi r6, _unaligned_ex1 /* Bail if no page */
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andi r5, r5, 0xfffff000 /* Extract RPN */
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andi r4, r4, 0x00000fff /* Extract offset */
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or r4, r4, r5 /* Create physical address */
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#endif /* CONFIG_MMU */
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andi r6, r3, 0x400; /* Extract ESR[S] */
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bnei r6, ex_sw;
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@ -959,15 +911,15 @@ _unaligned_data_exception:
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andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
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ex_lw_vm:
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beqid r6, ex_lhw_vm;
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lbui r5, r4, 0; /* Exception address in r4 - delay slot */
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load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
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/* Load a word, byte-by-byte from destination address and save it in tmp space*/
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la r6, r0, ex_tmp_data_loc_0;
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sbi r5, r6, 0;
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lbui r5, r4, 1;
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load2: lbui r5, r4, 1;
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sbi r5, r6, 1;
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lbui r5, r4, 2;
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load3: lbui r5, r4, 2;
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sbi r5, r6, 2;
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lbui r5, r4, 3;
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load4: lbui r5, r4, 3;
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sbi r5, r6, 3;
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brid ex_lw_tail_vm;
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/* Get the destination register value into r3 - delay slot */
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@ -977,7 +929,7 @@ ex_lhw_vm:
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* save it in tmp space */
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la r6, r0, ex_tmp_data_loc_0;
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sbi r5, r6, 0;
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lbui r5, r4, 1;
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load5: lbui r5, r4, 1;
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sbi r5, r6, 1;
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lhui r3, r6, 0; /* Get the destination register value into r3 */
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ex_lw_tail_vm:
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@ -996,22 +948,53 @@ ex_sw_tail_vm:
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swi r3, r5, 0; /* Get the word - delay slot */
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/* Store the word, byte-by-byte into destination address */
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lbui r3, r5, 0;
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sbi r3, r4, 0;
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store1: sbi r3, r4, 0;
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lbui r3, r5, 1;
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sbi r3, r4, 1;
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store2: sbi r3, r4, 1;
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lbui r3, r5, 2;
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sbi r3, r4, 2;
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store3: sbi r3, r4, 2;
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lbui r3, r5, 3;
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brid ret_from_exc;
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sbi r3, r4, 3; /* Delay slot */
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store4: sbi r3, r4, 3; /* Delay slot */
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ex_shw_vm:
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/* Store the lower half-word, byte-by-byte into destination address */
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lbui r3, r5, 2;
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sbi r3, r4, 0;
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store5: sbi r3, r4, 0;
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lbui r3, r5, 3;
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brid ret_from_exc;
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sbi r3, r4, 1; /* Delay slot */
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store6: sbi r3, r4, 1; /* Delay slot */
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ex_sw_end_vm: /* Exception handling of store word, ends. */
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/* We have to prevent cases that get/put_user macros get unaligned pointer
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* to bad page area. We have to find out which origin instruction caused it
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* and called fixup for that origin instruction not instruction in unaligned
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* handler */
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ex_unaligned_fixup:
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ori r5, r7, 0 /* setup pointer to pt_regs */
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lwi r6, r7, PT_PC; /* faulting address is one instruction above */
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addik r6, r6, -4 /* for finding proper fixup */
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swi r6, r7, PT_PC; /* a save back it to PT_PC */
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addik r7, r0, SIGSEGV
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/* call bad_page_fault for finding aligned fixup, fixup address is saved
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* in PT_PC which is used as return address from exception */
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la r15, r0, ret_from_exc-8 /* setup return address */
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brid bad_page_fault
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nop
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/* We prevent all load/store because it could failed any attempt to access */
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.section __ex_table,"a";
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.word load1,ex_unaligned_fixup;
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.word load2,ex_unaligned_fixup;
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.word load3,ex_unaligned_fixup;
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.word load4,ex_unaligned_fixup;
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.word load5,ex_unaligned_fixup;
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.word store1,ex_unaligned_fixup;
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.word store2,ex_unaligned_fixup;
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.word store3,ex_unaligned_fixup;
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.word store4,ex_unaligned_fixup;
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.word store5,ex_unaligned_fixup;
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.word store6,ex_unaligned_fixup;
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.previous;
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.end _unaligned_data_exception
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#endif /* CONFIG_MMU */
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@ -69,7 +69,7 @@ static int store_updates_sp(struct pt_regs *regs)
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* It is called from do_page_fault above and from some of the procedures
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* in traps.c.
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*/
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static void bad_page_fault(struct pt_regs *regs, unsigned long address, int sig)
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void bad_page_fault(struct pt_regs *regs, unsigned long address, int sig)
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{
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const struct exception_table_entry *fixup;
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/* MS: no context */
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