Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next: sparc32: remove unused file: include/asm/pgtsun4.h sparc32: fix PAGE_SIZE definition sparc32: enable different preemptions models sparc32: support atomic64_t apbuart: fix section mismatch warning sparc32: drop useless preprocessor conditional in atomic_32.h sparc32: drop unused atomic24 support
This commit is contained in:
Linus Torvalds
commit
37cfc3f67d
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@ -31,6 +31,7 @@ config SPARC
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config SPARC32
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def_bool !64BIT
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select GENERIC_ATOMIC64
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config SPARC64
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def_bool 64BIT
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@ -383,9 +384,7 @@ config SCHED_MC
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making when dealing with multi-core CPU chips at a cost of slightly
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increased overhead in some places. If unsure say N here.
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if SPARC64
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source "kernel/Kconfig.preempt"
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endif
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config CMDLINE_BOOL
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bool "Default bootloader kernel arguments"
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@ -13,7 +13,7 @@
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#include <linux/types.h>
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#ifdef __KERNEL__
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#include <asm-generic/atomic64.h>
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#include <asm/system.h>
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@ -52,112 +52,10 @@ extern void atomic_set(atomic_t *, int);
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#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
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#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
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/* This is the old 24-bit implementation. It's still used internally
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* by some sparc-specific code, notably the semaphore implementation.
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*/
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typedef struct { volatile int counter; } atomic24_t;
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#ifndef CONFIG_SMP
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#define ATOMIC24_INIT(i) { (i) }
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#define atomic24_read(v) ((v)->counter)
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#define atomic24_set(v, i) (((v)->counter) = i)
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#else
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/* We do the bulk of the actual work out of line in two common
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* routines in assembler, see arch/sparc/lib/atomic.S for the
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* "fun" details.
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*
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* For SMP the trick is you embed the spin lock byte within
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* the word, use the low byte so signedness is easily retained
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* via a quick arithmetic shift. It looks like this:
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*
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* ----------------------------------------
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* | signed 24-bit counter value | lock | atomic_t
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* ----------------------------------------
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* 31 8 7 0
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*/
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#define ATOMIC24_INIT(i) { ((i) << 8) }
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static inline int atomic24_read(const atomic24_t *v)
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{
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int ret = v->counter;
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while(ret & 0xff)
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ret = v->counter;
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return ret >> 8;
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}
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#define atomic24_set(v, i) (((v)->counter) = ((i) << 8))
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#endif
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static inline int __atomic24_add(int i, atomic24_t *v)
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{
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register volatile int *ptr asm("g1");
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register int increment asm("g2");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g7");
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ptr = &v->counter;
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increment = i;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___atomic24_add\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
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: "0" (increment), "r" (ptr)
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: "memory", "cc");
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return increment;
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}
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static inline int __atomic24_sub(int i, atomic24_t *v)
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{
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register volatile int *ptr asm("g1");
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register int increment asm("g2");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g7");
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ptr = &v->counter;
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increment = i;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___atomic24_sub\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
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: "0" (increment), "r" (ptr)
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: "memory", "cc");
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return increment;
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}
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#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))
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#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))
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#define atomic24_dec_return(v) __atomic24_sub(1, (v))
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#define atomic24_inc_return(v) __atomic24_add(1, (v))
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#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)
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#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)
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#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))
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#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))
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#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)
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/* Atomic operations are already serializing */
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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#endif /* !(__KERNEL__) */
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#endif /* !(__ARCH_SPARC_ATOMIC__) */
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@ -8,14 +8,10 @@
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#ifndef _SPARC_PAGE_H
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#define _SPARC_PAGE_H
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#define PAGE_SHIFT 12
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#include <linux/const.h>
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#ifndef __ASSEMBLY__
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/* I have my suspicions... -DaveM */
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#define PAGE_SIZE (1UL << PAGE_SHIFT)
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#else
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#endif
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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#include <asm/btfixup.h>
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@ -1,171 +0,0 @@
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/*
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* pgtsun4.h: Sun4 specific pgtable.h defines and code.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#ifndef _SPARC_PGTSUN4C_H
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#define _SPARC_PGTSUN4C_H
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#include <asm/contregs.h>
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/* PMD_SHIFT determines the size of the area a second-level page table can map */
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#define SUN4C_PMD_SHIFT 23
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define SUN4C_PGDIR_SHIFT 23
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#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT)
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#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1))
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#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
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/* To represent how the sun4c mmu really lays things out. */
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#define SUN4C_REAL_PGDIR_SHIFT 18
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#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT)
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#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1))
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#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
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/* 19 bit PFN on sun4 */
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#define SUN4C_PFN_MASK 0x7ffff
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/* Don't increase these unless the structures in sun4c.c are fixed */
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#define SUN4C_MAX_SEGMAPS 256
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#define SUN4C_MAX_CONTEXTS 16
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/*
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* To be efficient, and not have to worry about allocating such
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* a huge pgd, we make the kernel sun4c tables each hold 1024
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* entries and the pgd similarly just like the i386 tables.
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*/
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#define SUN4C_PTRS_PER_PTE 1024
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#define SUN4C_PTRS_PER_PMD 1
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#define SUN4C_PTRS_PER_PGD 1024
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/*
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* Sparc SUN4C pte fields.
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*/
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#define _SUN4C_PAGE_VALID 0x80000000
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#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */
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#define _SUN4C_PAGE_DIRTY 0x40000000
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#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */
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#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */
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#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */
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#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */
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#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */
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#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */
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#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */
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#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */
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#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */
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#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */
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#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
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_SUN4C_PAGE_ACCESSED)
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#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
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_SUN4C_PAGE_MODIFIED)
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#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
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#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT)
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#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
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_SUN4C_PAGE_WRITE)
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#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
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#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
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#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
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_SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
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/* SUN4C swap entry encoding
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*
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* We use 5 bits for the type and 19 for the offset. This gives us
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* 32 swapfiles of 4GB each. Encoding looks like:
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*
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* RRRRRRRRooooooooooooooooooottttt
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* fedcba9876543210fedcba9876543210
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*
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* The top 8 bits are reserved for protection and status bits, especially
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* FILE and PRESENT.
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*/
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#define SUN4C_SWP_TYPE_MASK 0x1f
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#define SUN4C_SWP_OFF_MASK 0x7ffff
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#define SUN4C_SWP_OFF_SHIFT 5
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#ifndef __ASSEMBLY__
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static inline unsigned long sun4c_get_synchronous_error(void)
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{
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unsigned long sync_err;
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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"=r" (sync_err) :
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"r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
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return sync_err;
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}
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static inline unsigned long sun4c_get_synchronous_address(void)
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{
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unsigned long sync_addr;
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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"=r" (sync_addr) :
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"r" (AC_SYNC_VA), "i" (ASI_CONTROL));
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return sync_addr;
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}
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/* SUN4 pte, segmap, and context manipulation */
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static inline unsigned long sun4c_get_segmap(unsigned long addr)
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{
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register unsigned long entry;
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__asm__ __volatile__("\n\tlduha [%1] %2, %0\n\t" :
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"=r" (entry) :
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"r" (addr), "i" (ASI_SEGMAP));
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return entry;
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}
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static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
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{
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__asm__ __volatile__("\n\tstha %1, [%0] %2; nop; nop; nop;\n\t" : :
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"r" (addr), "r" (entry),
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"i" (ASI_SEGMAP)
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: "memory");
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}
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static inline unsigned long sun4c_get_pte(unsigned long addr)
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{
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register unsigned long entry;
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__asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
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"=r" (entry) :
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"r" (addr), "i" (ASI_PTE));
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return entry;
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}
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static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
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{
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__asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
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"r" (addr),
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"r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
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: "memory");
|
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}
|
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|
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static inline int sun4c_get_context(void)
|
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{
|
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register int ctx;
|
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|
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__asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
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"=r" (ctx) :
|
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"r" (AC_CONTEXT), "i" (ASI_CONTROL));
|
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|
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return ctx;
|
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}
|
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|
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static inline int sun4c_set_context(int ctx)
|
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{
|
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__asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
|
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"r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
|
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: "memory");
|
||||
|
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return ctx;
|
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}
|
||||
|
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#endif /* !(__ASSEMBLY__) */
|
||||
|
||||
#endif /* !(_SPARC_PGTSUN4_H) */
|
||||
|
|
@ -95,7 +95,7 @@ BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *)
|
|||
* Observe the order of get_free_pages() in alloc_thread_info_node().
|
||||
* The sun4 has 8K stack too, because it's short on memory, and 16K is a waste.
|
||||
*/
|
||||
#define THREAD_SIZE 8192
|
||||
#define THREAD_SIZE (2 * PAGE_SIZE)
|
||||
|
||||
/*
|
||||
* Offsets in thread_info structure, used in assembly code
|
||||
|
|
|
|||
|
|
@ -40,60 +40,5 @@ ___xchg32_sun4md:
|
|||
mov %g4, %o7
|
||||
#endif
|
||||
|
||||
/* Read asm-sparc/atomic.h carefully to understand how this works for SMP.
|
||||
* Really, some things here for SMP are overly clever, go read the header.
|
||||
*/
|
||||
.globl ___atomic24_add
|
||||
___atomic24_add:
|
||||
rd %psr, %g3 ! Keep the code small, old way was stupid
|
||||
nop; nop; nop; ! Let the bits set
|
||||
or %g3, PSR_PIL, %g7 ! Disable interrupts
|
||||
wr %g7, 0x0, %psr ! Set %psr
|
||||
nop; nop; nop; ! Let the bits set
|
||||
#ifdef CONFIG_SMP
|
||||
1: ldstub [%g1 + 3], %g7 ! Spin on the byte lock for SMP.
|
||||
orcc %g7, 0x0, %g0 ! Did we get it?
|
||||
bne 1b ! Nope...
|
||||
ld [%g1], %g7 ! Load locked atomic24_t
|
||||
sra %g7, 8, %g7 ! Get signed 24-bit integer
|
||||
add %g7, %g2, %g2 ! Add in argument
|
||||
sll %g2, 8, %g7 ! Transpose back to atomic24_t
|
||||
st %g7, [%g1] ! Clever: This releases the lock as well.
|
||||
#else
|
||||
ld [%g1], %g7 ! Load locked atomic24_t
|
||||
add %g7, %g2, %g2 ! Add in argument
|
||||
st %g2, [%g1] ! Store it back
|
||||
#endif
|
||||
wr %g3, 0x0, %psr ! Restore original PSR_PIL
|
||||
nop; nop; nop; ! Let the bits set
|
||||
jmpl %o7, %g0 ! NOTE: not + 8, see callers in atomic.h
|
||||
mov %g4, %o7 ! Restore %o7
|
||||
|
||||
.globl ___atomic24_sub
|
||||
___atomic24_sub:
|
||||
rd %psr, %g3 ! Keep the code small, old way was stupid
|
||||
nop; nop; nop; ! Let the bits set
|
||||
or %g3, PSR_PIL, %g7 ! Disable interrupts
|
||||
wr %g7, 0x0, %psr ! Set %psr
|
||||
nop; nop; nop; ! Let the bits set
|
||||
#ifdef CONFIG_SMP
|
||||
1: ldstub [%g1 + 3], %g7 ! Spin on the byte lock for SMP.
|
||||
orcc %g7, 0x0, %g0 ! Did we get it?
|
||||
bne 1b ! Nope...
|
||||
ld [%g1], %g7 ! Load locked atomic24_t
|
||||
sra %g7, 8, %g7 ! Get signed 24-bit integer
|
||||
sub %g7, %g2, %g2 ! Subtract argument
|
||||
sll %g2, 8, %g7 ! Transpose back to atomic24_t
|
||||
st %g7, [%g1] ! Clever: This releases the lock as well
|
||||
#else
|
||||
ld [%g1], %g7 ! Load locked atomic24_t
|
||||
sub %g7, %g2, %g2 ! Subtract argument
|
||||
st %g2, [%g1] ! Store it back
|
||||
#endif
|
||||
wr %g3, 0x0, %psr ! Restore original PSR_PIL
|
||||
nop; nop; nop; ! Let the bits set
|
||||
jmpl %o7, %g0 ! NOTE: not + 8, see callers in atomic.h
|
||||
mov %g4, %o7 ! Restore %o7
|
||||
|
||||
.globl __atomic_end
|
||||
__atomic_end:
|
||||
|
|
|
|||
|
|
@ -62,8 +62,6 @@ extern void ___rw_read_enter(void);
|
|||
extern void ___rw_read_try(void);
|
||||
extern void ___rw_read_exit(void);
|
||||
extern void ___rw_write_enter(void);
|
||||
extern void ___atomic24_add(void);
|
||||
extern void ___atomic24_sub(void);
|
||||
|
||||
/* Alias functions whose names begin with "." and export the aliases.
|
||||
* The module references will be fixed up by module_frob_arch_sections.
|
||||
|
|
@ -97,10 +95,6 @@ EXPORT_SYMBOL(___rw_read_exit);
|
|||
EXPORT_SYMBOL(___rw_write_enter);
|
||||
#endif
|
||||
|
||||
/* Atomic operations. */
|
||||
EXPORT_SYMBOL(___atomic24_add);
|
||||
EXPORT_SYMBOL(___atomic24_sub);
|
||||
|
||||
EXPORT_SYMBOL(__ashrdi3);
|
||||
EXPORT_SYMBOL(__ashldi3);
|
||||
EXPORT_SYMBOL(__lshrdi3);
|
||||
|
|
|
|||
|
|
@ -577,7 +577,7 @@ static int __devinit apbuart_probe(struct platform_device *op)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id __initdata apbuart_match[] = {
|
||||
static struct of_device_id apbuart_match[] = {
|
||||
{
|
||||
.name = "GAISLER_APBUART",
|
||||
},
|
||||
|
|
@ -597,7 +597,7 @@ static struct platform_driver grlib_apbuart_of_driver = {
|
|||
};
|
||||
|
||||
|
||||
static int grlib_apbuart_configure(void)
|
||||
static int __init grlib_apbuart_configure(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
int line = 0;
|
||||
|
|
|
|||
Reference in New Issue