x86, perf_counter, bts: Add BTS support to perfcounters
Implement a performance counter with:
attr.type = PERF_TYPE_HARDWARE
attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS
attr.sample_period = 1
Using branch trace store (BTS) on x86 hardware, if available.
The from and to address for each branch can be sampled using:
PERF_SAMPLE_IP for the from address
PERF_SAMPLE_ADDR for the to address
[ v2: address review feedback, fix bugs ]
Signed-off-by: Markus Metzger <markus.t.metzger@intel.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Markus Metzger
Ingo Molnar
parent
183f3b0887
commit
30dd568c91
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@ -84,6 +84,16 @@ union cpuid10_edx {
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#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
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#define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2)
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/*
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* We model BTS tracing as another fixed-mode PMC.
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*
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* We choose a value in the middle of the fixed counter range, since lower
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* values are used by actual fixed counters and higher values are used
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* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
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*/
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#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
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#ifdef CONFIG_PERF_COUNTERS
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extern void init_hw_perf_counters(void);
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extern void perf_counters_lapic_init(void);
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@ -6,6 +6,7 @@
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* Copyright (C) 2009 Jaswinder Singh Rajput
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* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
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* Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
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* Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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*
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* For licencing details see kernel-base/COPYING
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*/
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@ -20,6 +21,7 @@
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#include <linux/sched.h>
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#include <linux/uaccess.h>
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#include <linux/highmem.h>
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#include <linux/cpu.h>
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#include <asm/apic.h>
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#include <asm/stacktrace.h>
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@ -27,12 +29,52 @@
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static u64 perf_counter_mask __read_mostly;
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/* The maximal number of PEBS counters: */
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#define MAX_PEBS_COUNTERS 4
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/* The size of a BTS record in bytes: */
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#define BTS_RECORD_SIZE 24
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/* The size of a per-cpu BTS buffer in bytes: */
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#define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 1024)
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/* The BTS overflow threshold in bytes from the end of the buffer: */
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#define BTS_OVFL_TH (BTS_RECORD_SIZE * 64)
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/*
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* Bits in the debugctlmsr controlling branch tracing.
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*/
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#define X86_DEBUGCTL_TR (1 << 6)
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#define X86_DEBUGCTL_BTS (1 << 7)
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#define X86_DEBUGCTL_BTINT (1 << 8)
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#define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
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#define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
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/*
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* A debug store configuration.
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*
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* We only support architectures that use 64bit fields.
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*/
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struct debug_store {
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u64 bts_buffer_base;
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u64 bts_index;
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u64 bts_absolute_maximum;
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u64 bts_interrupt_threshold;
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u64 pebs_buffer_base;
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u64 pebs_index;
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u64 pebs_absolute_maximum;
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u64 pebs_interrupt_threshold;
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u64 pebs_counter_reset[MAX_PEBS_COUNTERS];
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};
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struct cpu_hw_counters {
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struct perf_counter *counters[X86_PMC_IDX_MAX];
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unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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unsigned long interrupts;
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int enabled;
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struct debug_store *ds;
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};
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/*
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@ -57,6 +99,8 @@ struct x86_pmu {
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u64 counter_mask;
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u64 max_period;
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u64 intel_ctrl;
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void (*enable_bts)(u64 config);
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void (*disable_bts)(void);
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};
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static struct x86_pmu x86_pmu __read_mostly;
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@ -576,6 +620,9 @@ x86_perf_counter_update(struct perf_counter *counter,
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u64 prev_raw_count, new_raw_count;
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s64 delta;
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if (idx == X86_PMC_IDX_FIXED_BTS)
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return 0;
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/*
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* Careful: an NMI might modify the previous counter value.
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*
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@ -659,10 +706,109 @@ static void release_pmc_hardware(void)
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enable_lapic_nmi_watchdog();
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}
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static inline bool bts_available(void)
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{
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return x86_pmu.enable_bts != NULL;
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}
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static inline void init_debug_store_on_cpu(int cpu)
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{
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struct debug_store *ds = per_cpu(cpu_hw_counters, cpu).ds;
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if (!ds)
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return;
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wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
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(u32)((u64)(long)ds), (u32)((u64)(long)ds >> 32));
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}
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static inline void fini_debug_store_on_cpu(int cpu)
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{
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if (!per_cpu(cpu_hw_counters, cpu).ds)
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return;
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wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
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}
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static void release_bts_hardware(void)
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{
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int cpu;
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if (!bts_available())
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return;
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get_online_cpus();
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for_each_online_cpu(cpu)
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fini_debug_store_on_cpu(cpu);
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for_each_possible_cpu(cpu) {
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struct debug_store *ds = per_cpu(cpu_hw_counters, cpu).ds;
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if (!ds)
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continue;
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per_cpu(cpu_hw_counters, cpu).ds = NULL;
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kfree((void *)(long)ds->bts_buffer_base);
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kfree(ds);
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}
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put_online_cpus();
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}
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static int reserve_bts_hardware(void)
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{
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int cpu, err = 0;
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if (!bts_available())
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return -EOPNOTSUPP;
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get_online_cpus();
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for_each_possible_cpu(cpu) {
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struct debug_store *ds;
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void *buffer;
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err = -ENOMEM;
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buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
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if (unlikely(!buffer))
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break;
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ds = kzalloc(sizeof(*ds), GFP_KERNEL);
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if (unlikely(!ds)) {
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kfree(buffer);
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break;
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}
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ds->bts_buffer_base = (u64)(long)buffer;
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ds->bts_index = ds->bts_buffer_base;
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ds->bts_absolute_maximum =
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ds->bts_buffer_base + BTS_BUFFER_SIZE;
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ds->bts_interrupt_threshold =
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ds->bts_absolute_maximum - BTS_OVFL_TH;
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per_cpu(cpu_hw_counters, cpu).ds = ds;
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err = 0;
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}
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if (err)
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release_bts_hardware();
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else {
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for_each_online_cpu(cpu)
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init_debug_store_on_cpu(cpu);
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}
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put_online_cpus();
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return err;
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}
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static void hw_perf_counter_destroy(struct perf_counter *counter)
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{
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if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
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release_pmc_hardware();
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release_bts_hardware();
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mutex_unlock(&pmc_reserve_mutex);
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}
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}
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@ -705,6 +851,42 @@ set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr)
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return 0;
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}
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static void intel_pmu_enable_bts(u64 config)
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{
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unsigned long debugctlmsr;
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debugctlmsr = get_debugctlmsr();
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debugctlmsr |= X86_DEBUGCTL_TR;
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debugctlmsr |= X86_DEBUGCTL_BTS;
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debugctlmsr |= X86_DEBUGCTL_BTINT;
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if (!(config & ARCH_PERFMON_EVENTSEL_OS))
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debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
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if (!(config & ARCH_PERFMON_EVENTSEL_USR))
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debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
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update_debugctlmsr(debugctlmsr);
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}
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static void intel_pmu_disable_bts(void)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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unsigned long debugctlmsr;
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if (!cpuc->ds)
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return;
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debugctlmsr = get_debugctlmsr();
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debugctlmsr &=
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~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
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X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
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update_debugctlmsr(debugctlmsr);
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}
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/*
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* Setup the hardware configuration for a given attr_type
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*/
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@ -721,9 +903,13 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
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err = 0;
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if (!atomic_inc_not_zero(&active_counters)) {
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mutex_lock(&pmc_reserve_mutex);
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if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
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err = -EBUSY;
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else
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if (atomic_read(&active_counters) == 0) {
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if (!reserve_pmc_hardware())
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err = -EBUSY;
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else
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reserve_bts_hardware();
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}
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if (!err)
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atomic_inc(&active_counters);
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mutex_unlock(&pmc_reserve_mutex);
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}
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@ -801,7 +987,18 @@ static void p6_pmu_disable_all(void)
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static void intel_pmu_disable_all(void)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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if (!cpuc->enabled)
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return;
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cpuc->enabled = 0;
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barrier();
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
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if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
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intel_pmu_disable_bts();
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}
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static void amd_pmu_disable_all(void)
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@ -859,7 +1056,25 @@ static void p6_pmu_enable_all(void)
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static void intel_pmu_enable_all(void)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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if (cpuc->enabled)
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return;
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cpuc->enabled = 1;
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barrier();
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
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if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
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struct perf_counter *counter =
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cpuc->counters[X86_PMC_IDX_FIXED_BTS];
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if (WARN_ON_ONCE(!counter))
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return;
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intel_pmu_enable_bts(counter->hw.config);
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}
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}
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static void amd_pmu_enable_all(void)
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@ -946,6 +1161,11 @@ p6_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
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static inline void
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intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
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{
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if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
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intel_pmu_disable_bts();
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return;
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}
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if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
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intel_pmu_disable_fixed(hwc, idx);
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return;
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@ -974,6 +1194,9 @@ x86_perf_counter_set_period(struct perf_counter *counter,
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s64 period = hwc->sample_period;
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int err, ret = 0;
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if (idx == X86_PMC_IDX_FIXED_BTS)
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return 0;
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/*
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* If we are way outside a reasoable range then just skip forward:
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*/
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@ -1056,6 +1279,14 @@ static void p6_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
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static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
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{
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if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
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if (!__get_cpu_var(cpu_hw_counters).enabled)
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return;
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intel_pmu_enable_bts(hwc->config);
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return;
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}
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if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
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intel_pmu_enable_fixed(hwc, idx);
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return;
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@ -1077,11 +1308,16 @@ fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
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{
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unsigned int event;
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event = hwc->config & ARCH_PERFMON_EVENT_MASK;
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if (unlikely((event ==
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x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
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(hwc->sample_period == 1)))
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return X86_PMC_IDX_FIXED_BTS;
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if (!x86_pmu.num_counters_fixed)
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return -1;
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event = hwc->config & ARCH_PERFMON_EVENT_MASK;
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if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS)))
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return X86_PMC_IDX_FIXED_INSTRUCTIONS;
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if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES)))
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@ -1102,7 +1338,25 @@ static int x86_pmu_enable(struct perf_counter *counter)
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int idx;
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idx = fixed_mode_idx(counter, hwc);
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if (idx >= 0) {
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if (idx == X86_PMC_IDX_FIXED_BTS) {
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/*
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* Try to use BTS for branch tracing. If that is not
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* available, try to get a generic counter.
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*/
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if (unlikely(!cpuc->ds))
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goto try_generic;
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/*
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* Try to get the fixed counter, if that is already taken
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* then try to get a generic counter:
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*/
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if (test_and_set_bit(idx, cpuc->used_mask))
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goto try_generic;
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hwc->config_base = 0;
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hwc->counter_base = 0;
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hwc->idx = idx;
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} else if (idx >= 0) {
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/*
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* Try to get the fixed counter, if that is already taken
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* then try to get a generic counter:
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@ -1213,6 +1467,45 @@ void perf_counter_print_debug(void)
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local_irq_restore(flags);
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}
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static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc,
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struct perf_sample_data *data)
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{
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struct debug_store *ds = cpuc->ds;
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struct bts_record {
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u64 from;
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u64 to;
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u64 flags;
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};
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struct perf_counter *counter = cpuc->counters[X86_PMC_IDX_FIXED_BTS];
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unsigned long orig_ip = data->regs->ip;
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u64 at;
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if (!counter)
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return;
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if (!ds)
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return;
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for (at = ds->bts_buffer_base;
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at < ds->bts_index;
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at += sizeof(struct bts_record)) {
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struct bts_record *rec = (struct bts_record *)(long)at;
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data->regs->ip = rec->from;
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data->addr = rec->to;
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perf_counter_output(counter, 1, data);
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}
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ds->bts_index = ds->bts_buffer_base;
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data->regs->ip = orig_ip;
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data->addr = 0;
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/* There's new data available. */
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counter->pending_kill = POLL_IN;
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}
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static void x86_pmu_disable(struct perf_counter *counter)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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@ -1237,6 +1530,15 @@ static void x86_pmu_disable(struct perf_counter *counter)
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* that we are disabling:
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*/
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x86_perf_counter_update(counter, hwc, idx);
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/* Drain the remaining BTS records. */
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if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
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struct perf_sample_data data;
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struct pt_regs regs;
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|
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data.regs = ®s;
|
||||
intel_pmu_drain_bts_buffer(cpuc, &data);
|
||||
}
|
||||
cpuc->counters[idx] = NULL;
|
||||
clear_bit(idx, cpuc->used_mask);
|
||||
|
||||
|
|
@ -1264,6 +1566,7 @@ static int intel_pmu_save_and_restart(struct perf_counter *counter)
|
|||
|
||||
static void intel_pmu_reset(void)
|
||||
{
|
||||
struct debug_store *ds = __get_cpu_var(cpu_hw_counters).ds;
|
||||
unsigned long flags;
|
||||
int idx;
|
||||
|
||||
|
|
@ -1281,6 +1584,8 @@ static void intel_pmu_reset(void)
|
|||
for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
|
||||
checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
|
||||
}
|
||||
if (ds)
|
||||
ds->bts_index = ds->bts_buffer_base;
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
|
@ -1346,6 +1651,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
|
|||
cpuc = &__get_cpu_var(cpu_hw_counters);
|
||||
|
||||
perf_disable();
|
||||
intel_pmu_drain_bts_buffer(cpuc, &data);
|
||||
status = intel_pmu_get_status();
|
||||
if (!status) {
|
||||
perf_enable();
|
||||
|
|
@ -1547,6 +1853,8 @@ static struct x86_pmu intel_pmu = {
|
|||
* the generic counter period:
|
||||
*/
|
||||
.max_period = (1ULL << 31) - 1,
|
||||
.enable_bts = intel_pmu_enable_bts,
|
||||
.disable_bts = intel_pmu_disable_bts,
|
||||
};
|
||||
|
||||
static struct x86_pmu amd_pmu = {
|
||||
|
|
@ -1936,3 +2244,8 @@ struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
|
|||
|
||||
return entry;
|
||||
}
|
||||
|
||||
void hw_perf_counter_setup_online(int cpu)
|
||||
{
|
||||
init_debug_store_on_cpu(cpu);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -692,6 +692,8 @@ struct perf_sample_data {
|
|||
|
||||
extern int perf_counter_overflow(struct perf_counter *counter, int nmi,
|
||||
struct perf_sample_data *data);
|
||||
extern void perf_counter_output(struct perf_counter *counter, int nmi,
|
||||
struct perf_sample_data *data);
|
||||
|
||||
/*
|
||||
* Return 1 for a software counter, 0 for a hardware counter
|
||||
|
|
|
|||
|
|
@ -88,6 +88,7 @@ void __weak hw_perf_disable(void) { barrier(); }
|
|||
void __weak hw_perf_enable(void) { barrier(); }
|
||||
|
||||
void __weak hw_perf_counter_setup(int cpu) { barrier(); }
|
||||
void __weak hw_perf_counter_setup_online(int cpu) { barrier(); }
|
||||
|
||||
int __weak
|
||||
hw_perf_group_sched_in(struct perf_counter *group_leader,
|
||||
|
|
@ -2630,7 +2631,7 @@ static u32 perf_counter_tid(struct perf_counter *counter, struct task_struct *p)
|
|||
return task_pid_nr_ns(p, counter->ns);
|
||||
}
|
||||
|
||||
static void perf_counter_output(struct perf_counter *counter, int nmi,
|
||||
void perf_counter_output(struct perf_counter *counter, int nmi,
|
||||
struct perf_sample_data *data)
|
||||
{
|
||||
int ret;
|
||||
|
|
@ -4566,6 +4567,11 @@ perf_cpu_notify(struct notifier_block *self, unsigned long action, void *hcpu)
|
|||
perf_counter_init_cpu(cpu);
|
||||
break;
|
||||
|
||||
case CPU_ONLINE:
|
||||
case CPU_ONLINE_FROZEN:
|
||||
hw_perf_counter_setup_online(cpu);
|
||||
break;
|
||||
|
||||
case CPU_DOWN_PREPARE:
|
||||
case CPU_DOWN_PREPARE_FROZEN:
|
||||
perf_counter_exit_cpu(cpu);
|
||||
|
|
@ -4590,6 +4596,8 @@ void __init perf_counter_init(void)
|
|||
{
|
||||
perf_cpu_notify(&perf_cpu_nb, (unsigned long)CPU_UP_PREPARE,
|
||||
(void *)(long)smp_processor_id());
|
||||
perf_cpu_notify(&perf_cpu_nb, (unsigned long)CPU_ONLINE,
|
||||
(void *)(long)smp_processor_id());
|
||||
register_cpu_notifier(&perf_cpu_nb);
|
||||
}
|
||||
|
||||
|
|
|
|||
Reference in New Issue