firewire: Generalize the iso transmit descriptor buffer logic.
The descriptor circular buffer logic used for iso transmission is useful for async transmit too, so pull the sharable logic out in a few standalone functions. Signed-off-by: Kristian Høgsberg <krh@redhat.com> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
This commit is contained in:
Kristian Høgsberg
Stefan Richter
parent
9aad812538
commit
30200739e6
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@ -75,6 +75,30 @@ struct ar_context {
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struct tasklet_struct tasklet;
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};
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struct context;
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typedef int (*descriptor_callback_t)(struct context *ctx,
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struct descriptor *d,
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struct descriptor *last);
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struct context {
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struct fw_ohci *ohci;
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u32 regs;
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struct descriptor *buffer;
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dma_addr_t buffer_bus;
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size_t buffer_size;
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struct descriptor *head_descriptor;
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struct descriptor *tail_descriptor;
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struct descriptor *tail_descriptor_last;
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struct descriptor *prev_descriptor;
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descriptor_callback_t callback;
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struct tasklet_struct tasklet;
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};
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struct at_context {
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struct fw_ohci *ohci;
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dma_addr_t descriptor_bus;
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@ -103,15 +127,7 @@ struct at_context {
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struct iso_context {
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struct fw_iso_context base;
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struct tasklet_struct tasklet;
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u32 regs;
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struct descriptor *buffer;
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dma_addr_t buffer_bus;
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struct descriptor *head_descriptor;
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struct descriptor *tail_descriptor;
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struct descriptor *tail_descriptor_last;
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struct descriptor *prev_descriptor;
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struct context context;
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};
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#define CONFIG_ROM_SIZE 1024
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@ -394,6 +410,154 @@ ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
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return 0;
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}
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static void context_tasklet(unsigned long data)
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{
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struct context *ctx = (struct context *) data;
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struct fw_ohci *ohci = ctx->ohci;
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struct descriptor *d, *last;
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u32 address;
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int z;
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dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
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ctx->buffer_size, DMA_TO_DEVICE);
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d = ctx->tail_descriptor;
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last = ctx->tail_descriptor_last;
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while (last->branch_address != 0) {
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address = le32_to_cpu(last->branch_address);
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z = address & 0xf;
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d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d;
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last = (z == 2) ? d : d + z - 1;
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if (!ctx->callback(ctx, d, last))
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break;
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ctx->tail_descriptor = d;
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ctx->tail_descriptor_last = last;
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}
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}
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static int
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context_init(struct context *ctx, struct fw_ohci *ohci,
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size_t buffer_size, u32 regs,
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descriptor_callback_t callback)
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{
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ctx->ohci = ohci;
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ctx->regs = regs;
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ctx->buffer_size = buffer_size;
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ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
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if (ctx->buffer == NULL)
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return -ENOMEM;
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tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
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ctx->callback = callback;
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ctx->buffer_bus =
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dma_map_single(ohci->card.device, ctx->buffer,
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buffer_size, DMA_TO_DEVICE);
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if (dma_mapping_error(ctx->buffer_bus)) {
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kfree(ctx->buffer);
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return -ENOMEM;
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}
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ctx->head_descriptor = ctx->buffer;
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ctx->prev_descriptor = ctx->buffer;
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ctx->tail_descriptor = ctx->buffer;
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ctx->tail_descriptor_last = ctx->buffer;
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/* We put a dummy descriptor in the buffer that has a NULL
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* branch address and looks like it's been sent. That way we
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* have a descriptor to append DMA programs to. Also, the
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* ring buffer invariant is that it always has at least one
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* element so that head == tail means buffer full. */
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memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
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ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
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ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
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ctx->head_descriptor++;
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return 0;
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}
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static void
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context_release(struct context *ctx)
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{
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struct fw_card *card = &ctx->ohci->card;
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dma_unmap_single(card->device, ctx->buffer_bus,
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ctx->buffer_size, DMA_TO_DEVICE);
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kfree(ctx->buffer);
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}
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static struct descriptor *
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context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
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{
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struct descriptor *d, *tail, *end;
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d = ctx->head_descriptor;
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tail = ctx->tail_descriptor;
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end = ctx->buffer + ctx->buffer_size / sizeof(struct descriptor);
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if (d + z <= tail) {
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goto has_space;
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} else if (d > tail && d + z <= end) {
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goto has_space;
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} else if (d > tail && ctx->buffer + z <= tail) {
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d = ctx->buffer;
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goto has_space;
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}
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return NULL;
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has_space:
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memset(d, 0, z * sizeof *d);
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*d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
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return d;
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}
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static void context_run(struct context *ctx, u32 cycle_match)
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{
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struct fw_ohci *ohci = ctx->ohci;
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reg_write(ohci, command_ptr(ctx->regs),
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le32_to_cpu(ctx->tail_descriptor_last->branch_address));
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reg_write(ohci, control_clear(ctx->regs), ~0);
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reg_write(ohci, control_set(ctx->regs), CONTEXT_RUN | cycle_match);
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flush_writes(ohci);
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}
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static void context_append(struct context *ctx,
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struct descriptor *d, int z, int extra)
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{
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dma_addr_t d_bus;
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d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
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ctx->head_descriptor = d + z + extra;
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ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
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ctx->prev_descriptor = z == 2 ? d : d + z - 1;
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dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
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ctx->buffer_size, DMA_TO_DEVICE);
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reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE);
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flush_writes(ctx->ohci);
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}
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static void context_stop(struct context *ctx)
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{
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u32 reg;
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reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN);
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reg = reg_read(ctx->ohci, control_set(ctx->regs));
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if (reg & CONTEXT_ACTIVE)
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fw_notify("Tried to stop context, but it is still active "
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"(0x%08x).\n", reg);
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}
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static void
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do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list)
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@ -852,7 +1016,7 @@ static irqreturn_t irq_handler(int irq, void *data)
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while (iso_event) {
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i = ffs(iso_event) - 1;
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tasklet_schedule(&ohci->ir_context_list[i].tasklet);
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tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
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iso_event &= ~(1 << i);
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}
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@ -861,7 +1025,7 @@ static irqreturn_t irq_handler(int irq, void *data)
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while (iso_event) {
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i = ffs(iso_event) - 1;
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tasklet_schedule(&ohci->it_context_list[i].tasklet);
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tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
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iso_event &= ~(1 << i);
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}
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@ -1085,64 +1249,41 @@ static void ir_context_tasklet(unsigned long data)
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#define ISO_BUFFER_SIZE (64 * 1024)
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static void flush_iso_context(struct iso_context *ctx)
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static int handle_it_packet(struct context *context,
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struct descriptor *d,
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struct descriptor *last)
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{
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struct fw_ohci *ohci = fw_ohci(ctx->base.card);
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struct descriptor *d, *last;
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u32 address;
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int z;
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struct iso_context *ctx =
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container_of(context, struct iso_context, context);
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if (last->transfer_status == 0)
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/* This descriptor isn't done yet, stop iteration. */
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return 0;
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dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
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ISO_BUFFER_SIZE, DMA_TO_DEVICE);
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if (le16_to_cpu(last->control) & descriptor_irq_always)
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ctx->base.callback(&ctx->base,
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0, le16_to_cpu(last->res_count),
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ctx->base.callback_data);
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d = ctx->tail_descriptor;
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last = ctx->tail_descriptor_last;
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while (last->branch_address != 0 && last->transfer_status != 0) {
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address = le32_to_cpu(last->branch_address);
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z = address & 0xf;
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d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d;
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if (z == 2)
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last = d;
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else
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last = d + z - 1;
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if (le16_to_cpu(last->control) & descriptor_irq_always)
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ctx->base.callback(&ctx->base,
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0, le16_to_cpu(last->res_count),
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ctx->base.callback_data);
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}
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ctx->tail_descriptor = d;
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ctx->tail_descriptor_last = last;
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return 1;
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}
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static void it_context_tasklet(unsigned long data)
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{
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struct iso_context *ctx = (struct iso_context *)data;
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flush_iso_context(ctx);
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}
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static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
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int type)
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static struct fw_iso_context *
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ohci_allocate_iso_context(struct fw_card *card, int type)
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{
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struct fw_ohci *ohci = fw_ohci(card);
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struct iso_context *ctx, *list;
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void (*tasklet) (unsigned long data);
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descriptor_callback_t callback;
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u32 *mask;
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unsigned long flags;
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int index;
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int index, retval;
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if (type == FW_ISO_CONTEXT_TRANSMIT) {
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mask = &ohci->it_context_mask;
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list = ohci->it_context_list;
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tasklet = it_context_tasklet;
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callback = handle_it_packet;
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} else {
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mask = &ohci->ir_context_mask;
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list = ohci->ir_context_list;
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tasklet = ir_context_tasklet;
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return ERR_PTR(-EINVAL);
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}
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spin_lock_irqsave(&ohci->lock, flags);
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@ -1156,50 +1297,22 @@ static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
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ctx = &list[index];
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memset(ctx, 0, sizeof *ctx);
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tasklet_init(&ctx->tasklet, tasklet, (unsigned long)ctx);
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ctx->buffer = kmalloc(ISO_BUFFER_SIZE, GFP_KERNEL);
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if (ctx->buffer == NULL)
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goto buffer_alloc_failed;
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ctx->buffer_bus =
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dma_map_single(card->device, ctx->buffer,
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ISO_BUFFER_SIZE, DMA_TO_DEVICE);
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if (dma_mapping_error(ctx->buffer_bus))
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goto buffer_map_failed;
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ctx->head_descriptor = ctx->buffer;
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ctx->prev_descriptor = ctx->buffer;
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ctx->tail_descriptor = ctx->buffer;
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ctx->tail_descriptor_last = ctx->buffer;
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/* We put a dummy descriptor in the buffer that has a NULL
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* branch address and looks like it's been sent. That way we
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* have a descriptor to append DMA programs to. Also, the
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* ring buffer invariant is that it always has at least one
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* element so that head == tail means buffer full. */
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memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
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ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
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ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
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ctx->head_descriptor++;
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retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
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OHCI1394_IsoXmitContextBase(index), callback);
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if (retval < 0) {
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spin_lock_irqsave(&ohci->lock, flags);
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*mask |= 1 << index;
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spin_unlock_irqrestore(&ohci->lock, flags);
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return ERR_PTR(retval);
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}
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return &ctx->base;
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buffer_map_failed:
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kfree(ctx->buffer);
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buffer_alloc_failed:
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spin_lock_irqsave(&ohci->lock, flags);
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*mask |= 1 << index;
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spin_unlock_irqrestore(&ohci->lock, flags);
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return ERR_PTR(-ENOMEM);
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}
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static int ohci_send_iso(struct fw_iso_context *base, s32 cycle)
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{
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struct iso_context *ctx = (struct iso_context *)base;
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struct fw_ohci *ohci = fw_ohci(ctx->base.card);
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struct iso_context *ctx = container_of(base, struct iso_context, base);
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struct fw_ohci *ohci = ctx->context.ohci;
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u32 cycle_match = 0;
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int index;
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@ -1209,12 +1322,7 @@ static int ohci_send_iso(struct fw_iso_context *base, s32 cycle)
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(cycle & 0x7fff) << 16;
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reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
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reg_write(ohci, OHCI1394_IsoXmitCommandPtr(index),
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le32_to_cpu(ctx->tail_descriptor_last->branch_address));
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reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0);
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reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index),
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CONTEXT_RUN | cycle_match);
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flush_writes(ohci);
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context_run(&ctx->context, cycle_match);
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return 0;
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}
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@ -1222,12 +1330,10 @@ static int ohci_send_iso(struct fw_iso_context *base, s32 cycle)
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static void ohci_free_iso_context(struct fw_iso_context *base)
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{
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struct fw_ohci *ohci = fw_ohci(base->card);
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struct iso_context *ctx = (struct iso_context *)base;
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struct iso_context *ctx = container_of(base, struct iso_context, base);
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unsigned long flags;
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int index;
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flush_iso_context(ctx);
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spin_lock_irqsave(&ohci->lock, flags);
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if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
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@ -1243,8 +1349,7 @@ static void ohci_free_iso_context(struct fw_iso_context *base)
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}
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flush_writes(ohci);
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dma_unmap_single(ohci->card.device, ctx->buffer_bus,
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ISO_BUFFER_SIZE, DMA_TO_DEVICE);
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context_release(&ctx->context);
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spin_unlock_irqrestore(&ohci->lock, flags);
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}
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@ -1255,24 +1360,20 @@ ohci_queue_iso(struct fw_iso_context *base,
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struct fw_iso_buffer *buffer,
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unsigned long payload)
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{
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struct iso_context *ctx = (struct iso_context *)base;
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struct fw_ohci *ohci = fw_ohci(ctx->base.card);
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struct descriptor *d, *end, *last, *tail, *pd;
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struct iso_context *ctx = container_of(base, struct iso_context, base);
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struct descriptor *d, *last, *pd;
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struct fw_iso_packet *p;
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__le32 *header;
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dma_addr_t d_bus, page_bus;
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u32 z, header_z, payload_z, irq;
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u32 payload_index, payload_end_index, next_page_index;
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int index, page, end_page, i, length, offset;
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int page, end_page, i, length, offset;
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/* FIXME: Cycle lost behavior should be configurable: lose
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* packet, retransmit or terminate.. */
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p = packet;
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payload_index = payload;
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d = ctx->head_descriptor;
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tail = ctx->tail_descriptor;
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end = ctx->buffer + ISO_BUFFER_SIZE / sizeof(struct descriptor);
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if (p->skip)
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z = 1;
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@ -1293,21 +1394,9 @@ ohci_queue_iso(struct fw_iso_context *base,
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/* Get header size in number of descriptors. */
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header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
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if (d + z + header_z <= tail) {
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goto has_space;
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} else if (d > tail && d + z + header_z <= end) {
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goto has_space;
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} else if (d > tail && ctx->buffer + z + header_z <= tail) {
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d = ctx->buffer;
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goto has_space;
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}
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/* No space in buffer */
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return -1;
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has_space:
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memset(d, 0, (z + header_z) * sizeof *d);
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d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
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d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
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if (d == NULL)
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return -ENOMEM;
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if (!p->skip) {
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d[0].control = cpu_to_le16(descriptor_key_immediate);
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|
|
@ -1346,31 +1435,18 @@ ohci_queue_iso(struct fw_iso_context *base,
|
|||
payload_index += length;
|
||||
}
|
||||
|
||||
if (z == 2)
|
||||
last = d;
|
||||
else
|
||||
last = d + z - 1;
|
||||
|
||||
if (p->interrupt)
|
||||
irq = descriptor_irq_always;
|
||||
else
|
||||
irq = descriptor_no_irq;
|
||||
|
||||
last = z == 2 ? d : d + z - 1;
|
||||
last->control |= cpu_to_le16(descriptor_output_last |
|
||||
descriptor_status |
|
||||
descriptor_branch_always |
|
||||
irq);
|
||||
|
||||
dma_sync_single_for_device(ohci->card.device, ctx->buffer_bus,
|
||||
ISO_BUFFER_SIZE, DMA_TO_DEVICE);
|
||||
|
||||
ctx->head_descriptor = d + z + header_z;
|
||||
ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
|
||||
ctx->prev_descriptor = last;
|
||||
|
||||
index = ctx - ohci->it_context_list;
|
||||
reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index), CONTEXT_WAKE);
|
||||
flush_writes(ohci);
|
||||
context_append(&ctx->context, d, z, header_z);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Reference in New Issue