Staging: comedi: Checkpatch cleanups in adl_pci9111.c
This patch cleans up some various warnings generated from checkpatch.pl Signed-off-by: Mark Rankilor <reodge@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mark Rankilor
Greg Kroah-Hartman
parent
f25bd6bfdf
commit
2f6df34cd3
1 changed files with 59 additions and 46 deletions
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@ -68,8 +68,9 @@ CHANGELOG:
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TODO:
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- Really test implemented functionality.
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- Add support for the PCI-9111DG with a probe routine to identify the card type
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(perhaps with the help of the channel number readback of the A/D Data register).
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- Add support for the PCI-9111DG with a probe routine to identify the card
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type (perhaps with the help of the channel number readback of the A/D Data
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register).
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- Add external multiplexer support.
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*/
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@ -83,12 +84,12 @@ TODO:
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#include "comedi_pci.h"
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#include "comedi_fc.h"
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#define PCI9111_DRIVER_NAME "adl_pci9111"
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#define PCI9111_HR_DEVICE_ID 0x9111
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#define PCI9111_DRIVER_NAME "adl_pci9111"
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#define PCI9111_HR_DEVICE_ID 0x9111
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/* TODO: Add other pci9111 board id */
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#define PCI9111_IO_RANGE 0x0100
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#define PCI9111_IO_RANGE 0x0100
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#define PCI9111_FIFO_HALF_SIZE 512
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@ -134,27 +135,29 @@ TODO:
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/* IO address map */
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#define PCI9111_REGISTER_AD_FIFO_VALUE 0x00 /* AD Data stored in FIFO */
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#define PCI9111_REGISTER_DA_OUTPUT 0x00
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#define PCI9111_REGISTER_DIGITAL_IO 0x02
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#define PCI9111_REGISTER_EXTENDED_IO_PORTS 0x04
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#define PCI9111_REGISTER_AD_CHANNEL_CONTROL 0x06 /* Channel selection */
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#define PCI9111_REGISTER_AD_CHANNEL_READBACK 0x06
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#define PCI9111_REGISTER_INPUT_SIGNAL_RANGE 0x08
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#define PCI9111_REGISTER_RANGE_STATUS_READBACK 0x08
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#define PCI9111_REGISTER_TRIGGER_MODE_CONTROL 0x0A
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#define PCI9111_REGISTER_AD_MODE_INTERRUPT_READBACK 0x0A
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#define PCI9111_REGISTER_SOFTWARE_TRIGGER 0x0E
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#define PCI9111_REGISTER_INTERRUPT_CONTROL 0x0C
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#define PCI9111_REGISTER_AD_FIFO_VALUE 0x00 /* AD Data stored
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in FIFO */
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#define PCI9111_REGISTER_DA_OUTPUT 0x00
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#define PCI9111_REGISTER_DIGITAL_IO 0x02
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#define PCI9111_REGISTER_EXTENDED_IO_PORTS 0x04
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#define PCI9111_REGISTER_AD_CHANNEL_CONTROL 0x06 /* Channel
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selection */
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#define PCI9111_REGISTER_AD_CHANNEL_READBACK 0x06
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#define PCI9111_REGISTER_INPUT_SIGNAL_RANGE 0x08
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#define PCI9111_REGISTER_RANGE_STATUS_READBACK 0x08
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#define PCI9111_REGISTER_TRIGGER_MODE_CONTROL 0x0A
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#define PCI9111_REGISTER_AD_MODE_INTERRUPT_READBACK 0x0A
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#define PCI9111_REGISTER_SOFTWARE_TRIGGER 0x0E
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#define PCI9111_REGISTER_INTERRUPT_CONTROL 0x0C
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#define PCI9111_REGISTER_8254_COUNTER_0 0x40
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#define PCI9111_REGISTER_8254_COUNTER_1 0x42
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#define PCI9111_REGISTER_8254_COUNTER_2 0X44
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#define PCI9111_REGISTER_8254_COUNTER_2 0X44
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#define PCI9111_REGISTER_8254_CONTROL 0x46
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#define PCI9111_REGISTER_INTERRUPT_CLEAR 0x48
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#define PCI9111_REGISTER_INTERRUPT_CLEAR 0x48
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#define PCI9111_TRIGGER_MASK 0x0F
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#define PCI9111_PTRG_OFF (0 << 3)
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#define PCI9111_PTRG_ON (1 << 3)
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#define PCI9111_TRIGGER_MASK 0x0F
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#define PCI9111_PTRG_OFF (0 << 3)
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#define PCI9111_PTRG_ON (1 << 3)
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#define PCI9111_EITS_EXTERNAL (1 << 2)
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#define PCI9111_EITS_INTERNAL (0 << 2)
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#define PCI9111_TPST_SOFTWARE_TRIGGER (0 << 1)
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@ -164,9 +167,9 @@ TODO:
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#define PCI9111_ISC0_SET_IRQ_ON_ENDING_OF_AD_CONVERSION (0 << 0)
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#define PCI9111_ISC0_SET_IRQ_ON_FIFO_HALF_FULL (1 << 0)
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#define PCI9111_ISC1_SET_IRQ_ON_TIMER_TICK (0 << 1)
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#define PCI9111_ISC1_SET_IRQ_ON_EXT_TRG (1 << 1)
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#define PCI9111_FFEN_SET_FIFO_ENABLE (0 << 2)
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#define PCI9111_ISC1_SET_IRQ_ON_TIMER_TICK (0 << 1)
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#define PCI9111_ISC1_SET_IRQ_ON_EXT_TRG (1 << 1)
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#define PCI9111_FFEN_SET_FIFO_ENABLE (0 << 2)
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#define PCI9111_FFEN_SET_FIFO_DISABLE (1 << 2)
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#define PCI9111_CHANNEL_MASK 0x0F
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@ -177,7 +180,7 @@ TODO:
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#define PCI9111_FIFO_FULL_MASK 0x40
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#define PCI9111_AD_BUSY_MASK 0x80
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#define PCI9111_IO_BASE dev->iobase
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#define PCI9111_IO_BASE (dev->iobase)
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/*
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* Define inlined function
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@ -189,8 +192,9 @@ TODO:
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#define pci9111_trigger_and_autoscan_set(flags) \
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outb(flags, PCI9111_IO_BASE+PCI9111_REGISTER_TRIGGER_MODE_CONTROL)
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#define pci9111_interrupt_and_fifo_get() \
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((inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_MODE_INTERRUPT_READBACK) >> 4) &0x03)
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#define pci9111_interrupt_and_fifo_get() \
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((inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_MODE_INTERRUPT_READBACK) >> 4) \
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&0x03)
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#define pci9111_interrupt_and_fifo_set(flags) \
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outb(flags, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL)
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@ -201,38 +205,47 @@ TODO:
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#define pci9111_software_trigger() \
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outb(0, PCI9111_IO_BASE+PCI9111_REGISTER_SOFTWARE_TRIGGER)
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#define pci9111_fifo_reset() \
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outb(PCI9111_FFEN_SET_FIFO_ENABLE, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL); \
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outb(PCI9111_FFEN_SET_FIFO_DISABLE, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL); \
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outb(PCI9111_FFEN_SET_FIFO_ENABLE, PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL)
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#define pci9111_fifo_reset() do { \
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outb(PCI9111_FFEN_SET_FIFO_ENABLE, \
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PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL); \
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outb(PCI9111_FFEN_SET_FIFO_DISABLE, \
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PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL); \
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outb(PCI9111_FFEN_SET_FIFO_ENABLE, \
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PCI9111_IO_BASE+PCI9111_REGISTER_INTERRUPT_CONTROL); \
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} while (0)
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#define pci9111_is_fifo_full() \
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((inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)& \
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PCI9111_FIFO_FULL_MASK)==0)
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PCI9111_FIFO_FULL_MASK) == 0)
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#define pci9111_is_fifo_half_full() \
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((inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)& \
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PCI9111_FIFO_HALF_FULL_MASK)==0)
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PCI9111_FIFO_HALF_FULL_MASK) == 0)
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#define pci9111_is_fifo_empty() \
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((inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)& \
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PCI9111_FIFO_EMPTY_MASK)==0)
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PCI9111_FIFO_EMPTY_MASK) == 0)
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#define pci9111_ai_channel_set(channel) \
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outb((channel)&PCI9111_CHANNEL_MASK, PCI9111_IO_BASE+PCI9111_REGISTER_AD_CHANNEL_CONTROL)
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#define pci9111_ai_channel_set(channel) \
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outb((channel)&PCI9111_CHANNEL_MASK, \
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PCI9111_IO_BASE+PCI9111_REGISTER_AD_CHANNEL_CONTROL)
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#define pci9111_ai_channel_get() \
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inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_CHANNEL_READBACK)&PCI9111_CHANNEL_MASK
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#define pci9111_ai_channel_get() \
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(inb(PCI9111_IO_BASE+PCI9111_REGISTER_AD_CHANNEL_READBACK) \
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&PCI9111_CHANNEL_MASK)
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#define pci9111_ai_range_set(range) \
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outb((range)&PCI9111_RANGE_MASK, PCI9111_IO_BASE+PCI9111_REGISTER_INPUT_SIGNAL_RANGE)
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#define pci9111_ai_range_set(range) \
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outb((range)&PCI9111_RANGE_MASK, \
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PCI9111_IO_BASE+PCI9111_REGISTER_INPUT_SIGNAL_RANGE)
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#define pci9111_ai_range_get() \
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inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK)&PCI9111_RANGE_MASK
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#define pci9111_ai_range_get() \
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(inb(PCI9111_IO_BASE+PCI9111_REGISTER_RANGE_STATUS_READBACK) \
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&PCI9111_RANGE_MASK)
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#define pci9111_ai_get_data() \
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((inw(PCI9111_IO_BASE+PCI9111_REGISTER_AD_FIFO_VALUE)>>4)&PCI9111_AI_RESOLUTION_MASK) \
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^ PCI9111_AI_RESOLUTION_2_CMP_BIT
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#define pci9111_ai_get_data() \
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(((inw(PCI9111_IO_BASE+PCI9111_REGISTER_AD_FIFO_VALUE)>>4) \
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&PCI9111_AI_RESOLUTION_MASK) \
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^ PCI9111_AI_RESOLUTION_2_CMP_BIT)
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#define pci9111_hr_ai_get_data() \
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(inw(PCI9111_IO_BASE+PCI9111_REGISTER_AD_FIFO_VALUE) & PCI9111_HR_AI_RESOLUTION_MASK) \
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