x86: PAT infrastructure patch
Sets up pat_init() infrastructure. PAT MSR has following setting. PAT |PCD ||PWT ||| 000 WB _PAGE_CACHE_WB 001 WC _PAGE_CACHE_WC 010 UC- _PAGE_CACHE_UC_MINUS 011 UC _PAGE_CACHE_UC We are effectively changing WT from boot time setting to WC. UC_MINUS is used to provide backward compatibility to existing /dev/mem users(X). reserve_memtype and free_memtype are new interfaces for maintaining alias-free mapping. It is currently implemented in a simple way with a linked list and not optimized. reserve and free tracks the effective memory type, as a result of PAT and MTRR setting rather than what is actually requested in PAT. pat_init piggy backs on mtrr_init as the rules for setting both pat and mtrr are same. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
venkatesh.pallipadi@intel.com
Ingo Molnar
parent
d27554d874
commit
2e5d9c857d
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@ -1009,6 +1009,21 @@ config MTRR
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See <file:Documentation/mtrr.txt> for more information.
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config X86_PAT
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def_bool y
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prompt "x86 PAT support"
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depends on MTRR && NONPROMISC_DEVMEM
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help
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Use PAT attributes to setup page level cache control.
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---help---
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PATs are the modern equivalents of MTRRs and are much more
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flexible than MTRRs.
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Say N here if you see bootup problems (boot crash, boot hang,
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spontaneous reboots) or a non-working Xorg.
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If unsure, say Y.
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config EFI
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def_bool n
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prompt "EFI runtime service support"
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@ -11,6 +11,7 @@
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#include <asm/cpufeature.h>
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#include <asm/processor-flags.h>
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#include <asm/tlbflush.h>
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#include <asm/pat.h>
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#include "mtrr.h"
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struct mtrr_state {
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@ -35,6 +36,7 @@ static struct fixed_range_block fixed_range_blocks[] = {
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static unsigned long smp_changes_mask;
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static struct mtrr_state mtrr_state = {};
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static int mtrr_state_set;
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#undef MODULE_PARAM_PREFIX
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#define MODULE_PARAM_PREFIX "mtrr."
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@ -42,6 +44,106 @@ static struct mtrr_state mtrr_state = {};
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static int mtrr_show;
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module_param_named(show, mtrr_show, bool, 0);
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/*
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* Returns the effective MTRR type for the region
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* Error returns:
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* - 0xFE - when the range is "not entirely covered" by _any_ var range MTRR
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* - 0xFF - when MTRR is not enabled
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*/
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u8 mtrr_type_lookup(u64 start, u64 end)
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{
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int i;
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u64 base, mask;
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u8 prev_match, curr_match;
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if (!mtrr_state_set)
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return 0xFF;
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if (!mtrr_state.enabled)
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return 0xFF;
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/* Make end inclusive end, instead of exclusive */
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end--;
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/* Look in fixed ranges. Just return the type as per start */
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if (mtrr_state.have_fixed && (start < 0x100000)) {
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int idx;
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if (start < 0x80000) {
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idx = 0;
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idx += (start >> 16);
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return mtrr_state.fixed_ranges[idx];
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} else if (start < 0xC0000) {
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idx = 1 * 8;
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idx += ((start - 0x80000) >> 14);
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return mtrr_state.fixed_ranges[idx];
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} else if (start < 0x1000000) {
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idx = 3 * 8;
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idx += ((start - 0xC0000) >> 12);
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return mtrr_state.fixed_ranges[idx];
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}
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}
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/*
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* Look in variable ranges
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* Look of multiple ranges matching this address and pick type
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* as per MTRR precedence
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*/
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if (!mtrr_state.enabled & 2) {
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return mtrr_state.def_type;
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}
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prev_match = 0xFF;
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for (i = 0; i < num_var_ranges; ++i) {
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unsigned short start_state, end_state;
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if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11)))
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continue;
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base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) +
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(mtrr_state.var_ranges[i].base_lo & PAGE_MASK);
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mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) +
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(mtrr_state.var_ranges[i].mask_lo & PAGE_MASK);
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start_state = ((start & mask) == (base & mask));
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end_state = ((end & mask) == (base & mask));
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if (start_state != end_state)
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return 0xFE;
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if ((start & mask) != (base & mask)) {
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continue;
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}
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curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
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if (prev_match == 0xFF) {
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prev_match = curr_match;
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continue;
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}
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if (prev_match == MTRR_TYPE_UNCACHABLE ||
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curr_match == MTRR_TYPE_UNCACHABLE) {
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return MTRR_TYPE_UNCACHABLE;
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}
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if ((prev_match == MTRR_TYPE_WRBACK &&
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curr_match == MTRR_TYPE_WRTHROUGH) ||
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(prev_match == MTRR_TYPE_WRTHROUGH &&
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curr_match == MTRR_TYPE_WRBACK)) {
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prev_match = MTRR_TYPE_WRTHROUGH;
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curr_match = MTRR_TYPE_WRTHROUGH;
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}
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if (prev_match != curr_match) {
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return MTRR_TYPE_UNCACHABLE;
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}
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}
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if (prev_match != 0xFF)
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return prev_match;
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return mtrr_state.def_type;
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}
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/* Get the MSR pair relating to a var range */
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static void
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get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
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@ -79,12 +181,16 @@ static void print_fixed(unsigned base, unsigned step, const mtrr_type*types)
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base, base + step - 1, mtrr_attrib_to_str(*types));
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}
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static void prepare_set(void);
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static void post_set(void);
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/* Grab all of the MTRR state for this CPU into *state */
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void __init get_mtrr_state(void)
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{
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unsigned int i;
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struct mtrr_var_range *vrs;
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unsigned lo, dummy;
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unsigned long flags;
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vrs = mtrr_state.var_ranges;
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@ -131,6 +237,17 @@ void __init get_mtrr_state(void)
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printk(KERN_INFO "MTRR %u disabled\n", i);
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}
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}
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mtrr_state_set = 1;
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/* PAT setup for BP. We need to go through sync steps here */
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local_irq_save(flags);
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prepare_set();
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pat_init();
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post_set();
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local_irq_restore(flags);
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}
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/* Some BIOS's are fucked and don't set all MTRRs the same! */
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@ -397,6 +514,9 @@ static void generic_set_all(void)
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/* Actually set the state */
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mask = set_mtrr_state();
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/* also set PAT */
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pat_init();
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post_set();
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local_irq_restore(flags);
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@ -1,4 +1,5 @@
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obj-y := init_$(BITS).o fault.o ioremap.o extable.o pageattr.o mmap.o
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obj-y := init_$(BITS).o fault.o ioremap.o extable.o pageattr.o mmap.o \
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pat.o
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obj-$(CONFIG_X86_32) += pgtable_32.o
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@ -773,14 +773,14 @@ static inline int change_page_attr_clear(unsigned long addr, int numpages,
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int set_memory_uc(unsigned long addr, int numpages)
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{
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return change_page_attr_set(addr, numpages,
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__pgprot(_PAGE_PCD));
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__pgprot(_PAGE_CACHE_UC));
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}
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EXPORT_SYMBOL(set_memory_uc);
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int set_memory_wb(unsigned long addr, int numpages)
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{
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return change_page_attr_clear(addr, numpages,
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__pgprot(_PAGE_PCD | _PAGE_PWT));
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__pgprot(_PAGE_CACHE_MASK));
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}
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EXPORT_SYMBOL(set_memory_wb);
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@ -0,0 +1,402 @@
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/*
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* Handle caching attributes in page tables (PAT)
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*
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* Authors: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
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* Suresh B Siddha <suresh.b.siddha@intel.com>
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*
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* Loosely based on earlier PAT patchset from Eric Biederman and Andi Kleen.
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*/
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#include <linux/mm.h>
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#include <linux/kernel.h>
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#include <linux/gfp.h>
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#include <linux/fs.h>
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#include <asm/msr.h>
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#include <asm/tlbflush.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/pat.h>
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#include <asm/e820.h>
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#include <asm/cacheflush.h>
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#include <asm/fcntl.h>
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#include <asm/mtrr.h>
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int pat_wc_enabled = 1;
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static u64 __read_mostly boot_pat_state;
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static int nopat(char *str)
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{
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pat_wc_enabled = 0;
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printk(KERN_INFO "x86: PAT support disabled.\n");
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return 0;
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}
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early_param("nopat", nopat);
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static int pat_known_cpu(void)
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{
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if (!pat_wc_enabled)
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return 0;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
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(boot_cpu_data.x86 == 0xF ||
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(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model >= 15))) {
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if (cpu_has_pat) {
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return 1;
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}
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}
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pat_wc_enabled = 0;
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printk(KERN_INFO "CPU and/or kernel does not support PAT.\n");
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return 0;
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}
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enum {
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PAT_UC = 0, /* uncached */
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PAT_WC = 1, /* Write combining */
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PAT_WT = 4, /* Write Through */
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PAT_WP = 5, /* Write Protected */
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PAT_WB = 6, /* Write Back (default) */
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PAT_UC_MINUS = 7, /* UC, but can be overriden by MTRR */
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};
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#define PAT(x,y) ((u64)PAT_ ## y << ((x)*8))
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void pat_init(void)
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{
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u64 pat;
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#ifndef CONFIG_X86_PAT
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nopat(NULL);
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#endif
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/* Boot CPU enables PAT based on CPU feature */
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if (!smp_processor_id() && !pat_known_cpu())
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return;
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/* APs enable PAT iff boot CPU has enabled it before */
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if (smp_processor_id() && !pat_wc_enabled)
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return;
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/* Set PWT to Write-Combining. All other bits stay the same */
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/*
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* PTE encoding used in Linux:
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* PAT
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* |PCD
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* ||PWT
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* |||
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* 000 WB _PAGE_CACHE_WB
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* 001 WC _PAGE_CACHE_WC
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* 010 UC- _PAGE_CACHE_UC_MINUS
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* 011 UC _PAGE_CACHE_UC
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* PAT bit unused
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*/
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pat = PAT(0,WB) | PAT(1,WC) | PAT(2,UC_MINUS) | PAT(3,UC) |
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PAT(4,WB) | PAT(5,WC) | PAT(6,UC_MINUS) | PAT(7,UC);
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/* Boot CPU check */
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if (!smp_processor_id()) {
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rdmsrl(MSR_IA32_CR_PAT, boot_pat_state);
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}
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wrmsrl(MSR_IA32_CR_PAT, pat);
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printk(KERN_INFO "x86 PAT enabled: cpu %d, old 0x%Lx, new 0x%Lx\n",
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smp_processor_id(), boot_pat_state, pat);
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}
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#undef PAT
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static char *cattr_name(unsigned long flags)
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{
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switch (flags & _PAGE_CACHE_MASK) {
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case _PAGE_CACHE_UC: return "uncached";
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case _PAGE_CACHE_UC_MINUS: return "uncached-minus";
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case _PAGE_CACHE_WB: return "write-back";
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case _PAGE_CACHE_WC: return "write-combining";
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default: return "broken";
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}
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}
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/*
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* The global memtype list keeps track of memory type for specific
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* physical memory areas. Conflicting memory types in different
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* mappings can cause CPU cache corruption. To avoid this we keep track.
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*
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* The list is sorted based on starting address and can contain multiple
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* entries for each address (this allows reference counting for overlapping
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* areas). All the aliases have the same cache attributes of course.
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* Zero attributes are represented as holes.
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*
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* Currently the data structure is a list because the number of mappings
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* are expected to be relatively small. If this should be a problem
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* it could be changed to a rbtree or similar.
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*
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* memtype_lock protects the whole list.
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*/
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struct memtype {
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u64 start;
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u64 end;
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unsigned long type;
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struct list_head nd;
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};
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static LIST_HEAD(memtype_list);
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static DEFINE_SPINLOCK(memtype_lock); /* protects memtype list */
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/*
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* Does intersection of PAT memory type and MTRR memory type and returns
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* the resulting memory type as PAT understands it.
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* (Type in pat and mtrr will not have same value)
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* The intersection is based on "Effective Memory Type" tables in IA-32
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* SDM vol 3a
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*/
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static int pat_x_mtrr_type(u64 start, u64 end, unsigned long prot,
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unsigned long *ret_prot)
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{
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unsigned long pat_type;
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u8 mtrr_type;
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mtrr_type = mtrr_type_lookup(start, end);
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if (mtrr_type == 0xFF) { /* MTRR not enabled */
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*ret_prot = prot;
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return 0;
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}
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if (mtrr_type == 0xFE) { /* MTRR match error */
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*ret_prot = _PAGE_CACHE_UC;
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return -1;
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}
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if (mtrr_type != MTRR_TYPE_UNCACHABLE &&
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mtrr_type != MTRR_TYPE_WRBACK &&
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mtrr_type != MTRR_TYPE_WRCOMB) { /* MTRR type unhandled */
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*ret_prot = _PAGE_CACHE_UC;
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return -1;
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}
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pat_type = prot & _PAGE_CACHE_MASK;
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prot &= (~_PAGE_CACHE_MASK);
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/* Currently doing intersection by hand. Optimize it later. */
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if (pat_type == _PAGE_CACHE_WC) {
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*ret_prot = prot | _PAGE_CACHE_WC;
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} else if (pat_type == _PAGE_CACHE_UC_MINUS) {
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*ret_prot = prot | _PAGE_CACHE_UC_MINUS;
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} else if (pat_type == _PAGE_CACHE_UC ||
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mtrr_type == MTRR_TYPE_UNCACHABLE) {
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*ret_prot = prot | _PAGE_CACHE_UC;
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} else if (mtrr_type == MTRR_TYPE_WRCOMB) {
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*ret_prot = prot | _PAGE_CACHE_WC;
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} else {
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*ret_prot = prot | _PAGE_CACHE_WB;
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}
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return 0;
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}
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int reserve_memtype(u64 start, u64 end, unsigned long req_type,
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unsigned long *ret_type)
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{
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struct memtype *new_entry = NULL;
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struct memtype *parse;
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unsigned long actual_type;
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int err = 0;
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/* Only track when pat_wc_enabled */
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if (!pat_wc_enabled) {
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if (ret_type)
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*ret_type = req_type;
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return 0;
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}
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/* Low ISA region is always mapped WB in page table. No need to track */
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if (start >= ISA_START_ADDRESS && (end - 1) <= ISA_END_ADDRESS) {
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if (ret_type)
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*ret_type = _PAGE_CACHE_WB;
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return 0;
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}
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req_type &= _PAGE_CACHE_MASK;
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err = pat_x_mtrr_type(start, end, req_type, &actual_type);
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if (err) {
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if (ret_type)
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*ret_type = actual_type;
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return -EINVAL;
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}
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new_entry = kmalloc(sizeof(struct memtype), GFP_KERNEL);
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if (!new_entry)
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return -ENOMEM;
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new_entry->start = start;
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new_entry->end = end;
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new_entry->type = actual_type;
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if (ret_type)
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*ret_type = actual_type;
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spin_lock(&memtype_lock);
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/* Search for existing mapping that overlaps the current range */
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list_for_each_entry(parse, &memtype_list, nd) {
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struct memtype *saved_ptr;
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if (parse->start >= end) {
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list_add(&new_entry->nd, parse->nd.prev);
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new_entry = NULL;
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||||
break;
|
||||
}
|
||||
|
||||
if (start <= parse->start && end >= parse->start) {
|
||||
if (actual_type != parse->type && ret_type) {
|
||||
actual_type = parse->type;
|
||||
*ret_type = actual_type;
|
||||
new_entry->type = actual_type;
|
||||
}
|
||||
|
||||
if (actual_type != parse->type) {
|
||||
printk(
|
||||
KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
|
||||
current->comm, current->pid,
|
||||
start, end,
|
||||
cattr_name(actual_type),
|
||||
cattr_name(parse->type));
|
||||
err = -EBUSY;
|
||||
break;
|
||||
}
|
||||
|
||||
saved_ptr = parse;
|
||||
/*
|
||||
* Check to see whether the request overlaps more
|
||||
* than one entry in the list
|
||||
*/
|
||||
list_for_each_entry_continue(parse, &memtype_list, nd) {
|
||||
if (end <= parse->start) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (actual_type != parse->type) {
|
||||
printk(
|
||||
KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
|
||||
current->comm, current->pid,
|
||||
start, end,
|
||||
cattr_name(actual_type),
|
||||
cattr_name(parse->type));
|
||||
err = -EBUSY;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (err) {
|
||||
break;
|
||||
}
|
||||
|
||||
/* No conflict. Go ahead and add this new entry */
|
||||
list_add(&new_entry->nd, saved_ptr->nd.prev);
|
||||
new_entry = NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (start < parse->end) {
|
||||
if (actual_type != parse->type && ret_type) {
|
||||
actual_type = parse->type;
|
||||
*ret_type = actual_type;
|
||||
new_entry->type = actual_type;
|
||||
}
|
||||
|
||||
if (actual_type != parse->type) {
|
||||
printk(
|
||||
KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
|
||||
current->comm, current->pid,
|
||||
start, end,
|
||||
cattr_name(actual_type),
|
||||
cattr_name(parse->type));
|
||||
err = -EBUSY;
|
||||
break;
|
||||
}
|
||||
|
||||
saved_ptr = parse;
|
||||
/*
|
||||
* Check to see whether the request overlaps more
|
||||
* than one entry in the list
|
||||
*/
|
||||
list_for_each_entry_continue(parse, &memtype_list, nd) {
|
||||
if (end <= parse->start) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (actual_type != parse->type) {
|
||||
printk(
|
||||
KERN_INFO "%s:%d conflicting memory types %Lx-%Lx %s<->%s\n",
|
||||
current->comm, current->pid,
|
||||
start, end,
|
||||
cattr_name(actual_type),
|
||||
cattr_name(parse->type));
|
||||
err = -EBUSY;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (err) {
|
||||
break;
|
||||
}
|
||||
|
||||
/* No conflict. Go ahead and add this new entry */
|
||||
list_add(&new_entry->nd, &saved_ptr->nd);
|
||||
new_entry = NULL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (err) {
|
||||
kfree(new_entry);
|
||||
spin_unlock(&memtype_lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
if (new_entry) {
|
||||
/* No conflict. Not yet added to the list. Add to the tail */
|
||||
list_add_tail(&new_entry->nd, &memtype_list);
|
||||
}
|
||||
|
||||
spin_unlock(&memtype_lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
int free_memtype(u64 start, u64 end)
|
||||
{
|
||||
struct memtype *ml;
|
||||
int err = -EINVAL;
|
||||
|
||||
/* Only track when pat_wc_enabled */
|
||||
if (!pat_wc_enabled) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Low ISA region is always mapped WB. No need to track */
|
||||
if (start >= ISA_START_ADDRESS && end <= ISA_END_ADDRESS) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
spin_lock(&memtype_lock);
|
||||
list_for_each_entry(ml, &memtype_list, nd) {
|
||||
if (ml->start == start && ml->end == end) {
|
||||
list_del(&ml->nd);
|
||||
kfree(ml);
|
||||
err = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
spin_unlock(&memtype_lock);
|
||||
|
||||
if (err) {
|
||||
printk(KERN_DEBUG "%s:%d freeing invalid memtype %Lx-%Lx\n",
|
||||
current->comm, current->pid, start, end);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
@ -186,6 +186,7 @@ extern const char * const x86_power_flags[32];
|
|||
#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
|
||||
#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
|
||||
#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
|
||||
#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
|
||||
|
||||
#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
|
||||
# define cpu_has_invlpg 1
|
||||
|
|
|
|||
|
|
@ -57,6 +57,8 @@
|
|||
#define MSR_MTRRfix4K_F8000 0x0000026f
|
||||
#define MSR_MTRRdefType 0x000002ff
|
||||
|
||||
#define MSR_IA32_CR_PAT 0x00000277
|
||||
|
||||
#define MSR_IA32_DEBUGCTLMSR 0x000001d9
|
||||
#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
|
||||
#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
|
||||
|
|
|
|||
|
|
@ -84,6 +84,8 @@ struct mtrr_gentry
|
|||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
extern u8 mtrr_type_lookup(u64 addr, u64 end);
|
||||
|
||||
/* The following functions are for use by other drivers */
|
||||
# ifdef CONFIG_MTRR
|
||||
extern void mtrr_save_fixed_ranges(void *);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
|
||||
#ifndef _ASM_PAT_H
|
||||
#define _ASM_PAT_H 1
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
extern int pat_wc_enabled;
|
||||
|
||||
extern void pat_init(void);
|
||||
|
||||
extern int reserve_memtype(u64 start, u64 end,
|
||||
unsigned long req_type, unsigned long *ret_type);
|
||||
extern int free_memtype(u64 start, u64 end);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -57,6 +57,12 @@
|
|||
|
||||
#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
|
||||
|
||||
#define _PAGE_CACHE_MASK (_PAGE_PCD | _PAGE_PWT)
|
||||
#define _PAGE_CACHE_WB (0)
|
||||
#define _PAGE_CACHE_WC (_PAGE_PWT)
|
||||
#define _PAGE_CACHE_UC_MINUS (_PAGE_PCD)
|
||||
#define _PAGE_CACHE_UC (_PAGE_PCD | _PAGE_PWT)
|
||||
|
||||
#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
|
||||
#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
|
||||
|
||||
|
|
|
|||
Reference in New Issue