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staging: comedi: mite: mite_io_addr and daq_io_addr are void __iomem * 

The mite_io_addr and daq_io_addr variables in struct mite_struct
are both ioremap'ed pci resources and should be void __iomem *
not void *.

This quiets a lot of sparse warings for the write[lwb],read[lwb]
calls in the comedi mite drives like:

warning: incorrect type in argument 1 (different address spaces)
   expected void const volatile [noderef] <asn:2>*addr
   got void *<noident>

warning: incorrect type in argument 2 (different address spaces)
   expected void volatile [noderef] <asn:2>*addr
   got void *

It also exposed some warnings in the mite ni_660x driver where
the daq_io_address was getting cast as a void *const.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Ian Abbott <abbotti@mev.co.uk>
Cc: Mori Hess <fmhess@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2012-05-08 16:19:34 -07:00 committed by Greg Kroah-Hartman
parent a19fb006c4
commit 2b7a521b12
2 changed files with 4 additions and 4 deletions
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4
drivers/staging/comedi/drivers/mite.h
View File

@ -66,9 +66,9 @@ struct mite_struct {
struct pci_dev *pcidev;
resource_size_t mite_phys_addr;
void *mite_io_addr;
void __iomem *mite_io_addr;
resource_size_t daq_phys_addr;
void *daq_io_addr;
void __iomem *daq_io_addr;
struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
short channel_allocated[MAX_MITE_DMA_CHANNELS];

4
drivers/staging/comedi/drivers/ni_660x.c
View File

@ -761,7 +761,7 @@ static inline void ni_660x_write_register(struct comedi_device *dev,
unsigned chip_index, unsigned bits,
enum NI_660x_Register reg)
{
void *const write_address =
void __iomem *write_address =
private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
registerData[reg].offset;
@ -784,7 +784,7 @@ static inline unsigned ni_660x_read_register(struct comedi_device *dev,
unsigned chip_index,
enum NI_660x_Register reg)
{
void *const read_address =
void __iomem *read_address =
private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
registerData[reg].offset;