msm: timer: Remove msm_clocks[] and simplify code
We can simplify the timer code now that we only use the DGT for the clocksource and the GPT for the clockevent. Get rid of the msm_clocks[] array and propagate the changes throughout the code. This reduces the lines of code in this file and improves readability. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: David Brown <davidb@codeaurora.org>
This commit is contained in:
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a850c3f644
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2a00c1068b
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@ -40,8 +40,6 @@
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#define GPT_HZ 32768
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#define GPT_HZ 32768
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#define MSM_GLOBAL_TIMER MSM_CLOCK_GPT
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/* TODO: Remove these ifdefs */
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/* TODO: Remove these ifdefs */
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#if defined(CONFIG_ARCH_QSD8X50)
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#if defined(CONFIG_ARCH_QSD8X50)
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#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
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#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
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@ -57,31 +55,7 @@
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#define MSM_DGT_SHIFT (5)
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#define MSM_DGT_SHIFT (5)
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#endif
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#endif
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struct msm_clock {
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static void __iomem *event_base;
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struct clock_event_device clockevent;
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struct clocksource clocksource;
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unsigned int irq;
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void __iomem *regbase;
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uint32_t freq;
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uint32_t shift;
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void __iomem *global_counter;
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void __iomem *local_counter;
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union {
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struct clock_event_device *evt;
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struct clock_event_device __percpu **percpu_evt;
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};
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};
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enum {
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MSM_CLOCK_GPT,
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MSM_CLOCK_DGT,
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NR_TIMERS,
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};
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static struct msm_clock msm_clocks[];
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static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt);
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static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
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static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
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{
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{
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@ -90,59 +64,31 @@ static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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/* Stop the timer tick */
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/* Stop the timer tick */
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if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
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if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
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struct msm_clock *clock = clockevent_to_clock(evt);
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u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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u32 ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);
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ctrl &= ~TIMER_ENABLE_EN;
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ctrl &= ~TIMER_ENABLE_EN;
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writel_relaxed(ctrl, clock->regbase + TIMER_ENABLE);
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writel_relaxed(ctrl, event_base + TIMER_ENABLE);
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}
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}
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evt->event_handler(evt);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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static cycle_t msm_read_timer_count(struct clocksource *cs)
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{
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struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
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/*
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* Shift timer count down by a constant due to unreliable lower bits
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* on some targets.
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*/
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return readl(clk->global_counter) >> clk->shift;
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}
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static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
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{
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#ifdef CONFIG_SMP
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int i;
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for (i = 0; i < NR_TIMERS; i++)
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if (evt == &(msm_clocks[i].clockevent))
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return &msm_clocks[i];
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return &msm_clocks[MSM_GLOBAL_TIMER];
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#else
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return container_of(evt, struct msm_clock, clockevent);
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#endif
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}
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static int msm_timer_set_next_event(unsigned long cycles,
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static int msm_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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struct clock_event_device *evt)
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{
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{
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struct msm_clock *clock = clockevent_to_clock(evt);
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u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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u32 match = cycles << clock->shift;
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u32 ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);
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writel_relaxed(0, clock->regbase + TIMER_CLEAR);
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writel_relaxed(0, event_base + TIMER_CLEAR);
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writel_relaxed(match, clock->regbase + TIMER_MATCH_VAL);
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writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
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writel_relaxed(ctrl | TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
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writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
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return 0;
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return 0;
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}
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}
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static void msm_timer_set_mode(enum clock_event_mode mode,
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static void msm_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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struct clock_event_device *evt)
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{
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{
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struct msm_clock *clock = clockevent_to_clock(evt);
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u32 ctrl;
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u32 ctrl;
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ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);
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ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
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ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
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switch (mode) {
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switch (mode) {
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@ -156,59 +102,61 @@ static void msm_timer_set_mode(enum clock_event_mode mode,
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_SHUTDOWN:
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break;
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break;
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}
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}
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writel_relaxed(ctrl, clock->regbase + TIMER_ENABLE);
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writel_relaxed(ctrl, event_base + TIMER_ENABLE);
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}
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}
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static struct msm_clock msm_clocks[] = {
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static struct clock_event_device msm_clockevent = {
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[MSM_CLOCK_GPT] = {
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.name = "gp_timer",
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.clockevent = {
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.name = "gp_timer",
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.shift = 32,
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.shift = 32,
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.set_next_event = msm_timer_set_next_event,
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.rating = 200,
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.set_mode = msm_timer_set_mode,
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.set_next_event = msm_timer_set_next_event,
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};
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.set_mode = msm_timer_set_mode,
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},
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static union {
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.irq = INT_GP_TIMER_EXP,
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struct clock_event_device *evt;
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.freq = GPT_HZ,
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struct clock_event_device __percpu **percpu_evt;
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},
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} msm_evt;
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[MSM_CLOCK_DGT] = {
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.clocksource = {
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static void __iomem *source_base;
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.name = "dg_timer",
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.rating = 300,
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static cycle_t msm_read_timer_count(struct clocksource *cs)
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.read = msm_read_timer_count,
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{
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.mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
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/*
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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* Shift timer count down by a constant due to unreliable lower bits
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},
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* on some targets.
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.freq = DGT_HZ >> MSM_DGT_SHIFT,
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*/
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.shift = MSM_DGT_SHIFT,
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return readl_relaxed(source_base + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT;
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}
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}
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static struct clocksource msm_clocksource = {
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.name = "dg_timer",
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.rating = 300,
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.read = msm_read_timer_count,
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.mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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};
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static void __init msm_timer_init(void)
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static void __init msm_timer_init(void)
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{
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{
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struct msm_clock *clock;
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struct clock_event_device *ce = &msm_clockevent;
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struct clock_event_device *ce = &msm_clocks[MSM_CLOCK_GPT].clockevent;
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struct clocksource *cs = &msm_clocksource;
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struct clocksource *cs = &msm_clocks[MSM_CLOCK_DGT].clocksource;
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int res;
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int res;
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int global_offset = 0;
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if (cpu_is_msm7x01()) {
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if (cpu_is_msm7x01()) {
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msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
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event_base = MSM_CSR_BASE;
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msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
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source_base = MSM_CSR_BASE + 0x10;
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} else if (cpu_is_msm7x30()) {
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} else if (cpu_is_msm7x30()) {
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msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
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event_base = MSM_CSR_BASE + 0x04;
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msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
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source_base = MSM_CSR_BASE + 0x24;
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} else if (cpu_is_qsd8x50()) {
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} else if (cpu_is_qsd8x50()) {
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msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
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event_base = MSM_CSR_BASE;
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msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
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source_base = MSM_CSR_BASE + 0x10;
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} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
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event_base = MSM_TMR_BASE + 0x04;
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msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
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/* Use CPU0's timer as the global clock source. */
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source_base = MSM_TMR0_BASE + 0x24;
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/* Use CPU0's timer as the global timer. */
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global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
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} else
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} else
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BUG();
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BUG();
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@ -216,88 +164,71 @@ static void __init msm_timer_init(void)
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writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
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writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
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#endif
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#endif
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clock = &msm_clocks[MSM_CLOCK_GPT];
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writel_relaxed(0, event_base + TIMER_ENABLE);
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clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
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writel_relaxed(0, event_base + TIMER_CLEAR);
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writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
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writel_relaxed(0, clock->regbase + TIMER_ENABLE);
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ce->mult = div_sc(GPT_HZ, NSEC_PER_SEC, ce->shift);
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writel_relaxed(0, clock->regbase + TIMER_CLEAR);
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writel_relaxed(~0, clock->regbase + TIMER_MATCH_VAL);
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ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
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/*
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/*
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* allow at least 10 seconds to notice that the timer
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* allow at least 10 seconds to notice that the timer
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* wrapped
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* wrapped
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*/
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*/
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ce->max_delta_ns =
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ce->max_delta_ns = clockevent_delta2ns(0xf0000000, ce);
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clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
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/* 4 gets rounded down to 3 */
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/* 4 gets rounded down to 3 */
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ce->min_delta_ns = clockevent_delta2ns(4, ce);
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ce->min_delta_ns = clockevent_delta2ns(4, ce);
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ce->cpumask = cpumask_of(0);
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ce->cpumask = cpumask_of(0);
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ce->irq = clock->irq;
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ce->irq = INT_GP_TIMER_EXP;
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if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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clock->percpu_evt = alloc_percpu(struct clock_event_device *);
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msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
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if (!clock->percpu_evt) {
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if (!msm_evt.percpu_evt) {
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pr_err("memory allocation failed for %s\n", ce->name);
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pr_err("memory allocation failed for %s\n", ce->name);
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goto err;
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goto err;
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}
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}
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*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
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*__this_cpu_ptr(clock->percpu_evt) = ce;
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res = request_percpu_irq(ce->irq, msm_timer_interrupt,
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res = request_percpu_irq(ce->irq, msm_timer_interrupt,
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ce->name, clock->percpu_evt);
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ce->name, msm_evt.percpu_evt);
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if (!res)
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if (!res)
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enable_percpu_irq(ce->irq, 0);
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enable_percpu_irq(ce->irq, 0);
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} else {
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} else {
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clock->evt = ce;
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msm_evt.evt = ce;
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res = request_irq(ce->irq, msm_timer_interrupt,
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res = request_irq(ce->irq, msm_timer_interrupt,
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IRQF_TIMER | IRQF_NOBALANCING |
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IRQF_TIMER | IRQF_NOBALANCING |
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IRQF_TRIGGER_RISING, ce->name, &clock->evt);
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IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
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}
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}
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if (res)
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if (res)
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pr_err("request_irq failed for %s\n", ce->name);
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pr_err("request_irq failed for %s\n", ce->name);
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clockevents_register_device(ce);
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clockevents_register_device(ce);
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err:
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err:
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clock = &msm_clocks[MSM_CLOCK_DGT];
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writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
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clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
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res = clocksource_register_hz(cs, DGT_HZ >> MSM_DGT_SHIFT);
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clock->global_counter = clock->local_counter + global_offset;
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writel_relaxed(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
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res = clocksource_register_hz(cs, clock->freq);
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if (res)
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if (res)
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pr_err("clocksource_register failed for %s\n", cs->name);
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pr_err("clocksource_register failed\n");
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}
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}
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#ifdef CONFIG_LOCAL_TIMERS
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#ifdef CONFIG_LOCAL_TIMERS
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int __cpuinit local_timer_setup(struct clock_event_device *evt)
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int __cpuinit local_timer_setup(struct clock_event_device *evt)
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{
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{
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static bool local_timer_inited;
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struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
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/* Use existing clock_event for cpu 0 */
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/* Use existing clock_event for cpu 0 */
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if (!smp_processor_id())
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if (!smp_processor_id())
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return 0;
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return 0;
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if (!local_timer_inited) {
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writel_relaxed(0, event_base + TIMER_ENABLE);
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writel(0, clock->regbase + TIMER_ENABLE);
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writel_relaxed(0, event_base + TIMER_CLEAR);
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writel(0, clock->regbase + TIMER_CLEAR);
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writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
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writel(~0, clock->regbase + TIMER_MATCH_VAL);
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evt->irq = msm_clockevent.irq;
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local_timer_inited = true;
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}
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evt->irq = clock->irq;
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evt->name = "local_timer";
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evt->name = "local_timer";
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evt->features = CLOCK_EVT_FEAT_ONESHOT;
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evt->features = msm_clockevent.features;
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evt->rating = clock->clockevent.rating;
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evt->rating = msm_clockevent.rating;
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evt->set_mode = msm_timer_set_mode;
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evt->set_mode = msm_timer_set_mode;
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evt->set_next_event = msm_timer_set_next_event;
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evt->set_next_event = msm_timer_set_next_event;
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evt->shift = clock->clockevent.shift;
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evt->shift = msm_clockevent.shift;
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evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
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evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
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evt->max_delta_ns =
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evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
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clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
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evt->min_delta_ns = clockevent_delta2ns(4, evt);
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evt->min_delta_ns = clockevent_delta2ns(4, evt);
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*__this_cpu_ptr(clock->percpu_evt) = evt;
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*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
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enable_percpu_irq(evt->irq, 0);
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enable_percpu_irq(evt->irq, 0);
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clockevents_register_device(evt);
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clockevents_register_device(evt);
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return 0;
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return 0;
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}
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}
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