dect
/
linux-2.6
Archived
13
0
Fork 0
Code Releases Activity

ARM: arm-soc: Non-critical bug fixes 

Simple bug fixes that were not considered important enough for inclusion
 into 3.7, especially those that arrived late during the merge window.
 
 There's also a MAINTAINERS update for the Renesas platforms in here,
 marking Simon Horman as a maintainer and changing the git url to his tree.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJQx2n/AAoJEIwa5zzehBx3ciUQAKIlI8FQ/ggsfP3xYzT7y9dm
 WCmfWb5OMq/kO+7vNImiKpqYUW63C+/LZlsLvXreo0YaOcodnIGr6zR822POCZ7d
 76sG8isrnHL9nNfBF3qRLsNfrFV+CrBKvm1go0v6cVVp6VfpHwAk5wbNL+ET/3Kb
 l3rjpFhxd5m2CMLY3ejPpwxsYXB8RJTTwz2ANYH37+aO4JwJFOmnEZoDFSSnbF5F
 veNF1PQvvmiFfi18yOIDJLzF1M1tw4g8Qr5Ypno2sBQaz3lm73cBtf5hqT7XjYzk
 oYgbNbR+XuJD35jtyYtV2DzUEPqZvFFTi1AL31senG+vT0HlLj+7ykQoaWs5maAb
 p9Vp3pe5kpCmQgRmeVF6Pqe5aTPhbfBnfIp+mBh5Bs9CUsXsSt+X8JYpicA3lZAM
 3OWq2PTkK/Cvv7RW91H2njgfoIeM5YzR3bb3EZ7JyYdDO9U+o6CMxhhNimFKq9Zk
 QqbFbLPhhBrhtcpCQTp0i17dvFJkHUY3CuktcgekEx1cTCdcaisjz/5Ax+3ZOG0C
 WxDMyAwQ4DP+USc9LAQkBqw3uVcoM0RqlmrXvxRtkrLEsD4msnmKoOe8zm3Q/CoD
 ZWASjBMbKaLzQ7rbrmV8CdjwdAwrxexyDITRd0yKgW4IeXALLBqyLb3cqt23C6Bf
 qIZtOgu1DKm1QoBM8Tgm
 =Lcpo
 -----END PGP SIGNATURE-----

Merge tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC Non-critical bug fixes from Olof Johansson:
 "Simple bug fixes that were not considered important enough for
  inclusion into 3.7, especially those that arrived late during the
  merge window.

  There's also a MAINTAINERS update for the Renesas platforms in here,
  marking Simon Horman as a maintainer and changing the git url to his
  tree."

* tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  Update ARM/SHMOBILE section of MAINTAINERS
  ARM: Fix Kconfig symbols typo for LEDS
  ARM: pxa: add dummy SA1100 rtc clock in pxa25x
  ARM: pxa: fix pxa25x gpio wakeup setting
  ARM: OMAP4: PM: fix errata handling when CONFIG_PM=n
  ARM: cns3xxx: drop unnecessary symbol selection
  ARM: vexpress: fix ll debug code when building multiplatform
  ARM: OMAP4: retrigger localtimers after re-enabling gic
  ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
  ARM: OMAP4: PM: add errata support
  ARM: davinci: fix return value check by using IS_ERR in tnetv107x_devices_init()
  ARM: davinci: uncompress.h: bail out if uart not initialized
  ARM: davinci: serial.h: fix uart number in the comment
  ARM: davinci: dm644x evm: move pointer dereference below NULL check
  ARM: vexpress: Make the debug UART detection more specific
This commit is contained in:
Linus Torvalds 2012-12-12 11:32:16 -08:00
parent b1286f4e9a 0a9995e46f
commit 2989950cea
16 changed files with 168 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
View File

@ -1130,12 +1130,12 @@ S: Maintained
F: drivers/media/platform/s5p-tv/
ARM/SHMOBILE ARM ARCHITECTURE
M: Paul Mundt <lethal@linux-sh.org>
M: Simon Horman <horms@verge.net.au>
M: Magnus Damm <magnus.damm@gmail.com>
L: linux-sh@vger.kernel.org
W: http://oss.renesas.com
Q: http://patchwork.kernel.org/project/linux-sh/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git rmobile-latest
T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
S: Supported
F: arch/arm/mach-shmobile/
F: drivers/sh/

11
arch/arm/include/debug/vexpress.S
View File

@ -21,14 +21,17 @@
#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
.macro addruart,rp,rv,tmp
.arch armv7-a
@ Make an educated guess regarding the memory map:
@ - the original A9 core tile, which has MPCore peripherals
@ located at 0x1e000000, should use UART at 0x10009000
@ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
@ should use UART at 0x10009000
@ - all other (RS1 complaint) tiles use UART mapped
@ at 0x1c090000
mrc p15, 4, \tmp, c15, c0, 0
cmp \tmp, #0x1e000000
mrc p15, 0, \rp, c0, c0, 0
movw \rv, #0xc091
movt \rv, #0x410f
cmp \rp, \rv
@ Original memory map
moveq \rp, #DEBUG_LL_UART_OFFSET

1
arch/arm/mach-cns3xxx/Kconfig
View File

@ -3,7 +3,6 @@ menu "CNS3XXX platform type"
config MACH_CNS3420VB
bool "Support for CNS3420 Validation Board"
select MIGHT_HAVE_PCI
help
Include support for the Cavium Networks CNS3420 MPCore Platform
Baseboard.

5
arch/arm/mach-davinci/board-dm644x-evm.c
View File

@ -519,13 +519,11 @@ static int dm6444evm_msp430_get_pins(void)
char buf[4];
struct i2c_msg msg[2] = {
{
.addr = dm6446evm_msp->addr,
.flags = 0,
.len = 2,
.buf = (void __force *)txbuf,
},
{
.addr = dm6446evm_msp->addr,
.flags = I2C_M_RD,
.len = 4,
.buf = buf,
@ -536,6 +534,9 @@ static int dm6444evm_msp430_get_pins(void)
if (!dm6446evm_msp)
return -ENXIO;
msg[0].addr = dm6446evm_msp->addr;
msg[1].addr = dm6446evm_msp->addr;
/* Command 4 == get input state, returns port 2 and port3 data
* S Addr W [A] len=2 [A] cmd=4 [A]
* RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P

2
arch/arm/mach-davinci/devices-tnetv107x.c
View File

@ -374,7 +374,7 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
* complete sample conversion in time.
*/
tsc_clk = clk_get(NULL, "sys_tsc_clk");
if (tsc_clk) {
if (!IS_ERR(tsc_clk)) {
error = clk_set_rate(tsc_clk, 5000000);
WARN_ON(error < 0);
clk_put(tsc_clk);

2
arch/arm/mach-davinci/include/mach/serial.h
View File

@ -38,7 +38,7 @@
#ifndef __ASSEMBLY__
struct davinci_uart_config {
/* Bit field of UARTs present; bit 0 --> UART1 */
/* Bit field of UARTs present; bit 0 --> UART0 */
unsigned int enabled_uarts;
};

6
arch/arm/mach-davinci/include/mach/uncompress.h
View File

@ -32,6 +32,9 @@ u32 *uart;
/* PORT_16C550A, in polled non-fifo mode */
static void putc(char c)
{
if (!uart)
return;
while (!(uart[UART_LSR] & UART_LSR_THRE))
barrier();
uart[UART_TX] = c;
@ -39,6 +42,9 @@ static void putc(char c)
static inline void flush(void)
{
if (!uart)
return;
while (!(uart[UART_LSR] & UART_LSR_THRE))
barrier();
}

4
arch/arm/mach-omap2/common.h
View File

@ -275,6 +275,9 @@ static inline void __iomem *omap4_get_scu_base(void)
#endif
extern void __init gic_init_irq(void);
extern void gic_dist_disable(void);
extern bool gic_dist_disabled(void);
extern void gic_timer_retrigger(void);
extern void omap_smc1(u32 fn, u32 arg);
extern void __iomem *omap4_get_sar_ram_base(void);
extern void omap_do_wfi(void);
@ -282,6 +285,7 @@ extern void omap_do_wfi(void);
#ifdef CONFIG_SMP
/* Needed for secondary core boot */
extern void omap_secondary_startup(void);
extern void omap_secondary_startup_4460(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
extern void omap_auxcoreboot_addr(u32 cpu_addr);
extern u32 omap_read_auxcoreboot0(void);

38
arch/arm/mach-omap2/omap-headsmp.S
View File

@ -18,6 +18,8 @@
#include <linux/linkage.h>
#include <linux/init.h>
#include "omap44xx.h"
__CPUINIT
/* Physical address needed since MMU not enabled yet on secondary core */
@ -64,3 +66,39 @@ hold: ldr r12,=0x103
b secondary_startup
ENDPROC(omap_secondary_startup)
ENTRY(omap_secondary_startup_4460)
hold_2: ldr r12,=0x103
dsb
smc #0 @ read from AuxCoreBoot0
mov r0, r0, lsr #9
mrc p15, 0, r4, c0, c0, 5
and r4, r4, #0x0f
cmp r0, r4
bne hold_2
/*
* GIC distributor control register has changed between
* CortexA9 r1pX and r2pX. The Control Register secure
* banked version is now composed of 2 bits:
* bit 0 == Secure Enable
* bit 1 == Non-Secure Enable
* The Non-Secure banked register has not changed
* Because the ROM Code is based on the r1pX GIC, the CPU1
* GIC restoration will cause a problem to CPU0 Non-Secure SW.
* The workaround must be:
* 1) Before doing the CPU1 wakeup, CPU0 must disable
* the GIC distributor
* 2) CPU1 must re-enable the GIC distributor on
* it's wakeup path.
*/
ldr r1, =OMAP44XX_GIC_DIST_BASE
ldr r0, [r1]
orr r0, #1
str r0, [r1]
/*
* we've been released from the wait loop,secondary_stack
* should now contain the SVC stack for this core
*/
b secondary_startup
ENDPROC(omap_secondary_startup_4460)

9
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View File

@ -67,6 +67,7 @@ struct omap4_cpu_pm_info {
void __iomem *scu_sar_addr;
void __iomem *wkup_sar_addr;
void __iomem *l2x0_sar_addr;
void (*secondary_startup)(void);
};
static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
@ -299,6 +300,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
unsigned int cpu_state = 0;
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
if (omap_rev() == OMAP4430_REV_ES1_0)
return -ENXIO;
@ -308,7 +310,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
clear_cpu_prev_pwrst(cpu);
set_cpu_next_pwrst(cpu, power_state);
set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
scu_pwrst_prepare(cpu, power_state);
/*
@ -359,6 +361,11 @@ int __init omap4_mpuss_init(void)
pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
if (cpu_is_omap446x())
pm_info->secondary_startup = omap_secondary_startup_4460;
else
pm_info->secondary_startup = omap_secondary_startup;
pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
if (!pm_info->pwrdm) {
pr_err("Lookup failed for CPU1 pwrdm\n");

41
arch/arm/mach-omap2/omap-smp.c
View File

@ -32,6 +32,7 @@
#include "iomap.h"
#include "common.h"
#include "clockdomain.h"
#include "pm.h"
#define CPU_MASK 0xff0ffff0
#define CPU_CORTEX_A9 0x410FC090
@ -39,6 +40,8 @@
#define OMAP5_CORE_COUNT 0x2
u16 pm44xx_errata;
/* SCU base address */
static void __iomem *scu_base;
@ -118,8 +121,37 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
* 4.3.4.2 Power States of CPU0 and CPU1
*/
if (booted) {
/*
* GIC distributor control register has changed between
* CortexA9 r1pX and r2pX. The Control Register secure
* banked version is now composed of 2 bits:
* bit 0 == Secure Enable
* bit 1 == Non-Secure Enable
* The Non-Secure banked register has not changed
* Because the ROM Code is based on the r1pX GIC, the CPU1
* GIC restoration will cause a problem to CPU0 Non-Secure SW.
* The workaround must be:
* 1) Before doing the CPU1 wakeup, CPU0 must disable
* the GIC distributor
* 2) CPU1 must re-enable the GIC distributor on
* it's wakeup path.
*/
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
local_irq_disable();
gic_dist_disable();
}
clkdm_wakeup(cpu1_clkdm);
clkdm_allow_idle(cpu1_clkdm);
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
while (gic_dist_disabled()) {
udelay(1);
cpu_relax();
}
gic_timer_retrigger();
local_irq_enable();
}
} else {
dsb_sev();
booted = true;
@ -138,7 +170,14 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
static void __init wakeup_secondary(void)
{
void *startup_addr = omap_secondary_startup;
void __iomem *base = omap_get_wakeupgen_base();
if (cpu_is_omap446x()) {
startup_addr = omap_secondary_startup_4460;
pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
}
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot1 where ROM code will jump and start executing
@ -146,7 +185,7 @@ static void __init wakeup_secondary(void)
* A barrier is added to ensure that write buffer is drained
*/
if (omap_secure_apis_support())
omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
else
__raw_writel(virt_to_phys(omap5_secondary_startup),
base + OMAP_AUX_CORE_BOOT_1);

42
arch/arm/mach-omap2/omap4-common.c
View File

@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
#include <linux/of_irq.h>
@ -24,6 +25,7 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
#include <asm/smp_twd.h>
#include <plat/sram.h>
#include <plat/omap-secure.h>
@ -41,6 +43,10 @@ static void __iomem *l2cache_base;
#endif
static void __iomem *sar_ram_base;
static void __iomem *gic_dist_base_addr;
static void __iomem *twd_base;
#define IRQ_LOCALTIMER 29
#ifdef CONFIG_OMAP4_ERRATA_I688
/* Used to implement memory barrier on DRAM path */
@ -95,12 +101,14 @@ void __init omap_barriers_init(void)
void __init gic_init_irq(void)
{
void __iomem *omap_irq_base;
void __iomem *gic_dist_base_addr;
/* Static mapping, never released */
gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
BUG_ON(!gic_dist_base_addr);
twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
BUG_ON(!twd_base);
/* Static mapping, never released */
omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
BUG_ON(!omap_irq_base);
@ -110,6 +118,38 @@ void __init gic_init_irq(void)
gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
}
void gic_dist_disable(void)
{
if (gic_dist_base_addr)
__raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
}
bool gic_dist_disabled(void)
{
return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
}
void gic_timer_retrigger(void)
{
u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
/*
* The local timer interrupt got lost while the distributor was
* disabled. Ack the pending interrupt, and retrigger it.
*/
pr_warn("%s: lost localtimer interrupt\n", __func__);
__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
__raw_writel(1, twd_base + TWD_TIMER_COUNTER);
twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
__raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
}
}
}
#ifdef CONFIG_CACHE_L2X0
void __iomem *omap4_get_l2cache_base(void)

9
arch/arm/mach-omap2/pm.h
View File

@ -102,6 +102,15 @@ extern void enable_omap3630_toggle_l2_on_restore(void);
static inline void enable_omap3630_toggle_l2_on_restore(void) { }
#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0)
#if defined(CONFIG_ARCH_OMAP4)
extern u16 pm44xx_errata;
#define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id))
#else
#define IS_PM44XX_ERRATUM(id) 0
#endif
#ifdef CONFIG_POWER_AVS_OMAP
extern int omap_devinit_smartreflex(void);
extern void omap_enable_smartreflex_on_init(void);

6
arch/arm/mach-pxa/pxa25x.c
View File

@ -209,6 +209,7 @@ static struct clk_lookup pxa25x_clkregs[] = {
INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};
static struct clk_lookup pxa25x_hwuart_clkreg =
@ -338,6 +339,10 @@ void __init pxa25x_map_io(void)
pxa25x_get_clk_frequency_khz(1);
}
static struct pxa_gpio_platform_data pxa25x_gpio_info __initdata = {
.gpio_set_wake = gpio_set_wake,
};
static struct platform_device *pxa25x_devices[] __initdata = {
&pxa25x_device_udc,
&pxa_device_pmu,
@ -370,6 +375,7 @@ static int __init pxa25x_init(void)
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
register_syscore_ops(&pxa2xx_clock_syscore_ops);
pxa_register_device(&pxa_device_gpio, &pxa25x_gpio_info);
ret = platform_add_devices(pxa25x_devices,
ARRAY_SIZE(pxa25x_devices));
if (ret)

2
arch/arm/mach-s3c24xx/Kconfig
View File

@ -400,7 +400,7 @@ config MACH_MINI2440
bool "MINI2440 development board"
select EEPROM_AT24
select LEDS_CLASS
select LEDS_TRIGGER
select LEDS_TRIGGERS
select LEDS_TRIGGER_BACKLIGHT
select NEW_LEDS
select S3C_DEV_NAND

2
arch/arm/plat-versatile/Kconfig
View File

@ -19,7 +19,7 @@ config PLAT_VERSATILE_LEDS
def_bool y if NEW_LEDS
depends on ARCH_REALVIEW || ARCH_VERSATILE
select LEDS_CLASS
select LEDS_TRIGGER
select LEDS_TRIGGERS
config PLAT_VERSATILE_SCHED_CLOCK
def_bool y