drm/nouveau: Make the MM aware of pre-G80 tiling.
This commit has also the following 3 bugfix commits squashed into it from the nouveau git tree: drm/nouveau: Fix up the tiling alignment restrictions for nv1x. drm/nouveau: Fix up the nv2x tiling alignment restrictions. drm/nv50: fix align typo for g9x Signed-off-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Francisco Jerez
Dave Airlie
parent
0d87c10031
commit
287c153214
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@ -37,6 +37,7 @@ static void
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nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
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struct drm_device *dev = dev_priv->dev;
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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ttm_bo_kunmap(&nvbo->kmap);
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@ -44,12 +45,83 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
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if (unlikely(nvbo->gem))
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DRM_ERROR("bo %p still attached to GEM object\n", bo);
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if (nvbo->tile)
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nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
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spin_lock(&dev_priv->ttm.bo_list_lock);
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list_del(&nvbo->head);
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spin_unlock(&dev_priv->ttm.bo_list_lock);
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kfree(nvbo);
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}
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static void
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nouveau_bo_fixup_align(struct drm_device *dev,
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uint32_t tile_mode, uint32_t tile_flags,
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int *align, int *size)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/*
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* Some of the tile_flags have a periodic structure of N*4096 bytes,
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* align to to that as well as the page size. Overallocate memory to
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* avoid corruption of other buffer objects.
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*/
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if (dev_priv->card_type == NV_50) {
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switch (tile_flags) {
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case 0x1800:
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case 0x2800:
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case 0x4800:
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case 0x7a00:
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if (dev_priv->chipset >= 0xA0) {
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/* This is based on high end cards with 448 bits
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* memory bus, could be different elsewhere.*/
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*size += 6 * 28672;
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/* 8 * 28672 is the actual alignment requirement
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* but we must also align to page size. */
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*align = 2 * 8 * 28672;
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} else if (dev_priv->chipset >= 0x90) {
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*size += 3 * 16384;
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*align = 12 * 16384;
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} else {
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*size += 3 * 8192;
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/* 12 * 8192 is the actual alignment requirement
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* but we must also align to page size. */
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*align = 2 * 12 * 8192;
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}
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break;
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default:
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break;
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}
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} else {
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if (tile_mode) {
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if (dev_priv->chipset >= 0x40) {
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*align = 65536;
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*size = roundup(*size, 64 * tile_mode);
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} else if (dev_priv->chipset >= 0x30) {
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*align = 32768;
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*size = roundup(*size, 64 * tile_mode);
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} else if (dev_priv->chipset >= 0x20) {
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*align = 16384;
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*size = roundup(*size, 64 * tile_mode);
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} else if (dev_priv->chipset >= 0x10) {
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*align = 16384;
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*size = roundup(*size, 32 * tile_mode);
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}
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}
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}
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*size = ALIGN(*size, PAGE_SIZE);
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if (dev_priv->card_type == NV_50) {
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*size = ALIGN(*size, 65536);
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*align = max(65536, *align);
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}
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}
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int
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nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
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int size, int align, uint32_t flags, uint32_t tile_mode,
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@ -70,46 +142,9 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
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nvbo->tile_mode = tile_mode;
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nvbo->tile_flags = tile_flags;
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/*
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* Some of the tile_flags have a periodic structure of N*4096 bytes,
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* align to to that as well as the page size. Overallocate memory to
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* avoid corruption of other buffer objects.
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*/
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switch (tile_flags) {
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case 0x1800:
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case 0x2800:
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case 0x4800:
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case 0x7a00:
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if (dev_priv->chipset >= 0xA0) {
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/* This is based on high end cards with 448 bits
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* memory bus, could be different elsewhere.*/
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size += 6 * 28672;
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/* 8 * 28672 is the actual alignment requirement,
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* but we must also align to page size. */
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align = 2 * 8 * 28672;
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} else if (dev_priv->chipset >= 0x90) {
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size += 3 * 16384;
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align = 12 * 16834;
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} else {
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size += 3 * 8192;
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/* 12 * 8192 is the actual alignment requirement,
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* but we must also align to page size. */
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align = 2 * 12 * 8192;
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}
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break;
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default:
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break;
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}
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nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
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align >>= PAGE_SHIFT;
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size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
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if (dev_priv->card_type == NV_50) {
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size = (size + 65535) & ~65535;
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if (align < (65536 / PAGE_SIZE))
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align = (65536 / PAGE_SIZE);
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}
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if (flags & TTM_PL_FLAG_VRAM)
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nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING;
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if (flags & TTM_PL_FLAG_TT)
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@ -421,6 +456,7 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
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/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
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* TTM_PL_{VRAM,TT} directly.
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*/
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static int
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nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
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struct nouveau_bo *nvbo, bool evict, bool no_wait,
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@ -455,11 +491,12 @@ nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
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}
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static int
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nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, int no_wait,
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struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
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nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
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int no_wait, struct ttm_mem_reg *new_mem)
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{
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
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struct ttm_mem_reg *old_mem = &bo->mem;
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struct nouveau_channel *chan;
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uint64_t src_offset, dst_offset;
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uint32_t page_count;
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@ -559,7 +596,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
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if (ret)
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goto out;
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ret = nouveau_bo_move_m2mf(bo, true, no_wait, &bo->mem, &tmp_mem);
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ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem);
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if (ret)
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goto out;
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@ -597,7 +634,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
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if (ret)
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goto out;
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ret = nouveau_bo_move_m2mf(bo, true, no_wait, &bo->mem, new_mem);
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ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, new_mem);
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if (ret)
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goto out;
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@ -612,52 +649,106 @@ out:
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}
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static int
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nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
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bool no_wait, struct ttm_mem_reg *new_mem)
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nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
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struct nouveau_tile_reg **new_tile)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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struct drm_device *dev = dev_priv->dev;
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struct ttm_mem_reg *old_mem = &bo->mem;
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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uint64_t offset;
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int ret;
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if (dev_priv->card_type == NV_50 && new_mem->mem_type == TTM_PL_VRAM &&
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!nvbo->no_vm) {
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uint64_t offset = new_mem->mm_node->start << PAGE_SHIFT;
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if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
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/* Nothing to do. */
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*new_tile = NULL;
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return 0;
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}
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offset = new_mem->mm_node->start << PAGE_SHIFT;
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if (dev_priv->card_type == NV_50) {
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ret = nv50_mem_vm_bind_linear(dev,
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offset + dev_priv->vm_vram_base,
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new_mem->size, nvbo->tile_flags,
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offset);
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if (ret)
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return ret;
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} else if (dev_priv->card_type >= NV_10) {
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*new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
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nvbo->tile_mode);
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}
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if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
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!dev_priv->channel)
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return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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return 0;
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}
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static void
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nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
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struct nouveau_tile_reg *new_tile,
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struct nouveau_tile_reg **old_tile)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
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struct drm_device *dev = dev_priv->dev;
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if (dev_priv->card_type >= NV_10 &&
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dev_priv->card_type < NV_50) {
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if (*old_tile)
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nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
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*old_tile = new_tile;
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}
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}
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static int
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nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
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bool no_wait, struct ttm_mem_reg *new_mem)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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struct ttm_mem_reg *old_mem = &bo->mem;
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struct nouveau_tile_reg *new_tile = NULL;
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int ret = 0;
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ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
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if (ret)
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return ret;
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/* Software copy if the card isn't up and running yet. */
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if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
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!dev_priv->channel) {
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ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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goto out;
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}
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/* Fake bo copy. */
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if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
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BUG_ON(bo->mem.mm_node != NULL);
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bo->mem = *new_mem;
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new_mem->mm_node = NULL;
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return 0;
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goto out;
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}
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if (new_mem->mem_type == TTM_PL_SYSTEM) {
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if (old_mem->mem_type == TTM_PL_SYSTEM)
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return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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if (nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem))
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return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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} else if (old_mem->mem_type == TTM_PL_SYSTEM) {
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if (nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem))
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return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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} else {
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if (nouveau_bo_move_m2mf(bo, evict, no_wait, old_mem, new_mem))
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return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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}
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/* Hardware assisted copy. */
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if (new_mem->mem_type == TTM_PL_SYSTEM)
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ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem);
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else if (old_mem->mem_type == TTM_PL_SYSTEM)
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ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem);
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else
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ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
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return 0;
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if (!ret)
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goto out;
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/* Fallback to software copy. */
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ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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out:
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if (ret)
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nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
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else
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nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
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return ret;
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}
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static int
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@ -59,11 +59,19 @@ struct nouveau_grctx;
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#define MAX_NUM_DCB_ENTRIES 16
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#define NOUVEAU_MAX_CHANNEL_NR 128
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#define NOUVEAU_MAX_TILE_NR 15
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#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
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#define NV50_VM_BLOCK (512*1024*1024ULL)
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#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
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struct nouveau_tile_reg {
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struct nouveau_fence *fence;
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uint32_t addr;
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uint32_t size;
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bool used;
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};
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struct nouveau_bo {
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struct ttm_buffer_object bo;
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struct ttm_placement placement;
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@ -83,6 +91,7 @@ struct nouveau_bo {
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uint32_t tile_mode;
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uint32_t tile_flags;
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struct nouveau_tile_reg *tile;
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struct drm_gem_object *gem;
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struct drm_file *cpu_filp;
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@ -558,6 +567,12 @@ struct drm_nouveau_private {
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unsigned long sg_handle;
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} gart_info;
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/* nv10-nv40 tiling regions */
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struct {
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struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
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spinlock_t lock;
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} tile;
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/* G8x/G9x virtual address space */
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uint64_t vm_gart_base;
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uint64_t vm_gart_size;
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@ -695,6 +710,13 @@ extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
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extern int nouveau_mem_init(struct drm_device *);
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extern int nouveau_mem_init_agp(struct drm_device *);
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extern void nouveau_mem_close(struct drm_device *);
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extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
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uint32_t addr,
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uint32_t size,
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uint32_t pitch);
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extern void nv10_mem_expire_tiling(struct drm_device *dev,
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struct nouveau_tile_reg *tile,
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struct nouveau_fence *fence);
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extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
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uint32_t size, uint32_t flags,
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uint64_t phys);
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|
|
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|
@ -191,6 +191,92 @@ void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
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}
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}
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/*
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* NV10-NV40 tiling helpers
|
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*/
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static void
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nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
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uint32_t size, uint32_t pitch)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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tile->addr = addr;
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tile->size = size;
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tile->used = !!pitch;
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nouveau_fence_unref((void **)&tile->fence);
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if (!pfifo->cache_flush(dev))
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return;
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pfifo->reassign(dev, false);
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pfifo->cache_flush(dev);
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pfifo->cache_pull(dev, false);
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nouveau_wait_for_idle(dev);
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pgraph->set_region_tiling(dev, i, addr, size, pitch);
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pfb->set_region_tiling(dev, i, addr, size, pitch);
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pfifo->cache_pull(dev, true);
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pfifo->reassign(dev, true);
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}
|
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|
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struct nouveau_tile_reg *
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nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
|
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uint32_t pitch)
|
||||
{
|
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struct drm_nouveau_private *dev_priv = dev->dev_private;
|
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
|
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struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
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int i;
|
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spin_lock(&dev_priv->tile.lock);
|
||||
|
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for (i = 0; i < pfb->num_tiles; i++) {
|
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if (tile[i].used)
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/* Tile region in use. */
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continue;
|
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if (tile[i].fence &&
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!nouveau_fence_signalled(tile[i].fence, NULL))
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/* Pending tile region. */
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continue;
|
||||
|
||||
if (max(tile[i].addr, addr) <
|
||||
min(tile[i].addr + tile[i].size, addr + size))
|
||||
/* Kill an intersecting tile region. */
|
||||
nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
|
||||
|
||||
if (pitch && !found) {
|
||||
/* Free tile region. */
|
||||
nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
|
||||
found = &tile[i];
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock(&dev_priv->tile.lock);
|
||||
|
||||
return found;
|
||||
}
|
||||
|
||||
void
|
||||
nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
|
||||
struct nouveau_fence *fence)
|
||||
{
|
||||
if (fence) {
|
||||
/* Mark it as pending. */
|
||||
tile->fence = fence;
|
||||
nouveau_fence_ref(fence);
|
||||
}
|
||||
|
||||
tile->used = false;
|
||||
}
|
||||
|
||||
/*
|
||||
* NV50 VM helpers
|
||||
*/
|
||||
|
|
@ -513,6 +599,7 @@ nouveau_mem_init(struct drm_device *dev)
|
|||
|
||||
INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
|
||||
spin_lock_init(&dev_priv->ttm.bo_list_lock);
|
||||
spin_lock_init(&dev_priv->tile.lock);
|
||||
|
||||
dev_priv->fb_available_size = nouveau_mem_fb_amount(dev);
|
||||
|
||||
|
|
|
|||
Reference in New Issue