w1: complete the 1-wire (w1) ds1wm driver search algorithm
This adds multi-slave support of the w1 bus for the ds1wm Synthesizable 1-Wire Bus Master. Also many fixes and tweaks based on the rev3 of the datasheet http://datasheets.maxim-ic.com/en/ds/DS1WM.pdf Signed-off-by: Jean-François Dagenais <dagenaisj@sonatest.com> Cc: Evgeniy Polyakov <johnpol@2ka.mipt.ru> Cc: Szabolcs Gyurko <szabolcs.gyurko@tlt.hu> Cc: Matt Reimer <mreimer@vpop.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Jean-François Dagenais
Linus Torvalds
parent
89610274bd
commit
26a6afb917
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@ -42,7 +42,7 @@ config W1_MASTER_MXC
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config W1_MASTER_DS1WM
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tristate "Maxim DS1WM 1-wire busmaster"
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depends on W1 && ARM && HAVE_CLK
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depends on W1
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help
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Say Y here to enable the DS1WM 1-wire driver, such as that
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in HP iPAQ devices like h5xxx, h2200, and ASIC3-based like
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@ -33,6 +33,7 @@
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#define DS1WM_INT 0x02 /* R/W interrupt status */
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#define DS1WM_INT_EN 0x03 /* R/W interrupt enable */
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#define DS1WM_CLKDIV 0x04 /* R/W 5 bits of divisor and pre-scale */
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#define DS1WM_CNTRL 0x05 /* R/W master control register (not used yet) */
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#define DS1WM_CMD_1W_RESET (1 << 0) /* force reset on 1-wire bus */
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#define DS1WM_CMD_SRA (1 << 1) /* enable Search ROM accelerator mode */
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@ -56,6 +57,7 @@
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#define DS1WM_INTEN_ERSRF (1 << 5) /* enable rx shift register full int */
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#define DS1WM_INTEN_DQO (1 << 6) /* enable direct bus driving ops */
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#define DS1WM_INTEN_NOT_IAS (~DS1WM_INTEN_IAS) /* all but INTR active state */
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#define DS1WM_TIMEOUT (HZ * 5)
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@ -63,41 +65,50 @@ static struct {
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unsigned long freq;
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unsigned long divisor;
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} freq[] = {
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{ 4000000, 0x8 },
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{ 5000000, 0x2 },
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{ 6000000, 0x5 },
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{ 7000000, 0x3 },
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{ 8000000, 0xc },
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{ 10000000, 0x6 },
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{ 12000000, 0x9 },
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{ 14000000, 0x7 },
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{ 16000000, 0x10 },
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{ 20000000, 0xa },
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{ 24000000, 0xd },
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{ 28000000, 0xb },
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{ 32000000, 0x14 },
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{ 40000000, 0xe },
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{ 48000000, 0x11 },
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{ 56000000, 0xf },
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{ 64000000, 0x18 },
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{ 80000000, 0x12 },
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{ 96000000, 0x15 },
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{ 112000000, 0x13 },
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{ 128000000, 0x1c },
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{ 1000000, 0x80 },
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{ 2000000, 0x84 },
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{ 3000000, 0x81 },
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{ 4000000, 0x88 },
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{ 5000000, 0x82 },
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{ 6000000, 0x85 },
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{ 7000000, 0x83 },
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{ 8000000, 0x8c },
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{ 10000000, 0x86 },
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{ 12000000, 0x89 },
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{ 14000000, 0x87 },
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{ 16000000, 0x90 },
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{ 20000000, 0x8a },
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{ 24000000, 0x8d },
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{ 28000000, 0x8b },
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{ 32000000, 0x94 },
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{ 40000000, 0x8e },
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{ 48000000, 0x91 },
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{ 56000000, 0x8f },
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{ 64000000, 0x98 },
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{ 80000000, 0x92 },
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{ 96000000, 0x95 },
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{ 112000000, 0x93 },
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{ 128000000, 0x9c },
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/* you can continue this table, consult the OPERATION - CLOCK DIVISOR
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section of the ds1wm spec sheet. */
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};
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struct ds1wm_data {
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void __iomem *map;
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int bus_shift; /* # of shifts to calc register offsets */
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void __iomem *map;
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int bus_shift; /* # of shifts to calc register offsets */
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struct platform_device *pdev;
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const struct mfd_cell *cell;
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int irq;
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int active_high;
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int slave_present;
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void *reset_complete;
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void *read_complete;
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void *write_complete;
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u8 read_byte; /* last byte received */
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const struct mfd_cell *cell;
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int irq;
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int slave_present;
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void *reset_complete;
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void *read_complete;
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void *write_complete;
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int read_error;
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/* last byte received */
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u8 read_byte;
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/* byte to write that makes all intr disabled, */
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/* considering active_state (IAS) (optimization) */
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u8 int_en_reg_none;
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};
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static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
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@ -115,23 +126,39 @@ static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
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static irqreturn_t ds1wm_isr(int isr, void *data)
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{
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struct ds1wm_data *ds1wm_data = data;
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u8 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
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u8 intr;
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u8 inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
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/* if no bits are set in int enable register (except the IAS)
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than go no further, reading the regs below has side effects */
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if (!(inten & DS1WM_INTEN_NOT_IAS))
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return IRQ_NONE;
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ds1wm_write_register(ds1wm_data,
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DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
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/* this read action clears the INTR and certain flags in ds1wm */
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intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
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ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
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if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete)
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complete(ds1wm_data->reset_complete);
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if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete)
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if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete) {
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inten &= ~DS1WM_INTEN_ETMT;
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complete(ds1wm_data->write_complete);
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}
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if (intr & DS1WM_INT_RBF) {
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/* this read clears the RBF flag */
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ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
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DS1WM_DATA);
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DS1WM_DATA);
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inten &= ~DS1WM_INTEN_ERBF;
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if (ds1wm_data->read_complete)
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complete(ds1wm_data->read_complete);
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}
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if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete) {
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inten &= ~DS1WM_INTEN_EPD;
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complete(ds1wm_data->reset_complete);
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}
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ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, inten);
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return IRQ_HANDLED;
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}
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@ -142,33 +169,19 @@ static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
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ds1wm_data->reset_complete = &reset_done;
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/* enable Presence detect only */
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ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
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(ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
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ds1wm_data->int_en_reg_none);
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ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
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timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
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ds1wm_data->reset_complete = NULL;
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if (!timeleft) {
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dev_err(&ds1wm_data->pdev->dev, "reset failed\n");
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dev_err(&ds1wm_data->pdev->dev, "reset failed, timed out\n");
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return 1;
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}
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/* Wait for the end of the reset. According to the specs, the time
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* from when the interrupt is asserted to the end of the reset is:
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* tRSTH - tPDH - tPDL - tPDI
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* 625 us - 60 us - 240 us - 100 ns = 324.9 us
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*
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* We'll wait a bit longer just to be sure.
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* Was udelay(500), but if it is going to busywait the cpu that long,
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* might as well come back later.
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*/
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msleep(1);
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ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
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DS1WM_INTEN_ERBF | DS1WM_INTEN_ETMT | DS1WM_INTEN_EPD |
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(ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
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if (!ds1wm_data->slave_present) {
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dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
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return 1;
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@ -179,26 +192,47 @@ static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
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static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
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{
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unsigned long timeleft;
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DECLARE_COMPLETION_ONSTACK(write_done);
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ds1wm_data->write_complete = &write_done;
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ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
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ds1wm_data->int_en_reg_none | DS1WM_INTEN_ETMT);
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ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
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wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
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timeleft = wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
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ds1wm_data->write_complete = NULL;
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if (!timeleft) {
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dev_err(&ds1wm_data->pdev->dev, "write failed, timed out\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
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static u8 ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
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{
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unsigned long timeleft;
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u8 intEnable = DS1WM_INTEN_ERBF | ds1wm_data->int_en_reg_none;
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DECLARE_COMPLETION_ONSTACK(read_done);
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ds1wm_read_register(ds1wm_data, DS1WM_DATA);
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ds1wm_data->read_complete = &read_done;
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ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, intEnable);
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ds1wm_write_register(ds1wm_data, DS1WM_DATA, write_data);
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timeleft = wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
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ds1wm_write(ds1wm_data, write_data);
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wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
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ds1wm_data->read_complete = NULL;
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if (!timeleft) {
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dev_err(&ds1wm_data->pdev->dev, "read failed, timed out\n");
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ds1wm_data->read_error = -ETIMEDOUT;
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return 0xFF;
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}
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ds1wm_data->read_error = 0;
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return ds1wm_data->read_byte;
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}
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@ -206,8 +240,8 @@ static int ds1wm_find_divisor(int gclk)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(freq); i++)
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if (gclk <= freq[i].freq)
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for (i = ARRAY_SIZE(freq)-1; i >= 0; --i)
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if (gclk >= freq[i].freq)
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return freq[i].divisor;
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return 0;
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@ -222,6 +256,8 @@ static void ds1wm_up(struct ds1wm_data *ds1wm_data)
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ds1wm_data->cell->enable(ds1wm_data->pdev);
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divisor = ds1wm_find_divisor(plat->clock_rate);
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dev_dbg(&ds1wm_data->pdev->dev,
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"found divisor 0x%x for clock %d\n", divisor, plat->clock_rate);
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if (divisor == 0) {
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dev_err(&ds1wm_data->pdev->dev,
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"no suitable divisor for %dHz clock\n",
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@ -242,7 +278,7 @@ static void ds1wm_down(struct ds1wm_data *ds1wm_data)
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/* Disable interrupts. */
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ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
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ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0);
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ds1wm_data->int_en_reg_none);
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if (ds1wm_data->cell->disable)
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ds1wm_data->cell->disable(ds1wm_data->pdev);
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@ -279,41 +315,121 @@ static void ds1wm_search(void *data, struct w1_master *master_dev,
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{
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struct ds1wm_data *ds1wm_data = data;
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int i;
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unsigned long long rom_id;
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int ms_discrep_bit = -1;
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u64 r = 0; /* holds the progress of the search */
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u64 r_prime, d;
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unsigned slaves_found = 0;
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unsigned int pass = 0;
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/* XXX We need to iterate for multiple devices per the DS1WM docs.
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* See http://www.maxim-ic.com/appnotes.cfm/appnote_number/120. */
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if (ds1wm_reset(ds1wm_data))
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return;
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dev_dbg(&ds1wm_data->pdev->dev, "search begin\n");
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while (true) {
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++pass;
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if (pass > 100) {
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dev_dbg(&ds1wm_data->pdev->dev,
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"too many attempts (100), search aborted\n");
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return;
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}
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ds1wm_write(ds1wm_data, search_type);
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ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
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if (ds1wm_reset(ds1wm_data)) {
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dev_dbg(&ds1wm_data->pdev->dev,
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"pass: %d reset error (or no slaves)\n", pass);
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break;
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}
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for (rom_id = 0, i = 0; i < 16; i++) {
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dev_dbg(&ds1wm_data->pdev->dev,
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"pass: %d r : %0#18llx writing SEARCH_ROM\n", pass, r);
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ds1wm_write(ds1wm_data, search_type);
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dev_dbg(&ds1wm_data->pdev->dev,
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"pass: %d entering ASM\n", pass);
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ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
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dev_dbg(&ds1wm_data->pdev->dev,
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"pass: %d begining nibble loop\n", pass);
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unsigned char resp, r, d;
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r_prime = 0;
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d = 0;
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/* we work one nibble at a time */
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/* each nibble is interleaved to form a byte */
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for (i = 0; i < 16; i++) {
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resp = ds1wm_read(ds1wm_data, 0x00);
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unsigned char resp, _r, _r_prime, _d;
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r = ((resp & 0x02) >> 1) |
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((resp & 0x08) >> 2) |
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((resp & 0x20) >> 3) |
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((resp & 0x80) >> 4);
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_r = (r >> (4*i)) & 0xf;
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_r = ((_r & 0x1) << 1) |
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((_r & 0x2) << 2) |
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((_r & 0x4) << 3) |
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((_r & 0x8) << 4);
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d = ((resp & 0x01) >> 0) |
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((resp & 0x04) >> 1) |
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((resp & 0x10) >> 2) |
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((resp & 0x40) >> 3);
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/* writes _r, then reads back: */
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resp = ds1wm_read(ds1wm_data, _r);
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rom_id |= (unsigned long long) r << (i * 4);
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if (ds1wm_data->read_error) {
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dev_err(&ds1wm_data->pdev->dev,
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"pass: %d nibble: %d read error\n", pass, i);
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break;
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}
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}
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dev_dbg(&ds1wm_data->pdev->dev, "found 0x%08llX\n", rom_id);
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_r_prime = ((resp & 0x02) >> 1) |
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((resp & 0x08) >> 2) |
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((resp & 0x20) >> 3) |
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((resp & 0x80) >> 4);
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ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
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ds1wm_reset(ds1wm_data);
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_d = ((resp & 0x01) >> 0) |
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((resp & 0x04) >> 1) |
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((resp & 0x10) >> 2) |
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((resp & 0x40) >> 3);
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slave_found(master_dev, rom_id);
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r_prime |= (unsigned long long) _r_prime << (i * 4);
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d |= (unsigned long long) _d << (i * 4);
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}
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if (ds1wm_data->read_error) {
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dev_err(&ds1wm_data->pdev->dev,
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"pass: %d read error, retrying\n", pass);
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break;
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}
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dev_dbg(&ds1wm_data->pdev->dev,
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"pass: %d r\': %0#18llx d:%0#18llx\n",
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pass, r_prime, d);
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dev_dbg(&ds1wm_data->pdev->dev,
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"pass: %d nibble loop complete, exiting ASM\n", pass);
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ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
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dev_dbg(&ds1wm_data->pdev->dev,
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"pass: %d resetting bus\n", pass);
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ds1wm_reset(ds1wm_data);
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if ((r_prime & ((u64)1 << 63)) && (d & ((u64)1 << 63))) {
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dev_err(&ds1wm_data->pdev->dev,
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"pass: %d bus error, retrying\n", pass);
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continue; /* start over */
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}
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dev_dbg(&ds1wm_data->pdev->dev,
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"pass: %d found %0#18llx\n", pass, r_prime);
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slave_found(master_dev, r_prime);
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++slaves_found;
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dev_dbg(&ds1wm_data->pdev->dev,
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"pass: %d complete, preparing next pass\n", pass);
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/* any discrepency found which we already choose the
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'1' branch is now is now irrelevant we reveal the
|
||||
next branch with this: */
|
||||
d &= ~r;
|
||||
/* find last bit set, i.e. the most signif. bit set */
|
||||
ms_discrep_bit = fls64(d) - 1;
|
||||
dev_dbg(&ds1wm_data->pdev->dev,
|
||||
"pass: %d new d:%0#18llx MS discrep bit:%d\n",
|
||||
pass, d, ms_discrep_bit);
|
||||
|
||||
/* prev_ms_discrep_bit = ms_discrep_bit;
|
||||
prepare for next ROM search: */
|
||||
if (ms_discrep_bit == -1)
|
||||
break;
|
||||
|
||||
r = (r & ~(~0ull << (ms_discrep_bit))) | 1 << ms_discrep_bit;
|
||||
} /* end while true */
|
||||
dev_dbg(&ds1wm_data->pdev->dev,
|
||||
"pass: %d total: %d search done ms d bit pos: %d\n", pass,
|
||||
slaves_found, ms_discrep_bit);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------- */
|
||||
|
|
@ -373,15 +489,15 @@ static int ds1wm_probe(struct platform_device *pdev)
|
|||
goto err1;
|
||||
}
|
||||
ds1wm_data->irq = res->start;
|
||||
ds1wm_data->active_high = plat->active_high;
|
||||
ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
|
||||
|
||||
if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
|
||||
irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
|
||||
if (res->flags & IORESOURCE_IRQ_LOWEDGE)
|
||||
irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
|
||||
|
||||
ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED,
|
||||
"ds1wm", ds1wm_data);
|
||||
ret = request_irq(ds1wm_data->irq, ds1wm_isr,
|
||||
IRQF_DISABLED | IRQF_SHARED, "ds1wm", ds1wm_data);
|
||||
if (ret)
|
||||
goto err1;
|
||||
|
||||
|
|
@ -468,5 +584,6 @@ module_exit(ds1wm_exit);
|
|||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
|
||||
"Matt Reimer <mreimer@vpop.net>");
|
||||
"Matt Reimer <mreimer@vpop.net>,"
|
||||
"Jean-Francois Dagenais <dagenaisj@sonatest.com>");
|
||||
MODULE_DESCRIPTION("DS1WM w1 busmaster driver");
|
||||
|
|
|
|||
Reference in New Issue