spi/stmp: remove obsolete driver
This driver is obsolete and can't even be built anymore since the platform it depends has been removed. The STMP series is completely covered by the MXS platform these days, so spi-mxs can be used instead. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Wolfram Sang
Grant Likely
parent
a34fc82e23
commit
266904c779
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@ -379,12 +379,6 @@ config SPI_SIRF
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help
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SPI driver for CSR SiRFprimaII SoCs
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config SPI_STMP3XXX
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tristate "Freescale STMP37xx/378x SPI/SSP controller"
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depends on ARCH_STMP3XXX
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help
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SPI driver for Freescale STMP37xx/378x SoC SSP interface
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config SPI_MXS
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tristate "Freescale MXS SPI controller"
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depends on ARCH_MXS
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@ -60,7 +60,6 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
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obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
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obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
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obj-$(CONFIG_SPI_STMP3XXX) += spi-stmp.o
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obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
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obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
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obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o
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@ -1,664 +0,0 @@
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/*
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* Freescale STMP378X SPI master driver
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*
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* Author: dmitry pervushin <dimka@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <mach/platform.h>
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#include <mach/stmp3xxx.h>
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#include <mach/dma.h>
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#include <mach/regs-ssp.h>
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#include <mach/regs-apbh.h>
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/* 0 means DMA mode(recommended, default), !0 - PIO mode */
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static int pio;
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static int clock;
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/* default timeout for busy waits is 2 seconds */
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#define STMP_SPI_TIMEOUT (2 * HZ)
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struct stmp_spi {
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int id;
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void * __iomem regs; /* vaddr of the control registers */
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int irq, err_irq;
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u32 dma;
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struct stmp3xxx_dma_descriptor d;
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u32 speed_khz;
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u32 saved_timings;
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u32 divider;
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struct clk *clk;
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struct device *master_dev;
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struct work_struct work;
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struct workqueue_struct *workqueue;
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/* lock protects queue access */
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spinlock_t lock;
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struct list_head queue;
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struct completion done;
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};
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#define busy_wait(cond) \
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({ \
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unsigned long end_jiffies = jiffies + STMP_SPI_TIMEOUT; \
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bool succeeded = false; \
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do { \
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if (cond) { \
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succeeded = true; \
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break; \
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} \
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cpu_relax(); \
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} while (time_before(jiffies, end_jiffies)); \
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succeeded; \
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})
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/**
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* stmp_spi_init_hw
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* Initialize the SSP port
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*/
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static int stmp_spi_init_hw(struct stmp_spi *ss)
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{
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int err = 0;
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void *pins = ss->master_dev->platform_data;
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err = stmp3xxx_request_pin_group(pins, dev_name(ss->master_dev));
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if (err)
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goto out;
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ss->clk = clk_get(NULL, "ssp");
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if (IS_ERR(ss->clk)) {
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err = PTR_ERR(ss->clk);
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goto out_free_pins;
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}
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clk_enable(ss->clk);
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stmp3xxx_reset_block(ss->regs, false);
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stmp3xxx_dma_reset_channel(ss->dma);
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return 0;
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out_free_pins:
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stmp3xxx_release_pin_group(pins, dev_name(ss->master_dev));
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out:
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return err;
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}
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static void stmp_spi_release_hw(struct stmp_spi *ss)
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{
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void *pins = ss->master_dev->platform_data;
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if (ss->clk && !IS_ERR(ss->clk)) {
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clk_disable(ss->clk);
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clk_put(ss->clk);
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}
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stmp3xxx_release_pin_group(pins, dev_name(ss->master_dev));
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}
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static int stmp_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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u8 bits_per_word;
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u32 hz;
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struct stmp_spi *ss = spi_master_get_devdata(spi->master);
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u16 rate;
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bits_per_word = spi->bits_per_word;
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if (t && t->bits_per_word)
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bits_per_word = t->bits_per_word;
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/*
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* Calculate speed:
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* - by default, use maximum speed from ssp clk
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* - if device overrides it, use it
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* - if transfer specifies other speed, use transfer's one
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*/
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hz = 1000 * ss->speed_khz / ss->divider;
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if (spi->max_speed_hz)
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hz = min(hz, spi->max_speed_hz);
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if (t && t->speed_hz)
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hz = min(hz, t->speed_hz);
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if (hz == 0) {
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dev_err(&spi->dev, "Cannot continue with zero clock\n");
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return -EINVAL;
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}
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if (bits_per_word != 8) {
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dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
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__func__, bits_per_word);
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return -EINVAL;
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}
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dev_dbg(&spi->dev, "Requested clk rate = %uHz, max = %uHz/%d = %uHz\n",
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hz, ss->speed_khz, ss->divider,
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ss->speed_khz * 1000 / ss->divider);
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if (ss->speed_khz * 1000 / ss->divider < hz) {
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dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n",
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__func__, hz);
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return -EINVAL;
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}
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rate = 1000 * ss->speed_khz/ss->divider/hz;
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writel(BF(ss->divider, SSP_TIMING_CLOCK_DIVIDE) |
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BF(rate - 1, SSP_TIMING_CLOCK_RATE),
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HW_SSP_TIMING + ss->regs);
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writel(BF(1 /* mode SPI */, SSP_CTRL1_SSP_MODE) |
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BF(4 /* 8 bits */, SSP_CTRL1_WORD_LENGTH) |
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((spi->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
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((spi->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0) |
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(pio ? 0 : BM_SSP_CTRL1_DMA_ENABLE),
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ss->regs + HW_SSP_CTRL1);
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return 0;
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}
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static int stmp_spi_setup(struct spi_device *spi)
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{
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/* spi_setup() does basic checks,
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* stmp_spi_setup_transfer() does more later
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*/
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if (spi->bits_per_word != 8) {
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dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
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__func__, spi->bits_per_word);
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return -EINVAL;
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}
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return 0;
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}
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static inline u32 stmp_spi_cs(unsigned cs)
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{
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return ((cs & 1) ? BM_SSP_CTRL0_WAIT_FOR_CMD : 0) |
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((cs & 2) ? BM_SSP_CTRL0_WAIT_FOR_IRQ : 0);
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}
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static int stmp_spi_txrx_dma(struct stmp_spi *ss, int cs,
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unsigned char *buf, dma_addr_t dma_buf, int len,
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int first, int last, bool write)
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{
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u32 c0 = 0;
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dma_addr_t spi_buf_dma = dma_buf;
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int status = 0;
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enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
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c0 |= (first ? BM_SSP_CTRL0_LOCK_CS : 0);
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c0 |= (last ? BM_SSP_CTRL0_IGNORE_CRC : 0);
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c0 |= (write ? 0 : BM_SSP_CTRL0_READ);
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c0 |= BM_SSP_CTRL0_DATA_XFER;
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c0 |= stmp_spi_cs(cs);
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c0 |= BF(len, SSP_CTRL0_XFER_COUNT);
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if (!dma_buf)
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spi_buf_dma = dma_map_single(ss->master_dev, buf, len, dir);
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ss->d.command->cmd =
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BF(len, APBH_CHn_CMD_XFER_COUNT) |
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BF(1, APBH_CHn_CMD_CMDWORDS) |
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BM_APBH_CHn_CMD_WAIT4ENDCMD |
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BM_APBH_CHn_CMD_IRQONCMPLT |
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BF(write ? BV_APBH_CHn_CMD_COMMAND__DMA_READ :
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BV_APBH_CHn_CMD_COMMAND__DMA_WRITE,
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APBH_CHn_CMD_COMMAND);
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ss->d.command->pio_words[0] = c0;
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ss->d.command->buf_ptr = spi_buf_dma;
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stmp3xxx_dma_reset_channel(ss->dma);
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stmp3xxx_dma_clear_interrupt(ss->dma);
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stmp3xxx_dma_enable_interrupt(ss->dma);
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init_completion(&ss->done);
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stmp3xxx_dma_go(ss->dma, &ss->d, 1);
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wait_for_completion(&ss->done);
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if (!busy_wait(readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN))
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status = -ETIMEDOUT;
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if (!dma_buf)
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dma_unmap_single(ss->master_dev, spi_buf_dma, len, dir);
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return status;
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}
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static inline void stmp_spi_enable(struct stmp_spi *ss)
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{
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stmp3xxx_setl(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0);
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stmp3xxx_clearl(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0);
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}
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static inline void stmp_spi_disable(struct stmp_spi *ss)
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{
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stmp3xxx_clearl(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0);
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stmp3xxx_setl(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0);
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}
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static int stmp_spi_txrx_pio(struct stmp_spi *ss, int cs,
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unsigned char *buf, int len,
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bool first, bool last, bool write)
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{
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if (first)
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stmp_spi_enable(ss);
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stmp3xxx_setl(stmp_spi_cs(cs), ss->regs + HW_SSP_CTRL0);
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while (len--) {
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if (last && len <= 0)
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stmp_spi_disable(ss);
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stmp3xxx_clearl(BM_SSP_CTRL0_XFER_COUNT,
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ss->regs + HW_SSP_CTRL0);
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stmp3xxx_setl(1, ss->regs + HW_SSP_CTRL0);
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if (write)
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stmp3xxx_clearl(BM_SSP_CTRL0_READ,
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ss->regs + HW_SSP_CTRL0);
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else
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stmp3xxx_setl(BM_SSP_CTRL0_READ,
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ss->regs + HW_SSP_CTRL0);
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/* Run! */
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stmp3xxx_setl(BM_SSP_CTRL0_RUN, ss->regs + HW_SSP_CTRL0);
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if (!busy_wait(readl(ss->regs + HW_SSP_CTRL0) &
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BM_SSP_CTRL0_RUN))
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break;
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if (write)
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writel(*buf, ss->regs + HW_SSP_DATA);
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/* Set TRANSFER */
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stmp3xxx_setl(BM_SSP_CTRL0_DATA_XFER, ss->regs + HW_SSP_CTRL0);
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if (!write) {
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if (busy_wait((readl(ss->regs + HW_SSP_STATUS) &
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BM_SSP_STATUS_FIFO_EMPTY)))
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break;
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*buf = readl(ss->regs + HW_SSP_DATA) & 0xFF;
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}
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if (!busy_wait(readl(ss->regs + HW_SSP_CTRL0) &
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BM_SSP_CTRL0_RUN))
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break;
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/* advance to the next byte */
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buf++;
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}
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return len < 0 ? 0 : -ETIMEDOUT;
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}
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static int stmp_spi_handle_message(struct stmp_spi *ss, struct spi_message *m)
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{
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bool first, last;
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struct spi_transfer *t, *tmp_t;
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int status = 0;
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int cs;
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cs = m->spi->chip_select;
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list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
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first = (&t->transfer_list == m->transfers.next);
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last = (&t->transfer_list == m->transfers.prev);
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if (first || t->speed_hz || t->bits_per_word)
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stmp_spi_setup_transfer(m->spi, t);
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/* reject "not last" transfers which request to change cs */
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if (t->cs_change && !last) {
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dev_err(&m->spi->dev,
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"Message with t->cs_change has been skipped\n");
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continue;
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}
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if (t->tx_buf) {
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status = pio ?
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stmp_spi_txrx_pio(ss, cs, (void *)t->tx_buf,
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t->len, first, last, true) :
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stmp_spi_txrx_dma(ss, cs, (void *)t->tx_buf,
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t->tx_dma, t->len, first, last, true);
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#ifdef DEBUG
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if (t->len < 0x10)
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print_hex_dump_bytes("Tx ",
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DUMP_PREFIX_OFFSET,
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t->tx_buf, t->len);
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else
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pr_debug("Tx: %d bytes\n", t->len);
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#endif
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}
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if (t->rx_buf) {
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status = pio ?
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stmp_spi_txrx_pio(ss, cs, t->rx_buf,
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t->len, first, last, false) :
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stmp_spi_txrx_dma(ss, cs, t->rx_buf,
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t->rx_dma, t->len, first, last, false);
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#ifdef DEBUG
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if (t->len < 0x10)
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print_hex_dump_bytes("Rx ",
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DUMP_PREFIX_OFFSET,
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t->rx_buf, t->len);
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else
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pr_debug("Rx: %d bytes\n", t->len);
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#endif
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}
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (status)
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break;
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}
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return status;
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}
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/**
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* stmp_spi_handle - handle messages from the queue
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*/
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static void stmp_spi_handle(struct work_struct *w)
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{
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struct stmp_spi *ss = container_of(w, struct stmp_spi, work);
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unsigned long flags;
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struct spi_message *m;
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spin_lock_irqsave(&ss->lock, flags);
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while (!list_empty(&ss->queue)) {
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m = list_entry(ss->queue.next, struct spi_message, queue);
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list_del_init(&m->queue);
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spin_unlock_irqrestore(&ss->lock, flags);
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m->status = stmp_spi_handle_message(ss, m);
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m->complete(m->context);
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spin_lock_irqsave(&ss->lock, flags);
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}
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spin_unlock_irqrestore(&ss->lock, flags);
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return;
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}
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/**
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* stmp_spi_transfer - perform message transfer.
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* Called indirectly from spi_async, queues all the messages to
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* spi_handle_message.
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* @spi: spi device
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* @m: message to be queued
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*/
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static int stmp_spi_transfer(struct spi_device *spi, struct spi_message *m)
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{
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struct stmp_spi *ss = spi_master_get_devdata(spi->master);
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unsigned long flags;
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m->status = -EINPROGRESS;
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spin_lock_irqsave(&ss->lock, flags);
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list_add_tail(&m->queue, &ss->queue);
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queue_work(ss->workqueue, &ss->work);
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spin_unlock_irqrestore(&ss->lock, flags);
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return 0;
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}
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static irqreturn_t stmp_spi_irq(int irq, void *dev_id)
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{
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struct stmp_spi *ss = dev_id;
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|
||||
stmp3xxx_dma_clear_interrupt(ss->dma);
|
||||
complete(&ss->done);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t stmp_spi_irq_err(int irq, void *dev_id)
|
||||
{
|
||||
struct stmp_spi *ss = dev_id;
|
||||
u32 c1, st;
|
||||
|
||||
c1 = readl(ss->regs + HW_SSP_CTRL1);
|
||||
st = readl(ss->regs + HW_SSP_STATUS);
|
||||
dev_err(ss->master_dev, "%s: status = 0x%08X, c1 = 0x%08X\n",
|
||||
__func__, st, c1);
|
||||
stmp3xxx_clearl(c1 & 0xCCCC0000, ss->regs + HW_SSP_CTRL1);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int __devinit stmp_spi_probe(struct platform_device *dev)
|
||||
{
|
||||
int err = 0;
|
||||
struct spi_master *master;
|
||||
struct stmp_spi *ss;
|
||||
struct resource *r;
|
||||
|
||||
master = spi_alloc_master(&dev->dev, sizeof(struct stmp_spi));
|
||||
if (master == NULL) {
|
||||
err = -ENOMEM;
|
||||
goto out0;
|
||||
}
|
||||
master->flags = SPI_MASTER_HALF_DUPLEX;
|
||||
|
||||
ss = spi_master_get_devdata(master);
|
||||
platform_set_drvdata(dev, master);
|
||||
|
||||
/* Get resources(memory, IRQ) associated with the device */
|
||||
r = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
||||
if (r == NULL) {
|
||||
err = -ENODEV;
|
||||
goto out_put_master;
|
||||
}
|
||||
ss->regs = ioremap(r->start, resource_size(r));
|
||||
if (!ss->regs) {
|
||||
err = -EINVAL;
|
||||
goto out_put_master;
|
||||
}
|
||||
|
||||
ss->master_dev = &dev->dev;
|
||||
ss->id = dev->id;
|
||||
|
||||
INIT_WORK(&ss->work, stmp_spi_handle);
|
||||
INIT_LIST_HEAD(&ss->queue);
|
||||
spin_lock_init(&ss->lock);
|
||||
|
||||
ss->workqueue = create_singlethread_workqueue(dev_name(&dev->dev));
|
||||
if (!ss->workqueue) {
|
||||
err = -ENXIO;
|
||||
goto out_put_master;
|
||||
}
|
||||
master->transfer = stmp_spi_transfer;
|
||||
master->setup = stmp_spi_setup;
|
||||
|
||||
/* the spi->mode bits understood by this driver: */
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
||||
|
||||
ss->irq = platform_get_irq(dev, 0);
|
||||
if (ss->irq < 0) {
|
||||
err = ss->irq;
|
||||
goto out_put_master;
|
||||
}
|
||||
ss->err_irq = platform_get_irq(dev, 1);
|
||||
if (ss->err_irq < 0) {
|
||||
err = ss->err_irq;
|
||||
goto out_put_master;
|
||||
}
|
||||
|
||||
r = platform_get_resource(dev, IORESOURCE_DMA, 0);
|
||||
if (r == NULL) {
|
||||
err = -ENODEV;
|
||||
goto out_put_master;
|
||||
}
|
||||
|
||||
ss->dma = r->start;
|
||||
err = stmp3xxx_dma_request(ss->dma, &dev->dev, dev_name(&dev->dev));
|
||||
if (err)
|
||||
goto out_put_master;
|
||||
|
||||
err = stmp3xxx_dma_allocate_command(ss->dma, &ss->d);
|
||||
if (err)
|
||||
goto out_free_dma;
|
||||
|
||||
master->bus_num = dev->id;
|
||||
master->num_chipselect = 1;
|
||||
|
||||
/* SPI controller initializations */
|
||||
err = stmp_spi_init_hw(ss);
|
||||
if (err) {
|
||||
dev_dbg(&dev->dev, "cannot initialize hardware\n");
|
||||
goto out_free_dma_desc;
|
||||
}
|
||||
|
||||
if (clock) {
|
||||
dev_info(&dev->dev, "clock rate forced to %d\n", clock);
|
||||
clk_set_rate(ss->clk, clock);
|
||||
}
|
||||
ss->speed_khz = clk_get_rate(ss->clk);
|
||||
ss->divider = 2;
|
||||
dev_info(&dev->dev, "max possible speed %d = %ld/%d kHz\n",
|
||||
ss->speed_khz, clk_get_rate(ss->clk), ss->divider);
|
||||
|
||||
/* Register for SPI interrupt */
|
||||
err = request_irq(ss->irq, stmp_spi_irq, 0,
|
||||
dev_name(&dev->dev), ss);
|
||||
if (err) {
|
||||
dev_dbg(&dev->dev, "request_irq failed, %d\n", err);
|
||||
goto out_release_hw;
|
||||
}
|
||||
|
||||
/* ..and shared interrupt for all SSP controllers */
|
||||
err = request_irq(ss->err_irq, stmp_spi_irq_err, IRQF_SHARED,
|
||||
dev_name(&dev->dev), ss);
|
||||
if (err) {
|
||||
dev_dbg(&dev->dev, "request_irq(error) failed, %d\n", err);
|
||||
goto out_free_irq;
|
||||
}
|
||||
|
||||
err = spi_register_master(master);
|
||||
if (err) {
|
||||
dev_dbg(&dev->dev, "cannot register spi master, %d\n", err);
|
||||
goto out_free_irq_2;
|
||||
}
|
||||
dev_info(&dev->dev, "at (mapped) 0x%08X, irq=%d, bus %d, %s mode\n",
|
||||
(u32)ss->regs, ss->irq, master->bus_num,
|
||||
pio ? "PIO" : "DMA");
|
||||
return 0;
|
||||
|
||||
out_free_irq_2:
|
||||
free_irq(ss->err_irq, ss);
|
||||
out_free_irq:
|
||||
free_irq(ss->irq, ss);
|
||||
out_free_dma_desc:
|
||||
stmp3xxx_dma_free_command(ss->dma, &ss->d);
|
||||
out_free_dma:
|
||||
stmp3xxx_dma_release(ss->dma);
|
||||
out_release_hw:
|
||||
stmp_spi_release_hw(ss);
|
||||
out_put_master:
|
||||
if (ss->workqueue)
|
||||
destroy_workqueue(ss->workqueue);
|
||||
if (ss->regs)
|
||||
iounmap(ss->regs);
|
||||
platform_set_drvdata(dev, NULL);
|
||||
spi_master_put(master);
|
||||
out0:
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __devexit stmp_spi_remove(struct platform_device *dev)
|
||||
{
|
||||
struct stmp_spi *ss;
|
||||
struct spi_master *master;
|
||||
|
||||
master = spi_master_get(platform_get_drvdata(dev));
|
||||
ss = spi_master_get_devdata(master);
|
||||
|
||||
spi_unregister_master(master);
|
||||
|
||||
free_irq(ss->err_irq, ss);
|
||||
free_irq(ss->irq, ss);
|
||||
stmp3xxx_dma_free_command(ss->dma, &ss->d);
|
||||
stmp3xxx_dma_release(ss->dma);
|
||||
stmp_spi_release_hw(ss);
|
||||
destroy_workqueue(ss->workqueue);
|
||||
iounmap(ss->regs);
|
||||
spi_master_put(master);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int stmp_spi_suspend(struct platform_device *pdev, pm_message_t pmsg)
|
||||
{
|
||||
struct stmp_spi *ss;
|
||||
struct spi_master *master;
|
||||
|
||||
master = platform_get_drvdata(pdev);
|
||||
ss = spi_master_get_devdata(master);
|
||||
|
||||
ss->saved_timings = readl(HW_SSP_TIMING + ss->regs);
|
||||
clk_disable(ss->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stmp_spi_resume(struct platform_device *pdev)
|
||||
{
|
||||
struct stmp_spi *ss;
|
||||
struct spi_master *master;
|
||||
|
||||
master = platform_get_drvdata(pdev);
|
||||
ss = spi_master_get_devdata(master);
|
||||
|
||||
clk_enable(ss->clk);
|
||||
stmp3xxx_reset_block(ss->regs, false);
|
||||
writel(ss->saved_timings, ss->regs + HW_SSP_TIMING);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
#define stmp_spi_suspend NULL
|
||||
#define stmp_spi_resume NULL
|
||||
#endif
|
||||
|
||||
static struct platform_driver stmp_spi_driver = {
|
||||
.probe = stmp_spi_probe,
|
||||
.remove = __devexit_p(stmp_spi_remove),
|
||||
.driver = {
|
||||
.name = "stmp3xxx_ssp",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.suspend = stmp_spi_suspend,
|
||||
.resume = stmp_spi_resume,
|
||||
};
|
||||
module_platform_driver(stmp_spi_driver);
|
||||
|
||||
module_param(pio, int, S_IRUGO);
|
||||
module_param(clock, int, S_IRUGO);
|
||||
MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com>");
|
||||
MODULE_DESCRIPTION("STMP3xxx SPI/SSP driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Reference in New Issue