Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, pvclock: Remove leftover scale_delta() function x86, apic: Remove double #include x86: Adjust section annotations in AMD Fam10 MMCONF enabling code x86, UV: Update node controller MMRs x86: Remove unnecessary casts of void ptr returning alloc function return values x86: Address gcc4.6 "set but not used" warnings in apic.h x86, mm: Fix section mismatch in tlb.c
This commit is contained in:
Linus Torvalds
commit
25a34554d6
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@ -141,13 +141,13 @@ static inline void native_apic_msr_write(u32 reg, u32 v)
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static inline u32 native_apic_msr_read(u32 reg)
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{
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u32 low, high;
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u64 msr;
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if (reg == APIC_DFR)
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return -1;
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rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
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return low;
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rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
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return (u32)msr;
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}
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static inline void native_x2apic_wait_icr_idle(void)
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@ -181,12 +181,12 @@ extern void enable_x2apic(void);
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extern void x2apic_icr_write(u32 low, u32 id);
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static inline int x2apic_enabled(void)
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{
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int msr, msr2;
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u64 msr;
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if (!cpu_has_x2apic)
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return 0;
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rdmsr(MSR_IA32_APICBASE, msr, msr2);
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rdmsrl(MSR_IA32_APICBASE, msr);
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if (msr & X2APIC_ENABLE)
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return 1;
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return 0;
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@ -805,6 +805,78 @@ union uvh_node_present_table_u {
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
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#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
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/* ========================================================================= */
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@ -856,6 +928,29 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_CONFIG_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
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#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
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#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
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#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
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#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
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#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
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#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
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union uvh_rh_gam_config_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_config_mmr_s {
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unsigned long m_skt : 6; /* RW */
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unsigned long n_skt : 4; /* RW */
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unsigned long rsvd_10_11: 2; /* */
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unsigned long mmiol_cfg : 1; /* RW */
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unsigned long rsvd_13_63: 51; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
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/* ========================================================================= */
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@ -987,97 +1082,5 @@ union uvh_rtc1_int_config_u {
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ADDR_MAP_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
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#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
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#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
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#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
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#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
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union uvh_si_addr_map_config_u {
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unsigned long v;
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struct uvh_si_addr_map_config_s {
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unsigned long m_skt : 6; /* RW */
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unsigned long rsvd_6_7: 2; /* */
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unsigned long n_skt : 4; /* RW */
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unsigned long rsvd_12_63: 52; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
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union uvh_si_alias0_overlay_config_u {
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unsigned long v;
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struct uvh_si_alias0_overlay_config_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
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union uvh_si_alias1_overlay_config_u {
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unsigned long v;
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struct uvh_si_alias1_overlay_config_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
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union uvh_si_alias2_overlay_config_u {
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unsigned long v;
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struct uvh_si_alias2_overlay_config_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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#endif /* _ASM_X86_UV_UV_MMRS_H */
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#endif /* __ASM_UV_MMRS_X86_H__ */
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@ -52,7 +52,6 @@
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#include <asm/mce.h>
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#include <asm/kvm_para.h>
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#include <asm/tsc.h>
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#include <asm/atomic.h>
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unsigned int num_processors;
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@ -379,14 +379,14 @@ struct redir_addr {
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#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
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static __initdata struct redir_addr redir_addrs[] = {
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
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};
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static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
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{
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union uvh_si_alias0_overlay_config_u alias;
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union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
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union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
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int i;
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@ -660,7 +660,7 @@ void uv_nmi_init(void)
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void __init uv_system_init(void)
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{
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union uvh_si_addr_map_config_u m_n_config;
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union uvh_rh_gam_config_mmr_u m_n_config;
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union uvh_node_id_u node_id;
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unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
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int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
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@ -670,7 +670,7 @@ void __init uv_system_init(void)
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map_low_mmrs();
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m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
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m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
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m_val = m_n_config.s.m_skt;
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n_val = m_n_config.s.n_skt;
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mmr_base =
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|
|
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@ -212,7 +212,7 @@ static int install_equiv_cpu_table(const u8 *buf)
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return 0;
|
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}
|
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|
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equiv_cpu_table = (struct equiv_cpu_entry *) vmalloc(size);
|
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equiv_cpu_table = vmalloc(size);
|
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if (!equiv_cpu_table) {
|
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pr_err("failed to allocate equivalent CPU table\n");
|
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return 0;
|
||||
|
|
|
|||
|
|
@ -217,13 +217,13 @@ void __cpuinit fam10h_check_enable_mmcfg(void)
|
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wrmsrl(address, val);
|
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}
|
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|
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static int __devinit set_check_enable_amd_mmconf(const struct dmi_system_id *d)
|
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static int __init set_check_enable_amd_mmconf(const struct dmi_system_id *d)
|
||||
{
|
||||
pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dmi_system_id __cpuinitconst mmconf_dmi_table[] = {
|
||||
static const struct dmi_system_id __initconst mmconf_dmi_table[] = {
|
||||
{
|
||||
.callback = set_check_enable_amd_mmconf,
|
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.ident = "Sun Microsystems Machine",
|
||||
|
|
@ -234,7 +234,8 @@ static const struct dmi_system_id __cpuinitconst mmconf_dmi_table[] = {
|
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{}
|
||||
};
|
||||
|
||||
void __cpuinit check_enable_amd_mmconf_dmi(void)
|
||||
/* Called from a __cpuinit function, but only on the BSP. */
|
||||
void __ref check_enable_amd_mmconf_dmi(void)
|
||||
{
|
||||
dmi_check_system(mmconf_dmi_table);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -41,44 +41,6 @@ void pvclock_set_flags(u8 flags)
|
|||
valid_flags = flags;
|
||||
}
|
||||
|
||||
/*
|
||||
* Scale a 64-bit delta by scaling and multiplying by a 32-bit fraction,
|
||||
* yielding a 64-bit result.
|
||||
*/
|
||||
static inline u64 scale_delta(u64 delta, u32 mul_frac, int shift)
|
||||
{
|
||||
u64 product;
|
||||
#ifdef __i386__
|
||||
u32 tmp1, tmp2;
|
||||
#endif
|
||||
|
||||
if (shift < 0)
|
||||
delta >>= -shift;
|
||||
else
|
||||
delta <<= shift;
|
||||
|
||||
#ifdef __i386__
|
||||
__asm__ (
|
||||
"mul %5 ; "
|
||||
"mov %4,%%eax ; "
|
||||
"mov %%edx,%4 ; "
|
||||
"mul %5 ; "
|
||||
"xor %5,%5 ; "
|
||||
"add %4,%%eax ; "
|
||||
"adc %5,%%edx ; "
|
||||
: "=A" (product), "=r" (tmp1), "=r" (tmp2)
|
||||
: "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (mul_frac) );
|
||||
#elif defined(__x86_64__)
|
||||
__asm__ (
|
||||
"mul %%rdx ; shrd $32,%%rdx,%%rax"
|
||||
: "=a" (product) : "0" (delta), "d" ((u64)mul_frac) );
|
||||
#else
|
||||
#error implement me!
|
||||
#endif
|
||||
|
||||
return product;
|
||||
}
|
||||
|
||||
static u64 pvclock_get_nsec_offset(struct pvclock_shadow_time *shadow)
|
||||
{
|
||||
u64 delta = native_read_tsc() - shadow->tsc_timestamp;
|
||||
|
|
|
|||
|
|
@ -251,7 +251,7 @@ static void __cpuinit calculate_tlb_offset(void)
|
|||
}
|
||||
}
|
||||
|
||||
static int tlb_cpuhp_notify(struct notifier_block *n,
|
||||
static int __cpuinit tlb_cpuhp_notify(struct notifier_block *n,
|
||||
unsigned long action, void *hcpu)
|
||||
{
|
||||
switch (action & 0xf) {
|
||||
|
|
|
|||
|
|
@ -1343,8 +1343,8 @@ uv_activation_descriptor_init(int node, int pnode)
|
|||
* each bau_desc is 64 bytes; there are 8 (UV_ITEMS_PER_DESCRIPTOR)
|
||||
* per cpu; and up to 32 (UV_ADP_SIZE) cpu's per uvhub
|
||||
*/
|
||||
bau_desc = (struct bau_desc *)kmalloc_node(sizeof(struct bau_desc)*
|
||||
UV_ADP_SIZE*UV_ITEMS_PER_DESCRIPTOR, GFP_KERNEL, node);
|
||||
bau_desc = kmalloc_node(sizeof(struct bau_desc) * UV_ADP_SIZE
|
||||
* UV_ITEMS_PER_DESCRIPTOR, GFP_KERNEL, node);
|
||||
BUG_ON(!bau_desc);
|
||||
|
||||
pa = uv_gpa(bau_desc); /* need the real nasid*/
|
||||
|
|
@ -1402,9 +1402,9 @@ uv_payload_queue_init(int node, int pnode)
|
|||
struct bau_payload_queue_entry *pqp_malloc;
|
||||
struct bau_control *bcp;
|
||||
|
||||
pqp = (struct bau_payload_queue_entry *) kmalloc_node(
|
||||
(DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry),
|
||||
GFP_KERNEL, node);
|
||||
pqp = kmalloc_node((DEST_Q_SIZE + 1)
|
||||
* sizeof(struct bau_payload_queue_entry),
|
||||
GFP_KERNEL, node);
|
||||
BUG_ON(!pqp);
|
||||
pqp_malloc = pqp;
|
||||
|
||||
|
|
@ -1520,8 +1520,7 @@ static void __init uv_init_per_cpu(int nuvhubs)
|
|||
|
||||
timeout_us = calculate_destination_timeout();
|
||||
|
||||
uvhub_descs = (struct uvhub_desc *)
|
||||
kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
|
||||
uvhub_descs = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
|
||||
memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
|
||||
uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
|
||||
for_each_present_cpu(cpu) {
|
||||
|
|
|
|||
Reference in New Issue