atmel_lcdfb: Fix STN LCD support
Fixes STN LCD support for the atmel_lcdfb framebuffer driver. This patch is the result of a work from Jan Altenberg and has been tested on a Hitachi SP06Q002 on at91sam9261ek. It adds a Kconfig switch that enables the proper LCD in the board configuration file (STN or TFT). The switch is used in arch/arm/mach-at91/at91sam9261_devices.c & board-sam9261ek.c as an example. This patch includes the "Fix wrong line_length calculation" little one from Jan and Haavard (submitted earlier). AT91 platform informations are directly submitted trough the at91 maintainer, here : http://article.gmane.org/gmane.linux.kernel/543158 Signed-off-by: Nicolas Ferre <nicolas.ferre@rfo.atmel.com> Cc: "Antonino A. Daplas" <adaplas@gmail.com> Cc: Jan Altenberg <jan.altenberg@linutronix.de> Cc: Patrice Vilchez <patrice.vilchez@rfo.atmel.com> Cc: Andrew Victor <andrew@sanpeople.com> Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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parent
029641151b
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250a269da4
2 changed files with 64 additions and 8 deletions
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@ -849,6 +849,16 @@ config FB_INTSRAM
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Say Y if you want to map Frame Buffer in internal SRAM. Say N if you want
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to let frame buffer in external SDRAM.
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config FB_ATMEL_STN
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bool "Use a STN display with AT91/AT32 LCD Controller"
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depends on FB_ATMEL && MACH_AT91SAM9261EK
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default n
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help
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Say Y if you want to connect a STN LCD display to the AT91/AT32 LCD
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Controller. Say N if you want to connect a TFT.
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If unsure, say N.
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config FB_NVIDIA
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tristate "nVidia Framebuffer Support"
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depends on FB && PCI
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@ -79,6 +79,29 @@ static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
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.accel = FB_ACCEL_NONE,
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};
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static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
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{
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unsigned long value;
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if (!(cpu_is_at91sam9261() || cpu_is_at32ap7000()))
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return xres;
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value = xres;
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if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
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/* STN display */
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if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
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value *= 3;
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}
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if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
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|| ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
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&& (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
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value = DIV_ROUND_UP(value, 4);
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else
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value = DIV_ROUND_UP(value, 8);
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}
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return value;
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}
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static void atmel_lcdfb_update_dma(struct fb_info *info,
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struct fb_var_screeninfo *var)
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@ -181,6 +204,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
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var->xoffset = var->yoffset = 0;
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switch (var->bits_per_pixel) {
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case 1:
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case 2:
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case 4:
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case 8:
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@ -228,8 +252,10 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
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static int atmel_lcdfb_set_par(struct fb_info *info)
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{
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struct atmel_lcdfb_info *sinfo = info->par;
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unsigned long hozval_linesz;
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unsigned long value;
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unsigned long clk_value_khz;
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unsigned long bits_per_line;
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dev_dbg(info->device, "%s:\n", __func__);
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dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
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@ -241,12 +267,15 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
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lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
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if (info->var.bits_per_pixel <= 8)
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if (info->var.bits_per_pixel == 1)
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info->fix.visual = FB_VISUAL_MONO01;
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else if (info->var.bits_per_pixel <= 8)
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
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else
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info->fix.visual = FB_VISUAL_TRUECOLOR;
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info->fix.line_length = info->var.xres_virtual * (info->var.bits_per_pixel / 8);
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bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
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info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
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/* Re-initialize the DMA engine... */
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dev_dbg(info->device, " * update DMA engine\n");
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@ -262,18 +291,21 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
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/* Set pixel clock */
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clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
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value = clk_value_khz / PICOS2KHZ(info->var.pixclock);
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if (clk_value_khz % PICOS2KHZ(info->var.pixclock))
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value++;
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value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
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value = (value / 2) - 1;
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dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", value);
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if (value <= 0) {
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dev_notice(info->device, "Bypassing pixel clock divider\n");
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
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} else
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} else {
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET);
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info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1)));
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dev_dbg(info->device, " updated pixclk: %lu KHz\n",
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PICOS2KHZ(info->var.pixclock));
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}
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/* Initialize control register 2 */
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value = sinfo->default_lcdcon2;
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@ -311,9 +343,14 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
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dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
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/* Horizontal value (aka line size) */
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hozval_linesz = compute_hozval(info->var.xres,
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lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
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/* Display size */
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value = (info->var.xres - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
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value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
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value |= info->var.yres - 1;
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dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
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/* FIFO Threshold: Use formula from data sheet */
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@ -421,6 +458,15 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
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ret = 0;
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}
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break;
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case FB_VISUAL_MONO01:
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if (regno < 2) {
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val = (regno == 0) ? 0x00 : 0x1F;
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lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
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ret = 0;
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}
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break;
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}
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return ret;
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