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x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB 

The file names are somehow misleading as the code is not specific to
AMD K8 CPUs anymore. The files accomodate code for other AMD CPU
northbridges as well.

Same is true for the config option which is valid for AMD CPU
northbridges in general and not specific to K8.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20100917160343.GD4958@loge.amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
Andreas Herrmann 2010-09-17 18:03:43 +02:00 committed by H. Peter Anvin
parent 900f9ac9f1
commit 23ac4ae827
14 changed files with 22 additions and 22 deletions
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4
arch/x86/Kconfig
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@ -670,7 +670,7 @@ config GART_IOMMU
bool "GART IOMMU support" if EMBEDDED
default y
select SWIOTLB
depends on X86_64 && PCI && K8_NB
depends on X86_64 && PCI && AMD_NB
---help---
Support for full DMA access of devices with 32bit memory access only
on systems with more than 3GB. This is usually needed for USB,
@ -2076,7 +2076,7 @@ config OLPC_OPENFIRMWARE
endif # X86_32
config K8_NB
config AMD_NB
def_bool y
depends on CPU_SUP_AMD && PCI

8
arch/x86/include/asm/k8.h → arch/x86/include/asm/amd_nb.h
View File

@ -1,5 +1,5 @@
#ifndef _ASM_X86_K8_H
#define _ASM_X86_K8_H
#ifndef _ASM_X86_AMD_NB_H
#define _ASM_X86_AMD_NB_H
#include <linux/pci.h>
@ -20,7 +20,7 @@ struct k8_northbridge_info {
};
extern struct k8_northbridge_info k8_northbridges;
#ifdef CONFIG_K8_NB
#ifdef CONFIG_AMD_NB
static inline struct pci_dev *node_to_k8_nb_misc(int node)
{
@ -36,4 +36,4 @@ static inline struct pci_dev *node_to_k8_nb_misc(int node)
#endif
#endif /* _ASM_X86_K8_H */
#endif /* _ASM_X86_AMD_NB_H */

2
arch/x86/kernel/Makefile
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@ -87,7 +87,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_HPET_TIMER) += hpet.o
obj-$(CONFIG_APB_TIMER) += apb_timer.o
obj-$(CONFIG_K8_NB) += k8.o
obj-$(CONFIG_AMD_NB) += amd_nb.o
obj-$(CONFIG_DEBUG_RODATA_TEST) += test_rodata.o
obj-$(CONFIG_DEBUG_NX_TEST) += test_nx.o

2
arch/x86/kernel/k8.c → arch/x86/kernel/amd_nb.c
View File

@ -8,7 +8,7 @@
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <asm/k8.h>
#include <asm/amd_nb.h>
static u32 *flush_words;

2
arch/x86/kernel/aperture_64.c
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@ -27,7 +27,7 @@
#include <asm/gart.h>
#include <asm/pci-direct.h>
#include <asm/dma.h>
#include <asm/k8.h>
#include <asm/amd_nb.h>
#include <asm/x86_init.h>
int gart_iommu_aperture;

10
arch/x86/kernel/cpu/intel_cacheinfo.c
View File

@ -17,7 +17,7 @@
#include <asm/processor.h>
#include <linux/smp.h>
#include <asm/k8.h>
#include <asm/amd_nb.h>
#include <asm/smp.h>
#define LVL_1_INST 1
@ -306,7 +306,7 @@ struct _cache_attr {
ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
};
#ifdef CONFIG_K8_NB
#ifdef CONFIG_AMD_NB
/*
* L3 cache descriptors
@ -556,12 +556,12 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
show_cache_disable_1, store_cache_disable_1);
#else /* CONFIG_K8_NB */
#else /* CONFIG_AMD_NB */
static void __cpuinit
amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, int index)
{
};
#endif /* CONFIG_K8_NB */
#endif /* CONFIG_AMD_NB */
static int
__cpuinit cpuid4_cache_lookup_regs(int index,
@ -1000,7 +1000,7 @@ static struct attribute *default_attrs[] = {
static struct attribute *default_l3_attrs[] = {
DEFAULT_SYSFS_CACHE_ATTRS,
#ifdef CONFIG_K8_NB
#ifdef CONFIG_AMD_NB
&cache_disable_0.attr,
&cache_disable_1.attr,
#endif

2
arch/x86/kernel/pci-gart_64.c
View File

@ -39,7 +39,7 @@
#include <asm/cacheflush.h>
#include <asm/swiotlb.h>
#include <asm/dma.h>
#include <asm/k8.h>
#include <asm/amd_nb.h>
#include <asm/x86_init.h>
static unsigned long iommu_bus_base; /* GART remapping area (physical) */

2
arch/x86/kernel/setup.c
View File

@ -107,7 +107,7 @@
#include <asm/percpu.h>
#include <asm/topology.h>
#include <asm/apicdef.h>
#include <asm/k8.h>
#include <asm/amd_nb.h>
#ifdef CONFIG_X86_64
#include <asm/numa_64.h>
#endif

2
arch/x86/mm/k8topology_64.c
View File

@ -22,7 +22,7 @@
#include <asm/numa.h>
#include <asm/mpspec.h>
#include <asm/apic.h>
#include <asm/k8.h>
#include <asm/amd_nb.h>
static struct bootnode __initdata nodes[8];
static nodemask_t __initdata nodes_parsed = NODE_MASK_NONE;

2
arch/x86/mm/numa_64.c
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@ -18,7 +18,7 @@
#include <asm/dma.h>
#include <asm/numa.h>
#include <asm/acpi.h>
#include <asm/k8.h>
#include <asm/amd_nb.h>
struct pglist_data *node_data[MAX_NUMNODES] __read_mostly;
EXPORT_SYMBOL(node_data);

2
drivers/char/agp/Kconfig
View File

@ -57,7 +57,7 @@ config AGP_AMD
config AGP_AMD64
tristate "AMD Opteron/Athlon64 on-CPU GART support"
depends on AGP && X86 && K8_NB
depends on AGP && X86 && AMD_NB
help
This option gives you AGP support for the GLX component of
X using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs.

2
drivers/char/agp/amd64-agp.c
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@ -15,7 +15,7 @@
#include <linux/mmzone.h>
#include <asm/page.h> /* PAGE_SIZE */
#include <asm/e820.h>
#include <asm/k8.h>
#include <asm/amd_nb.h>
#include <asm/gart.h>
#include "agp.h"

2
drivers/edac/Kconfig
View File

@ -66,7 +66,7 @@ config EDAC_MCE
config EDAC_AMD64
tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
depends on EDAC_MM_EDAC && AMD_NB && X86_64 && PCI && EDAC_DECODE_MCE
help
Support for error detection and correction on the AMD 64
Families of Memory Controllers (K8, F10h and F11h)

2
drivers/edac/amd64_edac.c
View File

@ -1,5 +1,5 @@
#include "amd64_edac.h"
#include <asm/k8.h>
#include <asm/amd_nb.h>
static struct edac_pci_ctl_info *amd64_ctl_pci;