intel-gtt: store the dma mask size in intel_gtt_driver
Storing this explicitly makes for clearer code and hopefully less further confusion. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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0af9e92e77
commit
22533b494f
1 changed files with 11 additions and 7 deletions
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@ -73,6 +73,7 @@ struct intel_gtt_driver {
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unsigned int is_g33 : 1;
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unsigned int is_pineview : 1;
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unsigned int is_ironlake : 1;
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unsigned int dma_mask_size : 8;
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/* Chipset specific GTT setup */
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int (*setup)(void);
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void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
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@ -1309,11 +1310,13 @@ static const struct agp_bridge_driver intel_fake_agp_driver = {
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static const struct intel_gtt_driver i81x_gtt_driver = {
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.gen = 1,
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.dma_mask_size = 32,
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};
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static const struct intel_gtt_driver i8xx_gtt_driver = {
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.gen = 2,
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.setup = i830_setup,
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.write_entry = i830_write_entry,
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.dma_mask_size = 32,
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.check_flags = i830_check_flags,
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.chipset_flush = i830_chipset_flush,
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};
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@ -1322,6 +1325,7 @@ static const struct intel_gtt_driver i915_gtt_driver = {
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.setup = i9xx_setup,
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/* i945 is the last gpu to need phys mem (for overlay and cursors). */
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.write_entry = i830_write_entry,
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.dma_mask_size = 32,
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
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};
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@ -1330,6 +1334,7 @@ static const struct intel_gtt_driver g33_gtt_driver = {
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.is_g33 = 1,
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.setup = i9xx_setup,
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.write_entry = i965_write_entry,
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.dma_mask_size = 36,
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
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};
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@ -1338,6 +1343,7 @@ static const struct intel_gtt_driver pineview_gtt_driver = {
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.is_pineview = 1, .is_g33 = 1,
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.setup = i9xx_setup,
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.write_entry = i965_write_entry,
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.dma_mask_size = 36,
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
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};
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@ -1345,6 +1351,7 @@ static const struct intel_gtt_driver i965_gtt_driver = {
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.gen = 4,
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.setup = i9xx_setup,
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.write_entry = i965_write_entry,
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.dma_mask_size = 36,
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
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};
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@ -1352,6 +1359,7 @@ static const struct intel_gtt_driver g4x_gtt_driver = {
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.gen = 5,
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.setup = i9xx_setup,
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.write_entry = i965_write_entry,
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.dma_mask_size = 36,
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
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};
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@ -1360,6 +1368,7 @@ static const struct intel_gtt_driver ironlake_gtt_driver = {
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.is_ironlake = 1,
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.setup = i9xx_setup,
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.write_entry = i965_write_entry,
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.dma_mask_size = 36,
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
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};
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@ -1367,6 +1376,7 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
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.gen = 6,
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.setup = i9xx_setup,
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.write_entry = gen6_write_entry,
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.dma_mask_size = 40,
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.check_flags = gen6_check_flags,
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.chipset_flush = i9xx_chipset_flush,
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};
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@ -1511,13 +1521,7 @@ int intel_gmch_probe(struct pci_dev *pdev,
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dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
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if (intel_private.driver->write_entry == gen6_write_entry)
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mask = 40;
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else if (intel_private.driver->write_entry == i965_write_entry)
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mask = 36;
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else
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mask = 32;
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mask = intel_private.driver->dma_mask_size;
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if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
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dev_err(&intel_private.pcidev->dev,
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"set gfx device dma mask %d-bit failed!\n", mask);
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