[PATCH] x86: VIA C7 CPU flags
New CPU flags for next generation of crypto engine as found in VIA C7 processors. Signed-off-by: Michal Ludvig <michal@logix.cz> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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2 changed files with 13 additions and 1 deletions
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@ -52,7 +52,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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/* VIA/Cyrix/Centaur-defined */
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NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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"ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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@ -88,6 +88,12 @@
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#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */
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#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
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#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
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#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
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#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
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#define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */
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#define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */
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#define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery Multiplier */
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#define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */
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/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
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#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
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@ -121,6 +127,12 @@
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#define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN)
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#define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT)
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#define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN)
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#define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2)
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#define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN)
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#define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE)
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#define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN)
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#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
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#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
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#endif /* __ASM_I386_CPUFEATURE_H */
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