drm/radeon: add hier-z registers for r300 and r500 chipsets
This commit is contained in:
Dave Airlie
parent
5e35eff13f
commit
21efa2bac9
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@ -190,7 +190,7 @@ void r300_init_reg_flags(struct drm_device *dev)
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ADD_RANGE(0x42C0, 2);
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ADD_RANGE(R300_RS_CNTL_0, 2);
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ADD_RANGE(0x43A4, 2);
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ADD_RANGE(R300_SC_HYPERZ, 2);
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ADD_RANGE(0x43E8, 1);
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ADD_RANGE(0x46A4, 5);
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@ -209,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
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ADD_RANGE(0x4E50, 9);
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ADD_RANGE(0x4E88, 1);
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ADD_RANGE(0x4EA0, 2);
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ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
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ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
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ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
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ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
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ADD_RANGE(0x4F28, 1);
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ADD_RANGE(0x4F30, 2);
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ADD_RANGE(0x4F44, 1);
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ADD_RANGE(0x4F54, 1);
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ADD_RANGE(R300_ZB_CNTL, 3);
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ADD_RANGE(R300_ZB_FORMAT, 4);
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ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
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ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
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ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
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ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
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ADD_RANGE(R300_TX_FILTER_0, 16);
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ADD_RANGE(R300_TX_FILTER1_0, 16);
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@ -229,7 +227,7 @@ void r300_init_reg_flags(struct drm_device *dev)
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ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
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/* Sporadic registers used as primitives are emitted */
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ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
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ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
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ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
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ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
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ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
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@ -243,6 +241,7 @@ void r300_init_reg_flags(struct drm_device *dev)
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ADD_RANGE(R500_RS_INST_0, 16);
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ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
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ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
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ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
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} else {
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ADD_RANGE(R300_PFS_CNTL_0, 3);
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ADD_RANGE(R300_PFS_NODE_0, 4);
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@ -719,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
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BEGIN_RING(6);
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OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
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OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
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OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
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OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
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OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
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OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
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R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
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OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
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OUT_RING(0x0);
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ADVANCE_RING();
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@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
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/* END: Rasterization / Interpolators - many guesses */
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/* Hierarchical Z Enable */
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#define R300_SC_HYPERZ 0x43a4
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# define R300_SC_HYPERZ_DISABLE (0 << 0)
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# define R300_SC_HYPERZ_ENABLE (1 << 0)
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# define R300_SC_HYPERZ_MIN (0 << 1)
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# define R300_SC_HYPERZ_MAX (1 << 1)
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# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
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# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
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# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
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# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
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# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
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# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
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# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
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# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
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# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
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# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
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# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
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# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
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#define R300_SC_EDGERULE 0x43a8
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/* BEGIN: Scissors and cliprects */
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/* There are four clipping rectangles. Their corner coordinates are inclusive.
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@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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* for this.
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* Bit (1<<8) is the "test" bit. so plain write is 6 - vd
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*/
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#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00
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# define R300_RB3D_Z_DISABLED_1 0x00000010
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# define R300_RB3D_Z_DISABLED_2 0x00000014
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# define R300_RB3D_Z_TEST 0x00000012
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# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
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# define R300_RB3D_Z_WRITE_ONLY 0x00000006
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#define R300_ZB_CNTL 0x4F00
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# define R300_STENCIL_ENABLE (1 << 0)
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# define R300_Z_ENABLE (1 << 1)
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# define R300_Z_WRITE_ENABLE (1 << 2)
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# define R300_Z_SIGNED_COMPARE (1 << 3)
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# define R300_STENCIL_FRONT_BACK (1 << 4)
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# define R300_RB3D_Z_TEST 0x00000012
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# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
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# define R300_RB3D_Z_WRITE_ONLY 0x00000006
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# define R300_RB3D_STENCIL_ENABLE 0x00000001
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#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
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#define R300_ZB_ZSTENCILCNTL 0x4f04
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/* functions */
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# define R300_ZS_NEVER 0
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# define R300_ZS_LESS 1
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@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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# define R300_ZS_INVERT 5
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# define R300_ZS_INCR_WRAP 6
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# define R300_ZS_DECR_WRAP 7
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# define R300_Z_FUNC_SHIFT 0
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/* front and back refer to operations done for front
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and back faces, i.e. separate stencil function support */
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# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0
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# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3
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# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6
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# define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9
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# define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12
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# define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15
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# define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18
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# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21
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# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24
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# define R300_S_FRONT_FUNC_SHIFT 3
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# define R300_S_FRONT_SFAIL_OP_SHIFT 6
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# define R300_S_FRONT_ZPASS_OP_SHIFT 9
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# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
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# define R300_S_BACK_FUNC_SHIFT 15
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# define R300_S_BACK_SFAIL_OP_SHIFT 18
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# define R300_S_BACK_ZPASS_OP_SHIFT 21
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# define R300_S_BACK_ZFAIL_OP_SHIFT 24
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#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08
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# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0
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# define R300_RB3D_ZS2_STENCIL_MASK 0xFF
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# define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8
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# define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16
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#define R300_ZB_STENCILREFMASK 0x4f08
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# define R300_STENCILREF_SHIFT 0
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# define R300_STENCILREF_MASK 0x000000ff
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# define R300_STENCILMASK_SHIFT 8
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# define R300_STENCILMASK_MASK 0x0000ff00
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# define R300_STENCILWRITEMASK_SHIFT 16
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# define R300_STENCILWRITEMASK_MASK 0x00ff0000
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/* gap */
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#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10
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# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
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# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
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/* 16 bit format or some aditional bit ? */
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# define R300_DEPTH_FORMAT_UNK32 (32 << 0)
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#define R300_ZB_FORMAT 0x4f10
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# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
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# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
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# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
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/* reserved up to (15 << 0) */
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# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
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# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
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#define R300_RB3D_EARLY_Z 0x4F14
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# define R300_EARLY_Z_DISABLE (0 << 0)
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# define R300_EARLY_Z_ENABLE (1 << 0)
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#define R300_ZB_ZTOP 0x4F14
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# define R300_ZTOP_DISABLE (0 << 0)
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# define R300_ZTOP_ENABLE (1 << 0)
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/* gap */
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#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */
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# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1
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# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3
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#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
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# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
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# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
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# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
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# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
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# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
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# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
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#define R300_ZB_BW_CNTL 0x4f1c
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# define R300_HIZ_DISABLE (0 << 0)
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# define R300_HIZ_ENABLE (1 << 0)
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# define R300_HIZ_MIN (0 << 1)
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# define R300_HIZ_MAX (1 << 1)
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# define R300_FAST_FILL_DISABLE (0 << 2)
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# define R300_FAST_FILL_ENABLE (1 << 2)
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# define R300_RD_COMP_DISABLE (0 << 3)
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# define R300_RD_COMP_ENABLE (1 << 3)
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# define R300_WR_COMP_DISABLE (0 << 4)
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# define R300_WR_COMP_ENABLE (1 << 4)
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# define R300_ZB_CB_CLEAR_RMW (0 << 5)
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# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
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# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
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# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
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# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
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# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
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# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
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# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
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# define R500_BMASK_ENABLE (0 << 10)
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# define R500_BMASK_DISABLE (1 << 10)
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# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
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# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
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# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
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# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
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# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
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# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
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# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
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# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
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# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
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# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
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# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
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# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
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# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
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# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
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# define R500_PEQ_PACKING_DISABLE (0 << 18)
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# define R500_PEQ_PACKING_ENABLE (1 << 18)
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# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
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# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
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/* gap */
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#define R300_RB3D_DEPTHOFFSET 0x4F20
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#define R300_RB3D_DEPTHPITCH 0x4F24
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# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */
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# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */
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# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */
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# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
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# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
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# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
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/* Z Buffer Address Offset.
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* Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
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*/
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#define R300_ZB_DEPTHOFFSET 0x4f20
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/* Z Buffer Pitch and Endian Control */
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#define R300_ZB_DEPTHPITCH 0x4f24
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# define R300_DEPTHPITCH_MASK 0x00003FFC
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# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
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# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
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# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
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# define R300_DEPTHMICROTILE_TILED (1 << 17)
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# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
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# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
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# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
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# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
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# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
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/* Z Buffer Clear Value */
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#define R300_ZB_DEPTHCLEARVALUE 0x4f28
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#define R300_ZB_ZMASK_OFFSET 0x4f30
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#define R300_ZB_ZMASK_PITCH 0x4f34
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#define R300_ZB_ZMASK_WRINDEX 0x4f38
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#define R300_ZB_ZMASK_DWORD 0x4f3c
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#define R300_ZB_ZMASK_RDINDEX 0x4f40
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/* Hierarchical Z Memory Offset */
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#define R300_ZB_HIZ_OFFSET 0x4f44
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/* Hierarchical Z Write Index */
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#define R300_ZB_HIZ_WRINDEX 0x4f48
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/* Hierarchical Z Data */
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#define R300_ZB_HIZ_DWORD 0x4f4c
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/* Hierarchical Z Read Index */
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#define R300_ZB_HIZ_RDINDEX 0x4f50
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/* Hierarchical Z Pitch */
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#define R300_ZB_HIZ_PITCH 0x4f54
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/* Z Buffer Z Pass Counter Data */
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#define R300_ZB_ZPASS_DATA 0x4f58
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/* Z Buffer Z Pass Counter Address */
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#define R300_ZB_ZPASS_ADDR 0x4f5c
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/* Depth buffer X and Y coordinate offset */
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#define R300_ZB_DEPTHXY_OFFSET 0x4f60
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# define R300_DEPTHX_OFFSET_SHIFT 1
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# define R300_DEPTHX_OFFSET_MASK 0x000007FE
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# define R300_DEPTHY_OFFSET_SHIFT 17
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# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
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/* Sets the fifo sizes */
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#define R500_ZB_FIFO_SIZE 0x4fd0
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# define R500_OP_FIFO_SIZE_FULL (0 << 0)
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# define R500_OP_FIFO_SIZE_HALF (1 << 0)
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# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
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# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
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/* Stencil Reference Value and Mask for backfacing quads */
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/* R300_ZB_STENCILREFMASK handles front face */
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#define R500_ZB_STENCILREFMASK_BF 0x4fd4
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# define R500_STENCILREF_SHIFT 0
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# define R500_STENCILREF_MASK 0x000000ff
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# define R500_STENCILMASK_SHIFT 8
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# define R500_STENCILMASK_MASK 0x0000ff00
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# define R500_STENCILWRITEMASK_SHIFT 16
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# define R500_STENCILWRITEMASK_MASK 0x00ff0000
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/* BEGIN: Vertex program instruction set */
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