ARM: arch-shmobile: Use multiple irq vectors for SDHI
This patch reverts "ARM: mach-shmobile: sh7372 SDHI vector merge" and supplies 3 IRQ resources for each SDHI block. Some blocks have a 4th IRQ, but this is used for DRM feathres that I do not have access tot he documentation for and are almost certainly tainted by licensing issues. So the 4th IRQ is not hooked-up even if it exists. Cc: Chris Ball <cjb@laptop.org> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Simon Horman <horms@verge.net.au> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
6b36fdd11b
commit
2007aea18c
3 changed files with 70 additions and 30 deletions
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@ -316,8 +316,16 @@ static struct resource sdhi0_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_MEM,
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},
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},
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[1] = {
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[1] = {
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.start = evt2irq(0x0e00) /* SDHI0 */,
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.start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
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.flags = IORESOURCE_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
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.flags = IORESOURCE_IRQ,
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},
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},
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};
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};
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@ -349,8 +357,16 @@ static struct resource sdhi1_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_MEM,
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},
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},
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[1] = {
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[1] = {
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.start = evt2irq(0x0e80),
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.start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
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.flags = IORESOURCE_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
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.flags = IORESOURCE_IRQ,
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},
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},
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};
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};
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@ -684,7 +684,15 @@ static struct resource sdhi0_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_MEM,
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},
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},
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[1] = {
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[1] = {
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.start = evt2irq(0x0e00) /* SDHI0 */,
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.start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
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.flags = IORESOURCE_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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},
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};
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};
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@ -719,7 +727,15 @@ static struct resource sdhi1_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_MEM,
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},
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},
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[1] = {
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[1] = {
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.start = evt2irq(0x0e80),
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.start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
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.flags = IORESOURCE_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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},
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};
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};
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@ -762,7 +778,15 @@ static struct resource sdhi2_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_MEM,
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},
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},
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[1] = {
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[1] = {
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.start = evt2irq(0x1200),
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.start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
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.flags = IORESOURCE_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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},
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};
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};
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@ -27,8 +27,6 @@
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enum {
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enum {
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UNUSED_INTCA = 0,
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UNUSED_INTCA = 0,
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ENABLED,
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DISABLED,
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/* interrupt sources INTCA */
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/* interrupt sources INTCA */
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IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
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IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
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@ -49,14 +47,14 @@ enum {
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MSIOF2, MSIOF1,
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MSIOF2, MSIOF1,
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SCIFA4, SCIFA5, SCIFB,
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SCIFA4, SCIFA5, SCIFB,
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FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
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FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
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SDHI0,
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SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
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SDHI1,
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SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
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IRREM,
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IRREM,
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IRDA,
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IRDA,
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TPU0,
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TPU0,
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TTI20,
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TTI20,
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DDM,
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DDM,
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SDHI2,
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SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
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RWDT0,
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RWDT0,
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DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
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DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
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DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
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DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
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@ -84,7 +82,7 @@ enum {
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/* interrupt groups INTCA */
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/* interrupt groups INTCA */
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DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
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DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
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AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1
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AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
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};
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};
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static struct intc_vect intca_vectors[] __initdata = {
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static struct intc_vect intca_vectors[] __initdata = {
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@ -125,17 +123,17 @@ static struct intc_vect intca_vectors[] __initdata = {
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INTC_VECT(SCIFB, 0x0d60),
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INTC_VECT(SCIFB, 0x0d60),
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INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
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INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
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INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
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INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
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INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
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INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
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INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
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INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
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INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
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INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
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INTC_VECT(SDHI1, 0x0ec0),
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INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
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INTC_VECT(IRREM, 0x0f60),
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INTC_VECT(IRREM, 0x0f60),
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INTC_VECT(IRDA, 0x0480),
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INTC_VECT(IRDA, 0x0480),
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INTC_VECT(TPU0, 0x04a0),
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INTC_VECT(TPU0, 0x04a0),
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INTC_VECT(TTI20, 0x1100),
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INTC_VECT(TTI20, 0x1100),
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INTC_VECT(DDM, 0x1140),
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INTC_VECT(DDM, 0x1140),
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INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
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INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
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INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
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INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
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INTC_VECT(RWDT0, 0x1280),
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INTC_VECT(RWDT0, 0x1280),
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INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
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INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
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INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
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INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
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@ -195,6 +193,12 @@ static struct intc_group intca_groups[] __initdata = {
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INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
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INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
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FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
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FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
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INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
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INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
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INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
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SDHI0_SDHI0I2, SDHI0_SDHI0I3),
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INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
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SDHI1_SDHI1I2),
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INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
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SDHI2_SDHI2I2, SDHI2_SDHI2I3),
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INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
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INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
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};
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};
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@ -230,10 +234,10 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
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{ SCIFB, SCIFA5, SCIFA4, MSIOF1,
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{ SCIFB, SCIFA5, SCIFA4, MSIOF1,
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0, 0, MSIOF2, 0 } },
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0, 0, MSIOF2, 0 } },
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{ 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
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{ 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
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{ DISABLED, ENABLED, ENABLED, ENABLED,
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{ SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
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FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
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FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
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{ 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
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{ 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
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{ 0, ENABLED, ENABLED, ENABLED,
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{ 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
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TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
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TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
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{ 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
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{ 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
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{ CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
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{ CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
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{ 0, 0, TPU0, 0,
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{ 0, 0, TPU0, 0,
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0, 0, 0, 0 } },
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0, 0, 0, 0 } },
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{ 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
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{ 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
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{ DISABLED, DISABLED, ENABLED, ENABLED,
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{ SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
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0, CMT3, 0, RWDT0 } },
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0, CMT3, 0, RWDT0 } },
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{ 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
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{ 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
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{ SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
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{ SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
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@ -354,14 +358,10 @@ static struct intc_mask_reg intca_ack_registers[] __initdata = {
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{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
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{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
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};
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};
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static struct intc_desc intca_desc __initdata = {
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static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
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.name = "sh7372-intca",
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intca_vectors, intca_groups,
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.force_enable = ENABLED,
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intca_mask_registers, intca_prio_registers,
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.force_disable = DISABLED,
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intca_sense_registers, intca_ack_registers);
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.hw = INTC_HW_DESC(intca_vectors, intca_groups,
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intca_mask_registers, intca_prio_registers,
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intca_sense_registers, intca_ack_registers),
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};
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enum {
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enum {
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UNUSED_INTCS = 0,
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UNUSED_INTCS = 0,
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