[ARM] 5469/1: Freescale STMP platform support [2/10]
Headers for STMP378x boards Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
dmitry pervushin
Russell King
parent
9bef5de1e0
commit
1e3dd535d6
3 changed files with 281 additions and 0 deletions
35
arch/arm/mach-stmp378x/include/mach/entry-macro.S
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35
arch/arm/mach-stmp378x/include/mach/entry-macro.S
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/*
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* Low-level IRQ helper macros for Freescale STMP378X
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*
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* Embedded Alley Solutions, Inc <source@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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.macro disable_fiq
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mov \base, #0xf0000000 @ vm address of IRQ controller
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ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT
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cmp \irqnr, #0x7f
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moveqs \irqnr, #0 @ Zero flag set for no IRQ
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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95
arch/arm/mach-stmp378x/include/mach/irqs.h
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arch/arm/mach-stmp378x/include/mach/irqs.h
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/*
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* Freescale STMP378X interrupts
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*
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* Copyright (C) 2005 Sigmatel Inc
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#define IRQ_DEBUG_UART 0
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#define IRQ_COMMS_RX 1
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#define IRQ_COMMS_TX 1
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#define IRQ_SSP2_ERROR 2
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#define IRQ_VDD5V 3
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#define IRQ_HEADPHONE_SHORT 4
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#define IRQ_DAC_DMA 5
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#define IRQ_DAC_ERROR 6
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#define IRQ_ADC_DMA 7
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#define IRQ_ADC_ERROR 8
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#define IRQ_SPDIF_DMA 9
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#define IRQ_SAIF2_DMA 9
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#define IRQ_SPDIF_ERROR 10
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#define IRQ_SAIF1_IRQ 10
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#define IRQ_SAIF2_IRQ 10
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#define IRQ_USB_CTRL 11
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#define IRQ_USB_WAKEUP 12
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#define IRQ_GPMI_DMA 13
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#define IRQ_SSP1_DMA 14
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#define IRQ_SSP_ERROR 15
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#define IRQ_GPIO0 16
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#define IRQ_GPIO1 17
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#define IRQ_GPIO2 18
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#define IRQ_SAIF1_DMA 19
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#define IRQ_SSP2_DMA 20
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#define IRQ_ECC8_IRQ 21
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#define IRQ_RTC_ALARM 22
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#define IRQ_UARTAPP_TX_DMA 23
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#define IRQ_UARTAPP_INTERNAL 24
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#define IRQ_UARTAPP_RX_DMA 25
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#define IRQ_I2C_DMA 26
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#define IRQ_I2C_ERROR 27
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#define IRQ_TIMER0 28
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#define IRQ_TIMER1 29
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#define IRQ_TIMER2 30
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#define IRQ_TIMER3 31
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#define IRQ_BATT_BRNOUT 32
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#define IRQ_VDDD_BRNOUT 33
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#define IRQ_VDDIO_BRNOUT 34
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#define IRQ_VDD18_BRNOUT 35
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#define IRQ_TOUCH_DETECT 36
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#define IRQ_LRADC_CH0 37
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#define IRQ_LRADC_CH1 38
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#define IRQ_LRADC_CH2 39
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#define IRQ_LRADC_CH3 40
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#define IRQ_LRADC_CH4 41
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#define IRQ_LRADC_CH5 42
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#define IRQ_LRADC_CH6 43
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#define IRQ_LRADC_CH7 44
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#define IRQ_LCDIF_DMA 45
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#define IRQ_LCDIF_ERROR 46
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#define IRQ_DIGCTL_DEBUG_TRAP 47
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#define IRQ_RTC_1MSEC 48
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#define IRQ_DRI_DMA 49
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#define IRQ_DRI_ATTENTION 50
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#define IRQ_GPMI_ATTENTION 51
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#define IRQ_IR 52
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#define IRQ_DCP_VMI 53
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#define IRQ_DCP 54
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#define IRQ_BCH 56
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#define IRQ_PXP 57
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#define IRQ_UARTAPP2_TX_DMA 58
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#define IRQ_UARTAPP2_INTERNAL 59
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#define IRQ_UARTAPP2_RX_DMA 60
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#define IRQ_VDAC_DETECT 61
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#define IRQ_VDD5V_DROOP 64
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#define IRQ_DCDC4P2_BO 65
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#define NR_REAL_IRQS 128
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#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
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/* All interrupts are FIQ capable */
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#define FIQ_START IRQ_DEBUG_UART
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/* Hard disk IRQ is a GPMI attention IRQ */
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#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
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151
arch/arm/mach-stmp378x/include/mach/pins.h
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arch/arm/mach-stmp378x/include/mach/pins.h
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/*
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* Freescale STMP378X SoC pin multiplexing
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*
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* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#ifndef __ASM_ARCH_PINS_H
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#define __ASM_ARCH_PINS_H
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/*
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* Define all STMP378x pins, a pin name corresponds to a STMP378x hardware
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* interface this pin belongs to.
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*/
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/* Bank 0 */
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#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
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#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
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#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
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#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
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#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
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#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
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#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
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#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
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#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
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#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
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#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
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#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
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#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
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#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
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#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
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#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
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#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16)
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#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17)
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#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18)
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#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
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#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20)
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#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21)
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#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22)
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#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23)
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#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
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#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
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#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26)
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#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27)
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#define PINID_AUART1_RX STMP3XXX_PINID(0, 28)
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#define PINID_AUART1_TX STMP3XXX_PINID(0, 29)
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#define PINID_I2C_SCL STMP3XXX_PINID(0, 30)
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#define PINID_I2C_SDA STMP3XXX_PINID(0, 31)
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/* Bank 1 */
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#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
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#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
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#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
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#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
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#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
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#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
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#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
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#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
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#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
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#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
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#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
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#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
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#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
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#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
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#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
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#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
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#define PINID_LCD_D16 STMP3XXX_PINID(1, 16)
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#define PINID_LCD_D17 STMP3XXX_PINID(1, 17)
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#define PINID_LCD_RESET STMP3XXX_PINID(1, 18)
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#define PINID_LCD_RS STMP3XXX_PINID(1, 19)
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#define PINID_LCD_WR STMP3XXX_PINID(1, 20)
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#define PINID_LCD_CS STMP3XXX_PINID(1, 21)
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#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22)
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#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23)
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#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24)
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#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25)
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#define PINID_PWM0 STMP3XXX_PINID(1, 26)
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#define PINID_PWM1 STMP3XXX_PINID(1, 27)
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#define PINID_PWM2 STMP3XXX_PINID(1, 28)
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#define PINID_PWM3 STMP3XXX_PINID(1, 29)
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#define PINID_PWM4 STMP3XXX_PINID(1, 30)
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/* Bank 2 */
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#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0)
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#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1)
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#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2)
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#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3)
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#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4)
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#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5)
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#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6)
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#define PINID_ROTARYA STMP3XXX_PINID(2, 7)
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#define PINID_ROTARYB STMP3XXX_PINID(2, 8)
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#define PINID_EMI_A00 STMP3XXX_PINID(2, 9)
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#define PINID_EMI_A01 STMP3XXX_PINID(2, 10)
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#define PINID_EMI_A02 STMP3XXX_PINID(2, 11)
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#define PINID_EMI_A03 STMP3XXX_PINID(2, 12)
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#define PINID_EMI_A04 STMP3XXX_PINID(2, 13)
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#define PINID_EMI_A05 STMP3XXX_PINID(2, 14)
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#define PINID_EMI_A06 STMP3XXX_PINID(2, 15)
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#define PINID_EMI_A07 STMP3XXX_PINID(2, 16)
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#define PINID_EMI_A08 STMP3XXX_PINID(2, 17)
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#define PINID_EMI_A09 STMP3XXX_PINID(2, 18)
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#define PINID_EMI_A10 STMP3XXX_PINID(2, 19)
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#define PINID_EMI_A11 STMP3XXX_PINID(2, 20)
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#define PINID_EMI_A12 STMP3XXX_PINID(2, 21)
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#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22)
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#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23)
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#define PINID_EMI_CASN STMP3XXX_PINID(2, 24)
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#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25)
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#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26)
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#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27)
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#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28)
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#define PINID_EMI_CKE STMP3XXX_PINID(2, 29)
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#define PINID_EMI_RASN STMP3XXX_PINID(2, 30)
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#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
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/* Bank 3 */
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#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
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#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
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#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
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#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
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#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
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#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
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#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
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#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
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#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
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#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
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#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
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#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
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#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
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#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
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#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
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#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
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#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16)
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#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17)
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#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18)
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#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19)
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#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
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#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
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#endif /* __ASM_ARCH_PINS_H */
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