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Blackfin arch: add TXDWA definition to enable new feature 

Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Bryan Wu 2008-07-15 12:08:50 +08:00
parent c71b478351
commit 1c0d20cd29
3 changed files with 4 additions and 0 deletions
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2
include/asm-blackfin/mach-bf527/anomaly.h
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@ -23,6 +23,8 @@
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* New Feature: EMAC TX DMA Word Alignment */
#define ANOMALY_05000285 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */

1
include/asm-blackfin/mach-bf527/defBF527.h
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@ -302,6 +302,7 @@
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */

1
include/asm-blackfin/mach-bf537/defBF537.h
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@ -290,6 +290,7 @@
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */