net/pch_gbe: supports eg20t ptp clock
Supports EG20T ptp clock in the driver Changes e-mail address. Adds number. Signed-off-by: Takahiro Shimizu <tshimizu818@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Takahiroi Shimizu
David S. Miller
parent
863d08ece9
commit
1a0bdadb4e
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@ -20,3 +20,16 @@ config PCH_GBE
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purpose use.
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ML7223/ML7831 is companion chip for Intel Atom E6xx series.
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ML7223/ML7831 is completely compatible for Intel EG20T PCH.
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if PCH_GBE
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config PCH_PTP
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bool "PCH PTP clock support"
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default n
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depends on PTP_1588_CLOCK_PCH
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---help---
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Say Y here if you want to use Precision Time Protocol (PTP) in the
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driver. PTP is a method to precisely synchronize distributed clocks
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over Ethernet networks.
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endif # PCH_GBE
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@ -630,6 +630,9 @@ struct pch_gbe_adapter {
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unsigned long tx_queue_len;
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bool have_msi;
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bool rx_stop_flag;
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int hwts_tx_en;
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int hwts_rx_en;
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struct pci_dev *ptp_pdev;
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};
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extern const char pch_driver_version[];
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@ -648,6 +651,16 @@ extern void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
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extern void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
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struct pch_gbe_rx_ring *rx_ring);
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extern void pch_gbe_update_stats(struct pch_gbe_adapter *adapter);
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#ifdef CONFIG_PCH_PTP
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extern u32 pch_ch_control_read(struct pci_dev *pdev);
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extern void pch_ch_control_write(struct pci_dev *pdev, u32 val);
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extern u32 pch_ch_event_read(struct pci_dev *pdev);
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extern void pch_ch_event_write(struct pci_dev *pdev, u32 val);
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extern u32 pch_src_uuid_lo_read(struct pci_dev *pdev);
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extern u32 pch_src_uuid_hi_read(struct pci_dev *pdev);
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extern u64 pch_rx_snap_read(struct pci_dev *pdev);
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extern u64 pch_tx_snap_read(struct pci_dev *pdev);
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#endif
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/* pch_gbe_param.c */
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extern void pch_gbe_check_options(struct pch_gbe_adapter *adapter);
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) 1999 - 2010 Intel Corporation.
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* Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
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* Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
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*
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* This code was derived from the Intel e1000e Linux driver.
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*
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@ -21,6 +21,10 @@
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#include "pch_gbe.h"
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#include "pch_gbe_api.h"
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#include <linux/module.h>
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#ifdef CONFIG_PCH_PTP
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#include <linux/net_tstamp.h>
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#include <linux/ptp_classify.h>
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#endif
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#define DRV_VERSION "1.00"
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const char pch_driver_version[] = DRV_VERSION;
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@ -95,12 +99,195 @@ const char pch_driver_version[] = DRV_VERSION;
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#define PCH_GBE_INT_DISABLE_ALL 0
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#ifdef CONFIG_PCH_PTP
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/* Macros for ieee1588 */
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#define TICKS_NS_SHIFT 5
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/* 0x40 Time Synchronization Channel Control Register Bits */
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#define MASTER_MODE (1<<0)
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#define SLAVE_MODE (0<<0)
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#define V2_MODE (1<<31)
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#define CAP_MODE0 (0<<16)
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#define CAP_MODE2 (1<<17)
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/* 0x44 Time Synchronization Channel Event Register Bits */
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#define TX_SNAPSHOT_LOCKED (1<<0)
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#define RX_SNAPSHOT_LOCKED (1<<1)
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#endif
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static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
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static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
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static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
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int data);
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#ifdef CONFIG_PCH_PTP
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static struct sock_filter ptp_filter[] = {
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PTP_FILTER
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};
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static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
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{
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u8 *data = skb->data;
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unsigned int offset;
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u16 *hi, *id;
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u32 lo;
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if ((sk_run_filter(skb, ptp_filter) != PTP_CLASS_V2_IPV4) &&
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(sk_run_filter(skb, ptp_filter) != PTP_CLASS_V1_IPV4)) {
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return 0;
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}
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offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
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if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
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return 0;
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hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
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id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
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memcpy(&lo, &hi[1], sizeof(lo));
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return (uid_hi == *hi &&
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uid_lo == lo &&
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seqid == *id);
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}
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static void pch_rx_timestamp(
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struct pch_gbe_adapter *adapter, struct sk_buff *skb)
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{
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struct skb_shared_hwtstamps *shhwtstamps;
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struct pci_dev *pdev;
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u64 ns;
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u32 hi, lo, val;
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u16 uid, seq;
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if (!adapter->hwts_rx_en)
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return;
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/* Get ieee1588's dev information */
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pdev = adapter->ptp_pdev;
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val = pch_ch_event_read(pdev);
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if (!(val & RX_SNAPSHOT_LOCKED))
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return;
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lo = pch_src_uuid_lo_read(pdev);
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hi = pch_src_uuid_hi_read(pdev);
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uid = hi & 0xffff;
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seq = (hi >> 16) & 0xffff;
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if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
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goto out;
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ns = pch_rx_snap_read(pdev);
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ns <<= TICKS_NS_SHIFT;
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shhwtstamps = skb_hwtstamps(skb);
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memset(shhwtstamps, 0, sizeof(*shhwtstamps));
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shhwtstamps->hwtstamp = ns_to_ktime(ns);
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out:
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pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
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}
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static void pch_tx_timestamp(
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struct pch_gbe_adapter *adapter, struct sk_buff *skb)
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{
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struct skb_shared_hwtstamps shhwtstamps;
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struct pci_dev *pdev;
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struct skb_shared_info *shtx;
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u64 ns;
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u32 cnt, val;
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shtx = skb_shinfo(skb);
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if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en))
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shtx->tx_flags |= SKBTX_IN_PROGRESS;
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else
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return;
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/* Get ieee1588's dev information */
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pdev = adapter->ptp_pdev;
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/*
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* This really stinks, but we have to poll for the Tx time stamp.
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* Usually, the time stamp is ready after 4 to 6 microseconds.
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*/
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for (cnt = 0; cnt < 100; cnt++) {
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val = pch_ch_event_read(pdev);
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if (val & TX_SNAPSHOT_LOCKED)
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break;
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udelay(1);
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}
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if (!(val & TX_SNAPSHOT_LOCKED)) {
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shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
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return;
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}
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ns = pch_tx_snap_read(pdev);
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ns <<= TICKS_NS_SHIFT;
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memset(&shhwtstamps, 0, sizeof(shhwtstamps));
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shhwtstamps.hwtstamp = ns_to_ktime(ns);
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skb_tstamp_tx(skb, &shhwtstamps);
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pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
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}
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static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
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{
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struct hwtstamp_config cfg;
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struct pch_gbe_adapter *adapter = netdev_priv(netdev);
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struct pci_dev *pdev;
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if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
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return -EFAULT;
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if (cfg.flags) /* reserved for future extensions */
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return -EINVAL;
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/* Get ieee1588's dev information */
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pdev = adapter->ptp_pdev;
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switch (cfg.tx_type) {
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case HWTSTAMP_TX_OFF:
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adapter->hwts_tx_en = 0;
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break;
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case HWTSTAMP_TX_ON:
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adapter->hwts_tx_en = 1;
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break;
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default:
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return -ERANGE;
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}
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switch (cfg.rx_filter) {
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case HWTSTAMP_FILTER_NONE:
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adapter->hwts_rx_en = 0;
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break;
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case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
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adapter->hwts_rx_en = 0;
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pch_ch_control_write(pdev, (SLAVE_MODE | CAP_MODE0));
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break;
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case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
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adapter->hwts_rx_en = 1;
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pch_ch_control_write(pdev, (MASTER_MODE | CAP_MODE0));
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break;
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case HWTSTAMP_FILTER_PTP_V2_EVENT:
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adapter->hwts_rx_en = 1;
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pch_ch_control_write(pdev, (V2_MODE | CAP_MODE2));
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break;
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default:
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return -ERANGE;
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}
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/* Clear out any old time stamps. */
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pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
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return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
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}
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#endif
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inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
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{
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iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
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@ -1072,6 +1259,11 @@ static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
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iowrite32(tx_ring->dma +
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(int)sizeof(struct pch_gbe_tx_desc) * ring_num,
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&hw->reg->TX_DSC_SW_P);
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#ifdef CONFIG_PCH_PTP
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pch_tx_timestamp(adapter, skb);
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#endif
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dev_kfree_skb_any(skb);
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}
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@ -1543,6 +1735,11 @@ pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
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adapter->stats.multicast++;
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/* Write meta date of skb */
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skb_put(skb, length);
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#ifdef CONFIG_PCH_PTP
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pch_rx_timestamp(adapter, skb);
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#endif
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skb->protocol = eth_type_trans(skb, netdev);
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if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
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skb->ip_summed = CHECKSUM_NONE;
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@ -2144,6 +2341,11 @@ static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
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pr_debug("cmd : 0x%04x\n", cmd);
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#ifdef CONFIG_PCH_PTP
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if (cmd == SIOCSHWTSTAMP)
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return hwtstamp_ioctl(netdev, ifr, cmd);
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#endif
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return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
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}
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@ -2435,6 +2637,15 @@ static int pch_gbe_probe(struct pci_dev *pdev,
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goto err_free_netdev;
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}
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#ifdef CONFIG_PCH_PTP
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adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
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PCI_DEVFN(12, 4));
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if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
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pr_err("Bad ptp filter\n");
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return -EINVAL;
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}
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#endif
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netdev->netdev_ops = &pch_gbe_netdev_ops;
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netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
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netif_napi_add(netdev, &adapter->napi,
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@ -2499,7 +2710,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
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netif_carrier_off(netdev);
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netif_stop_queue(netdev);
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dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
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dev_dbg(&pdev->dev, "PCH Network Connection\n");
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device_set_wakeup_enable(&pdev->dev, 1);
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return 0;
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@ -2600,7 +2811,7 @@ module_init(pch_gbe_init_module);
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module_exit(pch_gbe_exit_module);
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MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
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MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
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MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(DRV_VERSION);
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MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
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