Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (99 commits) drivers/virt: add missing linux/interrupt.h to fsl_hypervisor.c powerpc/85xx: fix mpic configuration in CAMP mode powerpc: Copy back TIF flags on return from softirq stack powerpc/64: Make server perfmon only built on ppc64 server devices powerpc/pseries: Fix hvc_vio.c build due to recent changes powerpc: Exporting boot_cpuid_phys powerpc: Add CFAR to oops output hvc_console: Add kdb support powerpc/pseries: Fix hvterm_raw_get_chars to accept < 16 chars, fixing xmon powerpc/irq: Quieten irq mapping printks powerpc: Enable lockup and hung task detectors in pseries and ppc64 defeconfigs powerpc: Add mpt2sas driver to pseries and ppc64 defconfig powerpc: Disable IRQs off tracer in ppc64 defconfig powerpc: Sync pseries and ppc64 defconfigs powerpc/pseries/hvconsole: Fix dropped console output hvc_console: Improve tty/console put_chars handling powerpc/kdump: Fix timeout in crash_kexec_wait_realmode powerpc/mm: Fix output of total_ram. powerpc/cpufreq: Add cpufreq driver for Momentum Maple boards powerpc: Correct annotations of pmu registration functions ... Fix up trivial Kconfig/Makefile conflicts in arch/powerpc, drivers, and drivers/cpufreq
This commit is contained in:
Linus Torvalds
commit
184475029a
|
|
@ -301,6 +301,7 @@ Code Seq#(hex) Include File Comments
|
|||
<mailto:rusty@rustcorp.com.au>
|
||||
0xAE all linux/kvm.h Kernel-based Virtual Machine
|
||||
<mailto:kvm@vger.kernel.org>
|
||||
0xAF 00-1F linux/fsl_hypervisor.h Freescale hypervisor
|
||||
0xB0 all RATIO devices in development:
|
||||
<mailto:vgo@ratio.de>
|
||||
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
|
||||
|
|
|
|||
|
|
@ -2526,6 +2526,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
<port#>,<js1>,<js2>,<js3>,<js4>,<js5>,<js6>,<js7>
|
||||
See also Documentation/input/joystick-parport.txt
|
||||
|
||||
udbg-immortal [PPC] When debugging early kernel crashes that
|
||||
happen after console_init() and before a proper
|
||||
console driver takes over, this boot options might
|
||||
help "seeing" what's going on.
|
||||
|
||||
uhash_entries= [KNL,NET]
|
||||
Set number of hash buckets for UDP/UDP-Lite connections
|
||||
|
||||
|
|
|
|||
|
|
@ -3895,7 +3895,7 @@ F: arch/powerpc/platforms/512x/
|
|||
F: arch/powerpc/platforms/52xx/
|
||||
|
||||
LINUX FOR POWERPC EMBEDDED PPC4XX
|
||||
M: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
M: Josh Boyer <jwboyer@gmail.com>
|
||||
M: Matt Porter <mporter@kernel.crashing.org>
|
||||
W: http://www.penguinppc.org/
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
|
|
@ -3927,6 +3927,7 @@ W: http://www.penguinppc.org/
|
|||
L: linuxppc-dev@lists.ozlabs.org
|
||||
S: Maintained
|
||||
F: arch/powerpc/platforms/83xx/
|
||||
F: arch/powerpc/platforms/85xx/
|
||||
|
||||
LINUX FOR POWERPC PA SEMI PWRFICIENT
|
||||
M: Olof Johansson <olof@lixom.net>
|
||||
|
|
|
|||
|
|
@ -135,6 +135,7 @@ config PPC
|
|||
select HAVE_RCU_TABLE_FREE if SMP
|
||||
select HAVE_SYSCALL_TRACEPOINTS
|
||||
select HAVE_BPF_JIT if (PPC64 && NET)
|
||||
select HAVE_ARCH_JUMP_LABEL
|
||||
|
||||
config EARLY_PRINTK
|
||||
bool
|
||||
|
|
@ -842,7 +843,7 @@ config LOWMEM_CAM_NUM
|
|||
|
||||
config RELOCATABLE
|
||||
bool "Build a relocatable kernel (EXPERIMENTAL)"
|
||||
depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE
|
||||
depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || PPC_47x)
|
||||
help
|
||||
This builds a kernel image that is capable of running at the
|
||||
location the kernel is loaded at (some alignment restrictions may
|
||||
|
|
|
|||
|
|
@ -167,6 +167,13 @@ config PPC_EARLY_DEBUG_LPAR
|
|||
Select this to enable early debugging for a machine with a HVC
|
||||
console on vterm 0.
|
||||
|
||||
config PPC_EARLY_DEBUG_LPAR_HVSI
|
||||
bool "LPAR HVSI Console"
|
||||
depends on PPC_PSERIES
|
||||
help
|
||||
Select this to enable early debugging for a machine with a HVSI
|
||||
console on a specified vterm.
|
||||
|
||||
config PPC_EARLY_DEBUG_G5
|
||||
bool "Apple G5"
|
||||
depends on PPC_PMAC64
|
||||
|
|
@ -253,6 +260,14 @@ config PPC_EARLY_DEBUG_WSP
|
|||
|
||||
endchoice
|
||||
|
||||
config PPC_EARLY_DEBUG_HVSI_VTERMNO
|
||||
hex "vterm number to use with early debug HVSI"
|
||||
depends on PPC_EARLY_DEBUG_LPAR_HVSI
|
||||
default "0x30000000"
|
||||
help
|
||||
You probably want 0x30000000 for your first serial port and
|
||||
0x30000001 for your second one
|
||||
|
||||
config PPC_EARLY_DEBUG_44x_PHYSLOW
|
||||
hex "Low 32 bits of early debug UART physical address"
|
||||
depends on PPC_EARLY_DEBUG_44x
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ LDFLAGS_vmlinux-yy := -Bstatic
|
|||
LDFLAGS_vmlinux-$(CONFIG_PPC64)$(CONFIG_RELOCATABLE) := -pie
|
||||
LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-yy)
|
||||
|
||||
CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=none -mcall-aixdesc
|
||||
CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=no -mcall-aixdesc
|
||||
CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 -mmultiple
|
||||
KBUILD_CPPFLAGS += -Iarch/$(ARCH)
|
||||
KBUILD_AFLAGS += -Iarch/$(ARCH)
|
||||
|
|
|
|||
|
|
@ -143,6 +143,11 @@
|
|||
interrupts = <0x1d 0x4>;
|
||||
};
|
||||
|
||||
HWRNG: hwrng@110000 {
|
||||
compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
|
||||
reg = <4 0x00110000 0x50>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
|
|
|
|||
|
|
@ -130,12 +130,18 @@
|
|||
};
|
||||
|
||||
CRYPTO: crypto@180000 {
|
||||
compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
|
||||
compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto",
|
||||
"amcc,ppc4xx-crypto";
|
||||
reg = <4 0x00180000 0x80400>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1d 0x4>;
|
||||
};
|
||||
|
||||
HWRNG: hwrng@110000 {
|
||||
compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
|
||||
reg = <4 0x00110000 0x50>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
|
|
|
|||
|
|
@ -60,6 +60,8 @@
|
|||
compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
|
||||
"simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <19 2>;
|
||||
|
||||
ranges = <0x0 0x0 0xfe000000 0x02000000
|
||||
0x1 0x0 0xf8000000 0x00008000
|
||||
|
|
|
|||
|
|
@ -0,0 +1,280 @@
|
|||
/*
|
||||
* P1010 RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "p1010si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P1010RDB";
|
||||
compatible = "fsl,P1010RDB";
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
ifc@ffe1e000 {
|
||||
/* NOR, NAND Flashes and CPLD on board */
|
||||
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
|
||||
0x1 0x0 0x0 0xff800000 0x00010000
|
||||
0x3 0x0 0x0 0xffb00000 0x00000020>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x2000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
partition@40000 {
|
||||
/* 256KB for DTB Image */
|
||||
reg = <0x00040000 0x00040000>;
|
||||
label = "NOR DTB Image";
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
/* 7 MB for Linux Kernel Image */
|
||||
reg = <0x00080000 0x00700000>;
|
||||
label = "NOR Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
/* 20MB for JFFS2 based Root file System */
|
||||
reg = <0x00800000 0x01400000>;
|
||||
label = "NOR JFFS2 Root File System";
|
||||
};
|
||||
|
||||
partition@1f00000 {
|
||||
/* This location must not be altered */
|
||||
/* 512KB for u-boot Bootloader Image */
|
||||
/* 512KB for u-boot Environment Variables */
|
||||
reg = <0x01f00000 0x00100000>;
|
||||
label = "NOR U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x1 0x0 0x10000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00100000 0x00100000>;
|
||||
label = "NAND DTB Image";
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
/* 4MB for Linux Kernel Image */
|
||||
reg = <0x00200000 0x00400000>;
|
||||
label = "NAND Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@600000 {
|
||||
/* 4MB for Compressed Root file System Image */
|
||||
reg = <0x00600000 0x00400000>;
|
||||
label = "NAND Compressed RFS Image";
|
||||
};
|
||||
|
||||
partition@a00000 {
|
||||
/* 15MB for JFFS2 based Root file System */
|
||||
reg = <0x00a00000 0x00f00000>;
|
||||
label = "NAND JFFS2 Root File System";
|
||||
};
|
||||
|
||||
partition@1900000 {
|
||||
/* 7MB for User Area */
|
||||
reg = <0x01900000 0x00700000>;
|
||||
label = "NAND User area";
|
||||
};
|
||||
};
|
||||
|
||||
cpld@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1010rdb-cpld";
|
||||
reg = <0x3 0x0 0x0000020>;
|
||||
bank-width = <1>;
|
||||
device-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
spi@7000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
partition@0 {
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
/* 1MB for Environment */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "SPI Flash U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 512KB for DTB Image */
|
||||
reg = <0x00100000 0x00080000>;
|
||||
label = "SPI Flash DTB Image";
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
/* 4MB for Linux Kernel Image */
|
||||
reg = <0x00180000 0x00400000>;
|
||||
label = "SPI Flash Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
/* 4MB for Compressed RFS Image */
|
||||
reg = <0x00580000 0x00400000>;
|
||||
label = "SPI Flash Compressed RFSImage";
|
||||
};
|
||||
|
||||
partition@980000 {
|
||||
/* 6.5MB for JFFS2 based RFS */
|
||||
reg = <0x00980000 0x00680000>;
|
||||
label = "SPI Flash JFFS2 RFS";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
can0@1c000 {
|
||||
fsl,flexcan-clock-source = "platform";
|
||||
};
|
||||
|
||||
can1@1d000 {
|
||||
fsl,flexcan-clock-source = "platform";
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <2 1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <2 1>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
phy-handle = <&phy1>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
enet2: ethernet@b2000 {
|
||||
phy-handle = <&phy2>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
|
||||
ranges = <0x2000000 0x0 0xa0000000
|
||||
0x2000000 0x0 0xa0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe0a000 {
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,376 @@
|
|||
/*
|
||||
* P1010si Device Tree Source
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
compatible = "fsl,P1010";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P1010@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
ifc@ffe1e000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
reg = <0x0 0xffe1e000 0 0x2000>;
|
||||
interrupts = <16 2 19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1010-immr", "simple-bus";
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1010-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1010-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc8536-espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,espi-num-chipselects = <1>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,pq-sata-v2";
|
||||
reg = <0x18000 0x1000>;
|
||||
cell-index = <1>;
|
||||
interrupts = <74 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,pq-sata-v2";
|
||||
reg = <0x19000 0x1000>;
|
||||
cell-index = <2>;
|
||||
interrupts = <41 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
can0@1c000 {
|
||||
compatible = "fsl,flexcan-v1.0";
|
||||
reg = <0x1c000 0x1000>;
|
||||
interrupts = <48 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,flexcan-clock-divider = <2>;
|
||||
};
|
||||
|
||||
can1@1d000 {
|
||||
compatible = "fsl,flexcan-v1.0";
|
||||
reg = <0x1d000 0x1000>;
|
||||
interrupts = <61 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,flexcan-clock-divider = <2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1010-l2-cache-controller",
|
||||
"fsl,p1014-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1010-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-mdio";
|
||||
reg = <0x24000 0x1000 0xb0030 0x4>;
|
||||
};
|
||||
|
||||
mdio@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-tbi";
|
||||
reg = <0x25000 0x1000 0xb1030 0x4>;
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
mdio@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-tbi";
|
||||
reg = <0x26000 0x1000 0xb1030 0x4>;
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x8>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
fsl,sdhci-auto-cmd12;
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb0000 0x1000>;
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb1000 0x1000>;
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
enet2: ethernet@b2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb2000 0x1000>;
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,p1010-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,p1010-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe09000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
pci1: pcie@ffe0a000 {
|
||||
compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xffe0a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -412,7 +412,6 @@
|
|||
fsl,magic-packet;
|
||||
fsl,wake-on-filer;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
queue-group@0{
|
||||
|
|
@ -439,7 +438,6 @@
|
|||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
queue-group@0{
|
||||
|
|
|
|||
|
|
@ -0,0 +1,546 @@
|
|||
/*
|
||||
* P1023 RDS Device Tree Source
|
||||
*
|
||||
* Copyright 2010-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Author: Roy Zang <tie-fei.zang@freescale.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "fsl,P1023";
|
||||
compatible = "fsl,P1023RDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,P1023@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu1: PowerPC,P1023@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
soc@ff600000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1023-immr", "simple-bus";
|
||||
ranges = <0x0 0x0 0xff600000 0x200000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1023-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1023-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,p1023-espi", "fsl,mpc8536-espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
|
||||
fsl_dataflash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at45db081d";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
partition@u-boot {
|
||||
/* 512KB for u-boot Bootloader Image */
|
||||
label = "u-boot-spi";
|
||||
reg = <0x00000000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
partition@dtb {
|
||||
/* 512KB for DTB Image */
|
||||
label = "dtb-spi";
|
||||
reg = <0x00080000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1023-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 0x2>;
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30000 0x10000>;
|
||||
ranges = <0 0x30000 0x10000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <58 2>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <45 2>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <45 2>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <57 2>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupts = <57 2>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.2-rtic",
|
||||
"fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
power@e0070{
|
||||
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
|
||||
"fsl,p1022-pmc";
|
||||
reg = <0xe0070 0x20>;
|
||||
etsec1_clk: soc-clk@B0{
|
||||
fsl,pmcdr-mask = <0x00000080>;
|
||||
};
|
||||
etsec2_clk: soc-clk@B1{
|
||||
fsl,pmcdr-mask = <0x00000040>;
|
||||
};
|
||||
etsec3_clk: soc-clk@B2{
|
||||
fsl,pmcdr-mask = <0x00000020>;
|
||||
};
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,p1023-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,p1023-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ff605000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xff605000 0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
/* NOR Flash, BCSR */
|
||||
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
|
||||
0x1 0x0 0x0 0xe0000000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x02000000>;
|
||||
bank-width = <1>;
|
||||
device-width = <1>;
|
||||
partition@0 {
|
||||
label = "ramdisk";
|
||||
reg = <0x00000000 0x01c00000>;
|
||||
};
|
||||
partition@1c00000 {
|
||||
label = "kernel";
|
||||
reg = <0x01c00000 0x002e0000>;
|
||||
};
|
||||
partiton@1ee0000 {
|
||||
label = "dtb";
|
||||
reg = <0x01ee0000 0x00020000>;
|
||||
};
|
||||
partition@1f00000 {
|
||||
label = "firmware";
|
||||
reg = <0x01f00000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
partition@1f80000 {
|
||||
label = "u-boot";
|
||||
reg = <0x01f80000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
fpga@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1023rds-fpga";
|
||||
reg = <1 0 0x8000>;
|
||||
ranges = <0 1 0 0x8000>;
|
||||
|
||||
bcsr@20 {
|
||||
compatible = "fsl,p1023rds-bcsr";
|
||||
reg = <0x20 0x20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ff60a000 {
|
||||
compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
cell-index = <1>;
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xff60a000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 0 1
|
||||
0000 0 0 2 &mpic 1 1
|
||||
0000 0 0 3 &mpic 2 1
|
||||
0000 0 0 4 &mpic 3 1
|
||||
>;
|
||||
ranges = <0x2000000 0x0 0xc0000000
|
||||
0x2000000 0x0 0xc0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ff609000 {
|
||||
compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
cell-index = <2>;
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xff609000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 4 1
|
||||
0000 0 0 2 &mpic 5 1
|
||||
0000 0 0 3 &mpic 6 1
|
||||
0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
ranges = <0x2000000 0x0 0xa0000000
|
||||
0x2000000 0x0 0xa0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ff60b000 {
|
||||
cell-index = <3>;
|
||||
compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0 0xff60b000 0 0x1000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 8 1
|
||||
0000 0 0 2 &mpic 9 1
|
||||
0000 0 0 3 &mpic 10 1
|
||||
0000 0 0 4 &mpic 11 1
|
||||
>;
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* P2040RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "p2040si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P2040RDB";
|
||||
compatible = "fsl,P2040RDB";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
partition@u-boot {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@kernel {
|
||||
label = "kernel";
|
||||
reg = <0x00100000 0x00500000>;
|
||||
read-only;
|
||||
};
|
||||
partition@dtb {
|
||||
label = "dtb";
|
||||
reg = <0x00600000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@fs {
|
||||
label = "file system";
|
||||
reg = <0x00700000 0x00900000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
lm75b@48 {
|
||||
compatible = "nxp,lm75a";
|
||||
reg = <0x48>;
|
||||
};
|
||||
eeprom@50 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x50>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "pericom,pt7c4338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118100 {
|
||||
eeprom@50 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: usb@210000 {
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
usb1: usb@211000 {
|
||||
dr_mode = "host";
|
||||
phy_type = "utmi";
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x1000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x08000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
reg = <0xf 0xfe200000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe201000 {
|
||||
reg = <0xf 0xfe201000 0 0x1000>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe202000 {
|
||||
reg = <0xf 0xfe202000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,623 @@
|
|||
/*
|
||||
* P2040 Silicon Device Tree Source
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P2040";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
msi0 = &msi0;
|
||||
msi1 = &msi1;
|
||||
msi2 = &msi2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e500mc@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,e500mc@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu2: PowerPC,e500mc@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2_2>;
|
||||
L2_2: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu3: PowerPC,e500mc@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2_3>;
|
||||
L2_3: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,p2040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000>;
|
||||
interrupts = <16 2 1 27>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic", "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi0: msi@41600 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41600 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0 0 0
|
||||
0xe1 0 0 0
|
||||
0xe2 0 0 0
|
||||
0xe3 0 0 0
|
||||
0xe4 0 0 0
|
||||
0xe5 0 0 0
|
||||
0xe6 0 0 0
|
||||
0xe7 0 0 0>;
|
||||
};
|
||||
|
||||
msi1: msi@41800 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41800 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe8 0 0 0
|
||||
0xe9 0 0 0
|
||||
0xea 0 0 0
|
||||
0xeb 0 0 0
|
||||
0xec 0 0 0
|
||||
0xed 0 0 0
|
||||
0xee 0 0 0
|
||||
0xef 0 0 0>;
|
||||
};
|
||||
|
||||
msi2: msi@41a00 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41a00 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xf0 0 0 0
|
||||
0xf1 0 0 0
|
||||
0xf2 0 0 0
|
||||
0xf3 0 0 0
|
||||
0xf4 0 0 0
|
||||
0xf5 0 0 0
|
||||
0xf6 0 0 0
|
||||
0xf7 0 0 0>;
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
pins: global-utilities@e0e00 {
|
||||
compatible = "fsl,qoriq-pin-control-1.0";
|
||||
reg = <0xe0e00 0x200>;
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p2040-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,qoriq-rcpm-1.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
#sleep-cells = <1>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,p2040-sfp", "fsl,qoriq-sfp-1.0";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,p2040-serdes";
|
||||
reg = <0xea000 0x1000>;
|
||||
};
|
||||
|
||||
dma0: dma@100300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
|
||||
reg = <0x100300 0x4>;
|
||||
ranges = <0x0 0x100100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p2040-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <28 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p2040-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <29 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p2040-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <30 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p2040-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <31 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
dma1: dma@101300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
|
||||
reg = <0x101300 0x4>;
|
||||
ranges = <0x0 0x101100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p2040-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <32 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p2040-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <33 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p2040-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <34 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p2040-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <35 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@110000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,p2040-espi", "fsl,mpc8536-espi";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <53 0x2 0 0>;
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
|
||||
};
|
||||
|
||||
sdhc: sdhc@114000 {
|
||||
compatible = "fsl,p2040-esdhc", "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
interrupts = <48 2 0 0>;
|
||||
sdhci,auto-cmd12;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
|
||||
i2c@118000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x118000 0x100>;
|
||||
interrupts = <38 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@118100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x118100 0x100>;
|
||||
interrupts = <38 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@119000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <2>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x119000 0x100>;
|
||||
interrupts = <39 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@119100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <3>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x119100 0x100>;
|
||||
interrupts = <39 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@11c500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11c500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@11c600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11c600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2 0 0>;
|
||||
};
|
||||
|
||||
serial2: serial@11d500 {
|
||||
cell-index = <2>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11d500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2 0 0>;
|
||||
};
|
||||
|
||||
serial3: serial@11d600 {
|
||||
cell-index = <3>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11d600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2 0 0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@130000 {
|
||||
compatible = "fsl,p2040-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <55 2 0 0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl,p2040-usb2-mph",
|
||||
"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x210000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <44 0x2 0 0>;
|
||||
port0;
|
||||
};
|
||||
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl,p2040-usb2-dr",
|
||||
"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
||||
reg = <0x211000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <45 0x2 0 0>;
|
||||
};
|
||||
|
||||
sata@220000 {
|
||||
compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <68 0x2 0 0>;
|
||||
};
|
||||
|
||||
sata@221000 {
|
||||
compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
|
||||
reg = <0x221000 0x1000>;
|
||||
interrupts = <69 0x2 0 0>;
|
||||
};
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
ranges = <0 0x300000 0x10000>;
|
||||
interrupts = <92 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <88 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <89 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <90 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupts = <91 2 0 0>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.2-rtic",
|
||||
"fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sec_mon: sec_mon@314000 {
|
||||
compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
|
||||
reg = <0x314000 0x1000>;
|
||||
interrupts = <93 2 0 0>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
localbus@ffe124000 {
|
||||
compatible = "fsl,p2040-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi0>;
|
||||
interrupts = <16 2 1 15>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 15>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe201000 {
|
||||
compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi1>;
|
||||
interrupts = <16 2 1 14>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 14>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe202000 {
|
||||
compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi2>;
|
||||
interrupts = <16 2 1 13>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 13>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
/*
|
||||
* P3041DS Device Tree Source
|
||||
*
|
||||
* Copyright 2010-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "p3041si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P3041DS";
|
||||
compatible = "fsl,P3041DS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
partition@u-boot {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@kernel {
|
||||
label = "kernel";
|
||||
reg = <0x00100000 0x00500000>;
|
||||
read-only;
|
||||
};
|
||||
partition@dtb {
|
||||
label = "dtb";
|
||||
reg = <0x00600000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@fs {
|
||||
label = "file system";
|
||||
reg = <0x00700000 0x00900000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118100 {
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
};
|
||||
eeprom@52 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@119100 {
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
interrupts = <0x1 0x1 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x1000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xffa00000 0x00040000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x08000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,elbc-fcm-nand";
|
||||
reg = <0x2 0x0 0x40000>;
|
||||
|
||||
partition@0 {
|
||||
label = "NAND U-Boot Image";
|
||||
reg = <0x0 0x02000000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@2000000 {
|
||||
label = "NAND Root File System";
|
||||
reg = <0x02000000 0x10000000>;
|
||||
};
|
||||
|
||||
partition@12000000 {
|
||||
label = "NAND Compressed RFS Image";
|
||||
reg = <0x12000000 0x08000000>;
|
||||
};
|
||||
|
||||
partition@1a000000 {
|
||||
label = "NAND Linux Kernel Image";
|
||||
reg = <0x1a000000 0x04000000>;
|
||||
};
|
||||
|
||||
partition@1e000000 {
|
||||
label = "NAND DTB Image";
|
||||
reg = <0x1e000000 0x01000000>;
|
||||
};
|
||||
|
||||
partition@1f000000 {
|
||||
label = "NAND Writable User area";
|
||||
reg = <0x1f000000 0x21000000>;
|
||||
};
|
||||
};
|
||||
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,p3041ds-pixis";
|
||||
reg = <3 0 0x20>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
reg = <0xf 0xfe200000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe201000 {
|
||||
reg = <0xf 0xfe201000 0 0x1000>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe202000 {
|
||||
reg = <0xf 0xfe202000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci3: pcie@ffe203000 {
|
||||
reg = <0xf 0xfe203000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,660 @@
|
|||
/*
|
||||
* P3041 Silicon Device Tree Source
|
||||
*
|
||||
* Copyright 2010-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P3041";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
msi0 = &msi0;
|
||||
msi1 = &msi1;
|
||||
msi2 = &msi2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
|
||||
/*
|
||||
rio0 = &rapidio0;
|
||||
*/
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e500mc@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,e500mc@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu2: PowerPC,e500mc@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2_2>;
|
||||
L2_2: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu3: PowerPC,e500mc@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2_3>;
|
||||
L2_3: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000>;
|
||||
interrupts = <16 2 1 27>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic", "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi0: msi@41600 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41600 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0 0 0
|
||||
0xe1 0 0 0
|
||||
0xe2 0 0 0
|
||||
0xe3 0 0 0
|
||||
0xe4 0 0 0
|
||||
0xe5 0 0 0
|
||||
0xe6 0 0 0
|
||||
0xe7 0 0 0>;
|
||||
};
|
||||
|
||||
msi1: msi@41800 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41800 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe8 0 0 0
|
||||
0xe9 0 0 0
|
||||
0xea 0 0 0
|
||||
0xeb 0 0 0
|
||||
0xec 0 0 0
|
||||
0xed 0 0 0
|
||||
0xee 0 0 0
|
||||
0xef 0 0 0>;
|
||||
};
|
||||
|
||||
msi2: msi@41a00 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41a00 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xf0 0 0 0
|
||||
0xf1 0 0 0
|
||||
0xf2 0 0 0
|
||||
0xf3 0 0 0
|
||||
0xf4 0 0 0
|
||||
0xf5 0 0 0
|
||||
0xf6 0 0 0
|
||||
0xf7 0 0 0>;
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
pins: global-utilities@e0e00 {
|
||||
compatible = "fsl,qoriq-pin-control-1.0";
|
||||
reg = <0xe0e00 0x200>;
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,qoriq-rcpm-1.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
#sleep-cells = <1>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,p3041-serdes";
|
||||
reg = <0xea000 0x1000>;
|
||||
};
|
||||
|
||||
dma0: dma@100300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
|
||||
reg = <0x100300 0x4>;
|
||||
ranges = <0x0 0x100100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p3041-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <28 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p3041-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <29 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p3041-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <30 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p3041-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <31 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
dma1: dma@101300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
|
||||
reg = <0x101300 0x4>;
|
||||
ranges = <0x0 0x101100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p3041-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <32 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p3041-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <33 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p3041-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <34 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p3041-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <35 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@110000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <53 0x2 0 0>;
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
sdhc: sdhc@114000 {
|
||||
compatible = "fsl,p3041-esdhc", "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
interrupts = <48 2 0 0>;
|
||||
sdhci,auto-cmd12;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x118000 0x100>;
|
||||
interrupts = <38 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@118100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x118100 0x100>;
|
||||
interrupts = <38 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@119000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <2>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x119000 0x100>;
|
||||
interrupts = <39 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@119100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <3>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x119100 0x100>;
|
||||
interrupts = <39 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@11c500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11c500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@11c600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11c600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2 0 0>;
|
||||
};
|
||||
|
||||
serial2: serial@11d500 {
|
||||
cell-index = <2>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11d500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2 0 0>;
|
||||
};
|
||||
|
||||
serial3: serial@11d600 {
|
||||
cell-index = <3>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11d600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2 0 0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@130000 {
|
||||
compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <55 2 0 0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl,p3041-usb2-mph",
|
||||
"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x210000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <44 0x2 0 0>;
|
||||
phy_type = "utmi";
|
||||
port0;
|
||||
};
|
||||
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl,p3041-usb2-dr",
|
||||
"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
||||
reg = <0x211000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <45 0x2 0 0>;
|
||||
dr_mode = "host";
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
sata@220000 {
|
||||
compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <68 0x2 0 0>;
|
||||
};
|
||||
|
||||
sata@221000 {
|
||||
compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
|
||||
reg = <0x221000 0x1000>;
|
||||
interrupts = <69 0x2 0 0>;
|
||||
};
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
ranges = <0 0x300000 0x10000>;
|
||||
interrupts = <92 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <88 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <89 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <90 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupts = <91 2 0 0>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.2-rtic",
|
||||
"fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sec_mon: sec_mon@314000 {
|
||||
compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
|
||||
reg = <0x314000 0x1000>;
|
||||
interrupts = <93 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
rapidio0: rapidio@ffe0c0000
|
||||
*/
|
||||
|
||||
localbus@ffe124000 {
|
||||
compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi0>;
|
||||
interrupts = <16 2 1 15>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 15>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe201000 {
|
||||
compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi1>;
|
||||
interrupts = <16 2 1 14>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 14>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe202000 {
|
||||
compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi2>;
|
||||
interrupts = <16 2 1 13>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 13>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci3: pcie@ffe203000 {
|
||||
compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi2>;
|
||||
interrupts = <16 2 1 12>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 12>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 43 1 0 0
|
||||
0000 0 0 2 &mpic 0 1 0 0
|
||||
0000 0 0 3 &mpic 4 1 0 0
|
||||
0000 0 0 4 &mpic 8 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -3,258 +3,50 @@
|
|||
*
|
||||
* Copyright 2009-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "p4080si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P4080DS";
|
||||
compatible = "fsl,P4080DS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
|
||||
rio0 = &rapidio0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,4080@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,4080@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
};
|
||||
};
|
||||
cpu2: PowerPC,4080@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2_2>;
|
||||
L2_2: l2-cache {
|
||||
};
|
||||
};
|
||||
cpu3: PowerPC,4080@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2_3>;
|
||||
L2_3: l2-cache {
|
||||
};
|
||||
};
|
||||
cpu4: PowerPC,4080@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4>;
|
||||
next-level-cache = <&L2_4>;
|
||||
L2_4: l2-cache {
|
||||
};
|
||||
};
|
||||
cpu5: PowerPC,4080@5 {
|
||||
device_type = "cpu";
|
||||
reg = <5>;
|
||||
next-level-cache = <&L2_5>;
|
||||
L2_5: l2-cache {
|
||||
};
|
||||
};
|
||||
cpu6: PowerPC,4080@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6>;
|
||||
next-level-cache = <&L2_6>;
|
||||
L2_6: l2-cache {
|
||||
};
|
||||
};
|
||||
cpu7: PowerPC,4080@7 {
|
||||
device_type = "cpu";
|
||||
reg = <7>;
|
||||
next-level-cache = <&L2_7>;
|
||||
L2_7: l2-cache {
|
||||
};
|
||||
};
|
||||
};
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
memory-controller@8000 {
|
||||
compatible = "fsl,p4080-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x12 2>;
|
||||
};
|
||||
|
||||
memory-controller@9000 {
|
||||
compatible = "fsl,p4080-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x12 2>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,p4080-pamu";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <24 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
dma0: dma@100300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
|
||||
reg = <0x100300 0x4>;
|
||||
ranges = <0x0 0x100100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <28 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <29 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <30 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <31 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma1: dma@101300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
|
||||
reg = <0x101300 0x4>;
|
||||
ranges = <0x0 0x101100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <32 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <33 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <34 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <35 2>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@110000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <53 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -283,35 +75,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdhc: sdhc@114000 {
|
||||
compatible = "fsl,p4080-esdhc", "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
interrupts = <48 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x118000 0x100>;
|
||||
interrupts = <38 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@118100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x118100 0x100>;
|
||||
interrupts = <38 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
|
|
@ -323,198 +87,27 @@
|
|||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
interrupts = <0 0x1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x1 0x1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@119000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <2>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x119000 0x100>;
|
||||
interrupts = <39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@119100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <3>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x119100 0x100>;
|
||||
interrupts = <39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@11c500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11c500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@11c600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11c600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial2: serial@11d500 {
|
||||
cell-index = <2>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11d500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial3: serial@11d600 {
|
||||
cell-index = <3>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11d600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
gpio0: gpio@130000 {
|
||||
compatible = "fsl,p4080-gpio";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <55 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl,p4080-usb2-mph",
|
||||
"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x210000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <44 0x2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl,p4080-usb2-dr",
|
||||
"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
||||
reg = <0x211000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <45 0x2>;
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
ranges = <0 0x300000 0x10000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <92 2>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <88 2>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <89 2>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <90 2>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <91 2>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sec_mon: sec_mon@314000 {
|
||||
compatible = "fsl,sec-v4.0-mon";
|
||||
reg = <0x314000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <93 2>;
|
||||
};
|
||||
};
|
||||
|
||||
rapidio0: rapidio@ffe0c0000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "fsl,rapidio-delta";
|
||||
reg = <0xf 0xfe0c0000 0 0x20000>;
|
||||
ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/* err_irq bell_outb_irq bell_inb_irq
|
||||
msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
|
||||
interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
|
||||
ranges = <0 0 0xc 0x20000000 0 0x01000000>;
|
||||
};
|
||||
|
||||
localbus@ffe124000 {
|
||||
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0xf 0xfe124000 0 0x1000>;
|
||||
interrupts = <25 2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000>;
|
||||
|
||||
flash@0,0 {
|
||||
|
|
@ -526,32 +119,10 @@
|
|||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
compatible = "fsl,p4080-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf 0xfe200000 0 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1
|
||||
0000 0 0 2 &mpic 1 1
|
||||
0000 0 0 3 &mpic 2 1
|
||||
0000 0 0 4 &mpic 3 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
|
@ -563,31 +134,10 @@
|
|||
};
|
||||
|
||||
pci1: pcie@ffe201000 {
|
||||
compatible = "fsl,p4080-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf 0xfe201000 0 0x1000>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1
|
||||
0000 0 0 2 &mpic 5 1
|
||||
0000 0 0 3 &mpic 6 1
|
||||
0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
|
@ -599,31 +149,10 @@
|
|||
};
|
||||
|
||||
pci2: pcie@ffe202000 {
|
||||
compatible = "fsl,p4080-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf 0xfe202000 0 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1
|
||||
0000 0 0 2 &mpic 9 1
|
||||
0000 0 0 3 &mpic 10 1
|
||||
0000 0 0 4 &mpic 11 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
|
|
|||
|
|
@ -0,0 +1,661 @@
|
|||
/*
|
||||
* P4080 Silicon Device Tree Source
|
||||
*
|
||||
* Copyright 2009-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P4080";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
msi0 = &msi0;
|
||||
msi1 = &msi1;
|
||||
msi2 = &msi2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
|
||||
rio0 = &rapidio0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,4080@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,4080@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu2: PowerPC,4080@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2_2>;
|
||||
L2_2: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu3: PowerPC,4080@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2_3>;
|
||||
L2_3: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu4: PowerPC,4080@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4>;
|
||||
next-level-cache = <&L2_4>;
|
||||
L2_4: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu5: PowerPC,4080@5 {
|
||||
device_type = "cpu";
|
||||
reg = <5>;
|
||||
next-level-cache = <&L2_5>;
|
||||
L2_5: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu6: PowerPC,4080@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6>;
|
||||
next-level-cache = <&L2_6>;
|
||||
L2_6: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu7: PowerPC,4080@7 {
|
||||
device_type = "cpu";
|
||||
reg = <7>;
|
||||
next-level-cache = <&L2_7>;
|
||||
L2_7: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 22>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,p4080-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000
|
||||
0x11000 0x1000>;
|
||||
interrupts = <16 2 1 27
|
||||
16 2 1 26>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x5000>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic", "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi0: msi@41600 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41600 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0 0 0
|
||||
0xe1 0 0 0
|
||||
0xe2 0 0 0
|
||||
0xe3 0 0 0
|
||||
0xe4 0 0 0
|
||||
0xe5 0 0 0
|
||||
0xe6 0 0 0
|
||||
0xe7 0 0 0>;
|
||||
};
|
||||
|
||||
msi1: msi@41800 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41800 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe8 0 0 0
|
||||
0xe9 0 0 0
|
||||
0xea 0 0 0
|
||||
0xeb 0 0 0
|
||||
0xec 0 0 0
|
||||
0xed 0 0 0
|
||||
0xee 0 0 0
|
||||
0xef 0 0 0>;
|
||||
};
|
||||
|
||||
msi2: msi@41a00 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41a00 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xf0 0 0 0
|
||||
0xf1 0 0 0
|
||||
0xf2 0 0 0
|
||||
0xf3 0 0 0
|
||||
0xf4 0 0 0
|
||||
0xf5 0 0 0
|
||||
0xf6 0 0 0
|
||||
0xf7 0 0 0>;
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
pins: global-utilities@e0e00 {
|
||||
compatible = "fsl,qoriq-pin-control-1.0";
|
||||
reg = <0xe0e00 0x200>;
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,qoriq-rcpm-1.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
#sleep-cells = <1>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,p4080-serdes";
|
||||
reg = <0xea000 0x1000>;
|
||||
};
|
||||
|
||||
dma0: dma@100300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
|
||||
reg = <0x100300 0x4>;
|
||||
ranges = <0x0 0x100100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <28 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <29 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <30 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <31 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
dma1: dma@101300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
|
||||
reg = <0x101300 0x4>;
|
||||
ranges = <0x0 0x101100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <32 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <33 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <34 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p4080-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <35 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@110000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <53 0x2 0 0>;
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
sdhc: sdhc@114000 {
|
||||
compatible = "fsl,p4080-esdhc", "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
interrupts = <48 2 0 0>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x118000 0x100>;
|
||||
interrupts = <38 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@118100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x118100 0x100>;
|
||||
interrupts = <38 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@119000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <2>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x119000 0x100>;
|
||||
interrupts = <39 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@119100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <3>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x119100 0x100>;
|
||||
interrupts = <39 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@11c500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11c500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@11c600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11c600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2 0 0>;
|
||||
};
|
||||
|
||||
serial2: serial@11d500 {
|
||||
cell-index = <2>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11d500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2 0 0>;
|
||||
};
|
||||
|
||||
serial3: serial@11d600 {
|
||||
cell-index = <3>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11d600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2 0 0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@130000 {
|
||||
compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <55 2 0 0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl,p4080-usb2-mph",
|
||||
"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x210000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <44 0x2 0 0>;
|
||||
};
|
||||
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl,p4080-usb2-dr",
|
||||
"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
||||
reg = <0x211000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <45 0x2 0 0>;
|
||||
};
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
ranges = <0 0x300000 0x10000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <92 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <88 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <89 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <90 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <91 2 0 0>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sec_mon: sec_mon@314000 {
|
||||
compatible = "fsl,sec-v4.0-mon";
|
||||
reg = <0x314000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <93 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
rapidio0: rapidio@ffe0c0000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "fsl,rapidio-delta";
|
||||
interrupts = <
|
||||
16 2 1 11 /* err_irq */
|
||||
56 2 0 0 /* bell_outb_irq */
|
||||
57 2 0 0 /* bell_inb_irq */
|
||||
60 2 0 0 /* msg1_tx_irq */
|
||||
61 2 0 0 /* msg1_rx_irq */
|
||||
62 2 0 0 /* msg2_tx_irq */
|
||||
63 2 0 0>; /* msg2_rx_irq */
|
||||
};
|
||||
|
||||
localbus@ffe124000 {
|
||||
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
compatible = "fsl,p4080-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi0>;
|
||||
interrupts = <16 2 1 15>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 15>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe201000 {
|
||||
compatible = "fsl,p4080-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi1>;
|
||||
interrupts = <16 2 1 14>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 14>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe202000 {
|
||||
compatible = "fsl,p4080-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi2>;
|
||||
interrupts = <16 2 1 13>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 13>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
/*
|
||||
* P5020DS Device Tree Source
|
||||
*
|
||||
* Copyright 2010-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "p5020si.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P5020DS";
|
||||
compatible = "fsl,P5020DS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
partition@u-boot {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@kernel {
|
||||
label = "kernel";
|
||||
reg = <0x00100000 0x00500000>;
|
||||
read-only;
|
||||
};
|
||||
partition@dtb {
|
||||
label = "dtb";
|
||||
reg = <0x00600000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@fs {
|
||||
label = "file system";
|
||||
reg = <0x00700000 0x00900000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118100 {
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
};
|
||||
eeprom@52 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@119100 {
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
interrupts = <0x1 0x1 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x1000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xffa00000 0x00040000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x08000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,elbc-fcm-nand";
|
||||
reg = <0x2 0x0 0x40000>;
|
||||
|
||||
partition@0 {
|
||||
label = "NAND U-Boot Image";
|
||||
reg = <0x0 0x02000000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@2000000 {
|
||||
label = "NAND Root File System";
|
||||
reg = <0x02000000 0x10000000>;
|
||||
};
|
||||
|
||||
partition@12000000 {
|
||||
label = "NAND Compressed RFS Image";
|
||||
reg = <0x12000000 0x08000000>;
|
||||
};
|
||||
|
||||
partition@1a000000 {
|
||||
label = "NAND Linux Kernel Image";
|
||||
reg = <0x1a000000 0x04000000>;
|
||||
};
|
||||
|
||||
partition@1e000000 {
|
||||
label = "NAND DTB Image";
|
||||
reg = <0x1e000000 0x01000000>;
|
||||
};
|
||||
|
||||
partition@1f000000 {
|
||||
label = "NAND Writable User area";
|
||||
reg = <0x1f000000 0x21000000>;
|
||||
};
|
||||
};
|
||||
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,p5020ds-pixis";
|
||||
reg = <3 0 0x20>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
reg = <0xf 0xfe200000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
||||
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe201000 {
|
||||
reg = <0xf 0xfe201000 0 0x1000>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe202000 {
|
||||
reg = <0xf 0xfe202000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci3: pcie@ffe203000 {
|
||||
reg = <0xf 0xfe203000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,652 @@
|
|||
/*
|
||||
* P5020 Silicon Device Tree Source
|
||||
*
|
||||
* Copyright 2010-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P5020";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
msi0 = &msi0;
|
||||
msi1 = &msi1;
|
||||
msi2 = &msi2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
|
||||
/*
|
||||
rio0 = &rapidio0;
|
||||
*/
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e5500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,e5500@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 22>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000
|
||||
0x11000 0x1000>;
|
||||
interrupts = <16 2 1 27
|
||||
16 2 1 26>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic", "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi0: msi@41600 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41600 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0 0 0
|
||||
0xe1 0 0 0
|
||||
0xe2 0 0 0
|
||||
0xe3 0 0 0
|
||||
0xe4 0 0 0
|
||||
0xe5 0 0 0
|
||||
0xe6 0 0 0
|
||||
0xe7 0 0 0>;
|
||||
};
|
||||
|
||||
msi1: msi@41800 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41800 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe8 0 0 0
|
||||
0xe9 0 0 0
|
||||
0xea 0 0 0
|
||||
0xeb 0 0 0
|
||||
0xec 0 0 0
|
||||
0xed 0 0 0
|
||||
0xee 0 0 0
|
||||
0xef 0 0 0>;
|
||||
};
|
||||
|
||||
msi2: msi@41a00 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41a00 0x200>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xf0 0 0 0
|
||||
0xf1 0 0 0
|
||||
0xf2 0 0 0
|
||||
0xf3 0 0 0
|
||||
0xf4 0 0 0
|
||||
0xf5 0 0 0
|
||||
0xf6 0 0 0
|
||||
0xf7 0 0 0>;
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
pins: global-utilities@e0e00 {
|
||||
compatible = "fsl,qoriq-pin-control-1.0";
|
||||
reg = <0xe0e00 0x200>;
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,qoriq-rcpm-1.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
#sleep-cells = <1>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,p5020-serdes";
|
||||
reg = <0xea000 0x1000>;
|
||||
};
|
||||
|
||||
dma0: dma@100300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
|
||||
reg = <0x100300 0x4>;
|
||||
ranges = <0x0 0x100100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p5020-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <28 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p5020-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <29 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p5020-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <30 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p5020-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <31 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
dma1: dma@101300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
|
||||
reg = <0x101300 0x4>;
|
||||
ranges = <0x0 0x101100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,p5020-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <32 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,p5020-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <33 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,p5020-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <34 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,p5020-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <35 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@110000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <53 0x2 0 0>;
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
sdhc: sdhc@114000 {
|
||||
compatible = "fsl,p5020-esdhc", "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
interrupts = <48 2 0 0>;
|
||||
sdhci,auto-cmd12;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x118000 0x100>;
|
||||
interrupts = <38 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@118100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x118100 0x100>;
|
||||
interrupts = <38 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@119000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <2>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x119000 0x100>;
|
||||
interrupts = <39 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@119100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <3>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x119100 0x100>;
|
||||
interrupts = <39 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@11c500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11c500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@11c600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11c600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <36 2 0 0>;
|
||||
};
|
||||
|
||||
serial2: serial@11d500 {
|
||||
cell-index = <2>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11d500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2 0 0>;
|
||||
};
|
||||
|
||||
serial3: serial@11d600 {
|
||||
cell-index = <3>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x11d600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <37 2 0 0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@130000 {
|
||||
compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x130000 0x1000>;
|
||||
interrupts = <55 2 0 0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl,p5020-usb2-mph",
|
||||
"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x210000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <44 0x2 0 0>;
|
||||
phy_type = "utmi";
|
||||
port0;
|
||||
};
|
||||
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl,p5020-usb2-dr",
|
||||
"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
||||
reg = <0x211000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <45 0x2 0 0>;
|
||||
dr_mode = "host";
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
sata@220000 {
|
||||
compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <68 0x2 0 0>;
|
||||
};
|
||||
|
||||
sata@221000 {
|
||||
compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
|
||||
reg = <0x221000 0x1000>;
|
||||
interrupts = <69 0x2 0 0>;
|
||||
};
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
ranges = <0 0x300000 0x10000>;
|
||||
interrupts = <92 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <88 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <89 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <90 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupts = <91 2 0 0>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.2-rtic",
|
||||
"fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sec_mon: sec_mon@314000 {
|
||||
compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
|
||||
reg = <0x314000 0x1000>;
|
||||
interrupts = <93 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
rapidio0: rapidio@ffe0c0000
|
||||
*/
|
||||
|
||||
localbus@ffe124000 {
|
||||
compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi0>;
|
||||
interrupts = <16 2 1 15>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 15>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe201000 {
|
||||
compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi1>;
|
||||
interrupts = <16 2 1 14>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 14>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe202000 {
|
||||
compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi2>;
|
||||
interrupts = <16 2 1 13>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 13>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pci3: pcie@ffe203000 {
|
||||
compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <0x1fca055>;
|
||||
fsl,msi = <&msi2>;
|
||||
interrupts = <16 2 1 12>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 12>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 43 1 0 0
|
||||
0000 0 0 2 &mpic 0 1 0 0
|
||||
0000 0 0 3 &mpic 4 1 0 0
|
||||
0000 0 0 4 &mpic 8 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -110,6 +110,18 @@
|
|||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
CRYPTO: crypto@e0100000 {
|
||||
compatible = "amcc,ppc440epx-crypto","amcc,ppc4xx-crypto";
|
||||
reg = <0 0xE0100000 0x80400>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x17 0x4>;
|
||||
};
|
||||
|
||||
rng@e0120000 {
|
||||
compatible = "amcc,ppc440epx-rng","amcc,ppc4xx-rng";
|
||||
reg = <0 0xE0120000 0x150>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
compatible = "ibm,dma-440epx", "ibm,dma-4xx";
|
||||
dcr-reg = <0x100 0x027>;
|
||||
|
|
|
|||
|
|
@ -240,6 +240,8 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xe0005000 0x40>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <19 2>;
|
||||
|
||||
ranges = <0 0 0xfc000000 0x04000000
|
||||
2 0 0xc8000000 0x04000000
|
||||
|
|
|
|||
|
|
@ -337,7 +337,7 @@
|
|||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000001>;
|
||||
phy-address = <1>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
zmii-device = <&ZMII0>;
|
||||
|
|
@ -361,7 +361,7 @@
|
|||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000003>;
|
||||
phy-address = <3>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
zmii-device = <&ZMII0>;
|
||||
|
|
|
|||
|
|
@ -277,6 +277,48 @@
|
|||
};
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8540-localbus", "fsl,pq3-localbus",
|
||||
"simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <19 2>;
|
||||
|
||||
ranges = <0x0 0x0 0xfe000000 0x02000000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x02000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x00180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "root";
|
||||
reg = <0x00180000 0x01dc0000>;
|
||||
};
|
||||
partition@1f40000 {
|
||||
label = "env1";
|
||||
reg = <0x01f40000 0x00040000>;
|
||||
};
|
||||
partition@1f80000 {
|
||||
label = "env2";
|
||||
reg = <0x01f80000 0x00040000>;
|
||||
};
|
||||
partition@1fc0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x01fc0000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008000 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -346,6 +346,8 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xa0005000 0x100>; // BRx, ORx, etc.
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <19 2>;
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
|
||||
|
|
|
|||
|
|
@ -346,6 +346,8 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xe0005000 0x100>; // BRx, ORx, etc.
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <19 2>;
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
|
||||
|
|
|
|||
|
|
@ -312,6 +312,8 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xe0005000 0x100>; // BRx, ORx, etc.
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <19 2>;
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
|
||||
|
|
|
|||
|
|
@ -374,6 +374,8 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xef005000 0x100>; // BRx, ORx, etc.
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <19 2>;
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xfc000000 0x04000000 // NOR boot flash
|
||||
|
|
|
|||
|
|
@ -378,6 +378,8 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xef005000 0x100>; // BRx, ORx, etc.
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <19 2>;
|
||||
|
||||
ranges = <
|
||||
0 0x0 0xf8000000 0x08000000 // NOR boot flash
|
||||
|
|
|
|||
|
|
@ -34,9 +34,29 @@
|
|||
|
||||
BSS_STACK(4096);
|
||||
|
||||
static u32 ibm4xx_memstart;
|
||||
|
||||
static void iss_4xx_fixups(void)
|
||||
{
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
void *memory;
|
||||
u32 reg[3];
|
||||
|
||||
memory = finddevice("/memory");
|
||||
if (!memory)
|
||||
fatal("Can't find memory node\n");
|
||||
/* This assumes #address-cells = 2, #size-cells =1 and that */
|
||||
getprop(memory, "reg", reg, sizeof(reg));
|
||||
if (reg[2])
|
||||
/* If the device tree specifies the memory range, use it */
|
||||
ibm4xx_memstart = reg[1];
|
||||
else
|
||||
/* othersize, read it from the SDRAM controller */
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
}
|
||||
|
||||
static void *iss_4xx_vmlinux_alloc(unsigned long size)
|
||||
{
|
||||
return (void *)ibm4xx_memstart;
|
||||
}
|
||||
|
||||
#define SPRN_PIR 0x11E /* Processor Indentification Register */
|
||||
|
|
@ -48,6 +68,7 @@ void platform_init(void)
|
|||
|
||||
simple_alloc_init(_end, avail_ram, 128, 64);
|
||||
platform_ops.fixups = iss_4xx_fixups;
|
||||
platform_ops.vmlinux_alloc = iss_4xx_vmlinux_alloc;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
pir_reg = mfspr(SPRN_PIR);
|
||||
fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ CONFIG_SMP=y
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_SYSFS_DEPRECATED_V2=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_EXPERT=y
|
||||
|
|
@ -21,10 +21,11 @@ CONFIG_ISS4xx=y
|
|||
CONFIG_HZ_100=y
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_IRQ_ALL_CPUS=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="root=/dev/issblk0"
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_ADVANCED_OPTIONS=y
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
|
@ -67,7 +68,6 @@ CONFIG_EXT3_FS=y
|
|||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS_SECURITY=y
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_CRAMFS=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,173 @@
|
|||
CONFIG_PPC_85xx=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_KALLSYMS_EXTRA_PASS=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_P1023_RDS=y
|
||||
CONFIG_QUICC_ENGINE=y
|
||||
CONFIG_QE_GPIO=y
|
||||
CONFIG_CPM2=y
|
||||
CONFIG_MPC8xxx_GPIO=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
# CONFIG_PCIEAER is not set
|
||||
# CONFIG_PCIEASPM is not set
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_ARPD=y
|
||||
CONFIG_INET_ESP=y
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IP_SCTP=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=131072
|
||||
CONFIG_MISC_DEVICES=y
|
||||
CONFIG_EEPROM_LEGACY=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_ST=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_FSL=y
|
||||
CONFIG_SATA_SIL24=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_DAVICOM_PHY=y
|
||||
CONFIG_CICADA_PHY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_FS_ENET=y
|
||||
CONFIG_E1000E=y
|
||||
CONFIG_FSL_PQ_MDIO=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_MANY_PORTS=y
|
||||
CONFIG_SERIAL_8250_DETECT_IRQ=y
|
||||
CONFIG_SERIAL_8250_RSA=y
|
||||
CONFIG_SERIAL_QE=m
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_NVRAM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CPM=m
|
||||
CONFIG_I2C_MPC=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_MIXER_OSS=y
|
||||
CONFIG_SND_PCM_OSS=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
CONFIG_EDAC=y
|
||||
CONFIG_EDAC_MM_EDAC=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_FSL_DMA=y
|
||||
# CONFIG_NET_DMA is not set
|
||||
CONFIG_STAGING=y
|
||||
# CONFIG_STAGING_EXCLUDE_BUILD is not set
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_ISO9660_FS=m
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
CONFIG_UDF_FS=m
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_ADFS_FS=m
|
||||
CONFIG_AFFS_FS=m
|
||||
CONFIG_HFS_FS=m
|
||||
CONFIG_HFSPLUS_FS=m
|
||||
CONFIG_BEFS_FS=m
|
||||
CONFIG_BFS_FS=m
|
||||
CONFIG_EFS_FS=m
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_VXFS_FS=m
|
||||
CONFIG_HPFS_FS=m
|
||||
CONFIG_QNX4FS_FS=m
|
||||
CONFIG_SYSV_FS=m
|
||||
CONFIG_UFS_FS=m
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_FRAME_WARN=8092
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_VIRQ_DEBUG=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
|
|
@ -89,6 +89,11 @@ CONFIG_I2C_MPC=y
|
|||
CONFIG_VIDEO_OUTPUT_CONTROL=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_FSL_DIU=y
|
||||
CONFIG_VGACON_SOFT_SCROLLBACK=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FONTS=y
|
||||
CONFIG_FONT_8x8=y
|
||||
CONFIG_FONT_8x16=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_MIXER_OSS=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,187 @@
|
|||
CONFIG_PPC_85xx=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=8
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_KALLSYMS_EXTRA_PASS=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_P2040_RDB=y
|
||||
CONFIG_P3041_DS=y
|
||||
CONFIG_P4080_DS=y
|
||||
CONFIG_P5020_DS=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=13
|
||||
CONFIG_FSL_LBC=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
# CONFIG_PCIEASPM is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_XFRM_SUB_POLICY=y
|
||||
CONFIG_XFRM_STATISTICS=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_NET_KEY_MIGRATE=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_ARPD=y
|
||||
CONFIG_INET_AH=y
|
||||
CONFIG_INET_ESP=y
|
||||
CONFIG_INET_IPCOMP=y
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IP_SCTP=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=131072
|
||||
CONFIG_MISC_DEVICES=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_ST=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SYM53C8XX_2=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_SATA_FSL=y
|
||||
CONFIG_SATA_SIL24=y
|
||||
CONFIG_SATA_SIL=y
|
||||
CONFIG_PATA_SIL680=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_E1000E=y
|
||||
CONFIG_FSL_PQ_MDIO=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_PPC_EPAPR_HV_BYTECHAN=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_MANY_PORTS=y
|
||||
CONFIG_SERIAL_8250_DETECT_IRQ=y
|
||||
CONFIG_SERIAL_8250_RSA=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_NVRAM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_MPC=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_GPIO=y
|
||||
CONFIG_SPI_FSL_SPI=y
|
||||
CONFIG_SPI_FSL_ESPI=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=y
|
||||
CONFIG_USB_HID=m
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_DEVICEFS=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_FSL=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
|
||||
CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_OF=y
|
||||
CONFIG_MMC_SDHCI_OF_ESDHC=y
|
||||
CONFIG_EDAC=y
|
||||
CONFIG_EDAC_MM_EDAC=y
|
||||
CONFIG_EDAC_MPC85XX=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_DS3232=y
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_UIO=y
|
||||
CONFIG_STAGING=y
|
||||
# CONFIG_STAGING_EXCLUDE_BUILD is not set
|
||||
CONFIG_VIRT_DRIVERS=y
|
||||
CONFIG_FSL_HV_MANAGER=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_ISO9660_FS=m
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
CONFIG_UDF_FS=m
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=m
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_UTF8=m
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_SHIRQ=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_CRYPTO_NULL=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_MD4=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
|
|
@ -5,6 +5,7 @@ CONFIG_SYSVIPC=y
|
|||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
|
|
@ -25,7 +26,9 @@ CONFIG_MPC85xx_MDS=y
|
|||
CONFIG_MPC8536_DS=y
|
||||
CONFIG_MPC85xx_DS=y
|
||||
CONFIG_MPC85xx_RDB=y
|
||||
CONFIG_P1010_RDB=y
|
||||
CONFIG_P1022_DS=y
|
||||
CONFIG_P1023_RDS=y
|
||||
CONFIG_SOCRATES=y
|
||||
CONFIG_KSI8560=y
|
||||
CONFIG_XES_MPC85xx=y
|
||||
|
|
@ -44,7 +47,6 @@ CONFIG_NO_HZ=y
|
|||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=12
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_MSI=y
|
||||
|
|
@ -65,8 +67,6 @@ CONFIG_IP_PNP_DHCP=y
|
|||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=y
|
||||
CONFIG_NET_IPGRE=y
|
||||
CONFIG_NET_IPGRE_BROADCAST=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
|
|
@ -128,6 +128,10 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
|
|||
CONFIG_FB=y
|
||||
CONFIG_FB_FSL_DIU=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FONTS=y
|
||||
CONFIG_FONT_8x8=y
|
||||
CONFIG_FONT_8x16=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
|
|
@ -170,7 +174,6 @@ CONFIG_FSL_DMA=y
|
|||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_ISO9660_FS=m
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
|
|
@ -205,7 +208,6 @@ CONFIG_DEBUG_FS=y
|
|||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_VIRQ_DEBUG=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ CONFIG_SYSVIPC=y
|
|||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
|
|
@ -28,6 +29,7 @@ CONFIG_MPC8536_DS=y
|
|||
CONFIG_MPC85xx_DS=y
|
||||
CONFIG_MPC85xx_RDB=y
|
||||
CONFIG_P1022_DS=y
|
||||
CONFIG_P1023_RDS=y
|
||||
CONFIG_SOCRATES=y
|
||||
CONFIG_KSI8560=y
|
||||
CONFIG_XES_MPC85xx=y
|
||||
|
|
@ -46,7 +48,6 @@ CONFIG_NO_HZ=y
|
|||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=12
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_MSI=y
|
||||
|
|
@ -67,8 +68,6 @@ CONFIG_IP_PNP_DHCP=y
|
|||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=y
|
||||
CONFIG_NET_IPGRE=y
|
||||
CONFIG_NET_IPGRE_BROADCAST=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
|
|
@ -130,6 +129,10 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
|
|||
CONFIG_FB=y
|
||||
CONFIG_FB_FSL_DIU=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FONTS=y
|
||||
CONFIG_FONT_8x8=y
|
||||
CONFIG_FONT_8x16=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
|
|
@ -172,7 +175,6 @@ CONFIG_FSL_DMA=y
|
|||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_ISO9660_FS=m
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
|
|
|
|||
|
|
@ -176,12 +176,19 @@ CONFIG_CHR_DEV_SG=y
|
|||
CONFIG_SCSI_MULTI_LUN=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_FC_ATTRS=y
|
||||
CONFIG_SCSI_SAS_ATTRS=m
|
||||
CONFIG_SCSI_CXGB3_ISCSI=m
|
||||
CONFIG_SCSI_CXGB4_ISCSI=m
|
||||
CONFIG_SCSI_BNX2_ISCSI=m
|
||||
CONFIG_BE2ISCSI=m
|
||||
CONFIG_SCSI_MPT2SAS=m
|
||||
CONFIG_SCSI_IBMVSCSI=y
|
||||
CONFIG_SCSI_IBMVFC=m
|
||||
CONFIG_SCSI_SYM53C8XX_2=y
|
||||
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
|
||||
CONFIG_SCSI_IPR=y
|
||||
CONFIG_SCSI_QLA_FC=m
|
||||
CONFIG_SCSI_QLA_ISCSI=m
|
||||
CONFIG_SCSI_LPFC=m
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_SIL24=y
|
||||
|
|
@ -235,11 +242,13 @@ CONFIG_ACENIC_OMIT_TIGON_I=y
|
|||
CONFIG_E1000=y
|
||||
CONFIG_E1000E=y
|
||||
CONFIG_TIGON3=y
|
||||
CONFIG_BNX2=m
|
||||
CONFIG_SPIDER_NET=m
|
||||
CONFIG_GELIC_NET=m
|
||||
CONFIG_GELIC_WIRELESS=y
|
||||
CONFIG_CHELSIO_T1=m
|
||||
CONFIG_CHELSIO_T3=m
|
||||
CONFIG_CHELSIO_T4=m
|
||||
CONFIG_EHEA=m
|
||||
CONFIG_IXGBE=m
|
||||
CONFIG_IXGB=m
|
||||
|
|
@ -248,6 +257,8 @@ CONFIG_MYRI10GE=m
|
|||
CONFIG_NETXEN_NIC=m
|
||||
CONFIG_PASEMI_MAC=y
|
||||
CONFIG_MLX4_EN=m
|
||||
CONFIG_QLGE=m
|
||||
CONFIG_BE2NET=m
|
||||
CONFIG_ISERIES_VETH=m
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
|
|
@ -330,6 +341,8 @@ CONFIG_INFINIBAND_USER_MAD=m
|
|||
CONFIG_INFINIBAND_USER_ACCESS=m
|
||||
CONFIG_INFINIBAND_MTHCA=m
|
||||
CONFIG_INFINIBAND_EHCA=m
|
||||
CONFIG_INFINIBAND_CXGB3=m
|
||||
CONFIG_INFINIBAND_CXGB4=m
|
||||
CONFIG_MLX4_INFINIBAND=m
|
||||
CONFIG_INFINIBAND_IPOIB=m
|
||||
CONFIG_INFINIBAND_IPOIB_CM=y
|
||||
|
|
@ -430,11 +443,12 @@ CONFIG_NLS_KOI8_U=m
|
|||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_LATENCYTOP=y
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_IRQSOFF_TRACER=y
|
||||
CONFIG_SCHED_TRACER=y
|
||||
CONFIG_BLK_DEV_IO_TRACE=y
|
||||
CONFIG_DEBUG_STACKOVERFLOW=y
|
||||
|
|
|
|||
|
|
@ -149,6 +149,7 @@ CONFIG_SCSI_CXGB3_ISCSI=m
|
|||
CONFIG_SCSI_CXGB4_ISCSI=m
|
||||
CONFIG_SCSI_BNX2_ISCSI=m
|
||||
CONFIG_BE2ISCSI=m
|
||||
CONFIG_SCSI_MPT2SAS=m
|
||||
CONFIG_SCSI_IBMVSCSI=y
|
||||
CONFIG_SCSI_IBMVFC=m
|
||||
CONFIG_SCSI_SYM53C8XX_2=y
|
||||
|
|
@ -320,6 +321,8 @@ CONFIG_NLS_ISO8859_1=y
|
|||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_LATENCYTOP=y
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
#include <asm/ppc-opcode.h>
|
||||
|
||||
#define PPC_DBELL_MSG_BRDCAST (0x04000000)
|
||||
#define PPC_DBELL_TYPE(x) (((x) & 0xf) << 28)
|
||||
#define PPC_DBELL_TYPE(x) (((x) & 0xf) << (63-36))
|
||||
enum ppc_dbell {
|
||||
PPC_DBELL = 0, /* doorbell */
|
||||
PPC_DBELL_CRIT = 1, /* critical doorbell */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* EHV_PIC private definitions and structure.
|
||||
*
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
#ifndef __EHV_PIC_H__
|
||||
#define __EHV_PIC_H__
|
||||
|
||||
#include <linux/irq.h>
|
||||
|
||||
#define NR_EHV_PIC_INTS 1024
|
||||
|
||||
#define EHV_PIC_INFO(name) EHV_PIC_##name
|
||||
|
||||
#define EHV_PIC_VECPRI_POLARITY_NEGATIVE 0
|
||||
#define EHV_PIC_VECPRI_POLARITY_POSITIVE 1
|
||||
#define EHV_PIC_VECPRI_SENSE_EDGE 0
|
||||
#define EHV_PIC_VECPRI_SENSE_LEVEL 0x2
|
||||
#define EHV_PIC_VECPRI_POLARITY_MASK 0x1
|
||||
#define EHV_PIC_VECPRI_SENSE_MASK 0x2
|
||||
|
||||
struct ehv_pic {
|
||||
/* The remapper for this EHV_PIC */
|
||||
struct irq_host *irqhost;
|
||||
|
||||
/* The "linux" controller struct */
|
||||
struct irq_chip hc_irq;
|
||||
|
||||
/* core int flag */
|
||||
int coreint_flag;
|
||||
};
|
||||
|
||||
void ehv_pic_init(void);
|
||||
unsigned int ehv_pic_get_irq(void);
|
||||
|
||||
#endif /* __EHV_PIC_H__ */
|
||||
|
|
@ -0,0 +1,502 @@
|
|||
/*
|
||||
* ePAPR hcall interface
|
||||
*
|
||||
* Copyright 2008-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Timur Tabi <timur@freescale.com>
|
||||
*
|
||||
* This file is provided under a dual BSD/GPL license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* A "hypercall" is an "sc 1" instruction. This header file file provides C
|
||||
* wrapper functions for the ePAPR hypervisor interface. It is inteded
|
||||
* for use by Linux device drivers and other operating systems.
|
||||
*
|
||||
* The hypercalls are implemented as inline assembly, rather than assembly
|
||||
* language functions in a .S file, for optimization. It allows
|
||||
* the caller to issue the hypercall instruction directly, improving both
|
||||
* performance and memory footprint.
|
||||
*/
|
||||
|
||||
#ifndef _EPAPR_HCALLS_H
|
||||
#define _EPAPR_HCALLS_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#define EV_BYTE_CHANNEL_SEND 1
|
||||
#define EV_BYTE_CHANNEL_RECEIVE 2
|
||||
#define EV_BYTE_CHANNEL_POLL 3
|
||||
#define EV_INT_SET_CONFIG 4
|
||||
#define EV_INT_GET_CONFIG 5
|
||||
#define EV_INT_SET_MASK 6
|
||||
#define EV_INT_GET_MASK 7
|
||||
#define EV_INT_IACK 9
|
||||
#define EV_INT_EOI 10
|
||||
#define EV_INT_SEND_IPI 11
|
||||
#define EV_INT_SET_TASK_PRIORITY 12
|
||||
#define EV_INT_GET_TASK_PRIORITY 13
|
||||
#define EV_DOORBELL_SEND 14
|
||||
#define EV_MSGSND 15
|
||||
#define EV_IDLE 16
|
||||
|
||||
/* vendor ID: epapr */
|
||||
#define EV_LOCAL_VENDOR_ID 0 /* for private use */
|
||||
#define EV_EPAPR_VENDOR_ID 1
|
||||
#define EV_FSL_VENDOR_ID 2 /* Freescale Semiconductor */
|
||||
#define EV_IBM_VENDOR_ID 3 /* IBM */
|
||||
#define EV_GHS_VENDOR_ID 4 /* Green Hills Software */
|
||||
#define EV_ENEA_VENDOR_ID 5 /* Enea */
|
||||
#define EV_WR_VENDOR_ID 6 /* Wind River Systems */
|
||||
#define EV_AMCC_VENDOR_ID 7 /* Applied Micro Circuits */
|
||||
#define EV_KVM_VENDOR_ID 42 /* KVM */
|
||||
|
||||
/* The max number of bytes that a byte channel can send or receive per call */
|
||||
#define EV_BYTE_CHANNEL_MAX_BYTES 16
|
||||
|
||||
|
||||
#define _EV_HCALL_TOKEN(id, num) (((id) << 16) | (num))
|
||||
#define EV_HCALL_TOKEN(hcall_num) _EV_HCALL_TOKEN(EV_EPAPR_VENDOR_ID, hcall_num)
|
||||
|
||||
/* epapr error codes */
|
||||
#define EV_EPERM 1 /* Operation not permitted */
|
||||
#define EV_ENOENT 2 /* Entry Not Found */
|
||||
#define EV_EIO 3 /* I/O error occured */
|
||||
#define EV_EAGAIN 4 /* The operation had insufficient
|
||||
* resources to complete and should be
|
||||
* retried
|
||||
*/
|
||||
#define EV_ENOMEM 5 /* There was insufficient memory to
|
||||
* complete the operation */
|
||||
#define EV_EFAULT 6 /* Bad guest address */
|
||||
#define EV_ENODEV 7 /* No such device */
|
||||
#define EV_EINVAL 8 /* An argument supplied to the hcall
|
||||
was out of range or invalid */
|
||||
#define EV_INTERNAL 9 /* An internal error occured */
|
||||
#define EV_CONFIG 10 /* A configuration error was detected */
|
||||
#define EV_INVALID_STATE 11 /* The object is in an invalid state */
|
||||
#define EV_UNIMPLEMENTED 12 /* Unimplemented hypercall */
|
||||
#define EV_BUFFER_OVERFLOW 13 /* Caller-supplied buffer too small */
|
||||
|
||||
/*
|
||||
* Hypercall register clobber list
|
||||
*
|
||||
* These macros are used to define the list of clobbered registers during a
|
||||
* hypercall. Technically, registers r0 and r3-r12 are always clobbered,
|
||||
* but the gcc inline assembly syntax does not allow us to specify registers
|
||||
* on the clobber list that are also on the input/output list. Therefore,
|
||||
* the lists of clobbered registers depends on the number of register
|
||||
* parmeters ("+r" and "=r") passed to the hypercall.
|
||||
*
|
||||
* Each assembly block should use one of the HCALL_CLOBBERSx macros. As a
|
||||
* general rule, 'x' is the number of parameters passed to the assembly
|
||||
* block *except* for r11.
|
||||
*
|
||||
* If you're not sure, just use the smallest value of 'x' that does not
|
||||
* generate a compilation error. Because these are static inline functions,
|
||||
* the compiler will only check the clobber list for a function if you
|
||||
* compile code that calls that function.
|
||||
*
|
||||
* r3 and r11 are not included in any clobbers list because they are always
|
||||
* listed as output registers.
|
||||
*
|
||||
* XER, CTR, and LR are currently listed as clobbers because it's uncertain
|
||||
* whether they will be clobbered.
|
||||
*
|
||||
* Note that r11 can be used as an output parameter.
|
||||
*/
|
||||
|
||||
/* List of common clobbered registers. Do not use this macro. */
|
||||
#define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc"
|
||||
|
||||
#define EV_HCALL_CLOBBERS8 EV_HCALL_CLOBBERS
|
||||
#define EV_HCALL_CLOBBERS7 EV_HCALL_CLOBBERS8, "r10"
|
||||
#define EV_HCALL_CLOBBERS6 EV_HCALL_CLOBBERS7, "r9"
|
||||
#define EV_HCALL_CLOBBERS5 EV_HCALL_CLOBBERS6, "r8"
|
||||
#define EV_HCALL_CLOBBERS4 EV_HCALL_CLOBBERS5, "r7"
|
||||
#define EV_HCALL_CLOBBERS3 EV_HCALL_CLOBBERS4, "r6"
|
||||
#define EV_HCALL_CLOBBERS2 EV_HCALL_CLOBBERS3, "r5"
|
||||
#define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4"
|
||||
|
||||
|
||||
/*
|
||||
* We use "uintptr_t" to define a register because it's guaranteed to be a
|
||||
* 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit
|
||||
* platform.
|
||||
*
|
||||
* All registers are either input/output or output only. Registers that are
|
||||
* initialized before making the hypercall are input/output. All
|
||||
* input/output registers are represented with "+r". Output-only registers
|
||||
* are represented with "=r". Do not specify any unused registers. The
|
||||
* clobber list will tell the compiler that the hypercall modifies those
|
||||
* registers, which is good enough.
|
||||
*/
|
||||
|
||||
/**
|
||||
* ev_int_set_config - configure the specified interrupt
|
||||
* @interrupt: the interrupt number
|
||||
* @config: configuration for this interrupt
|
||||
* @priority: interrupt priority
|
||||
* @destination: destination CPU number
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_int_set_config(unsigned int interrupt,
|
||||
uint32_t config, unsigned int priority, uint32_t destination)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
register uintptr_t r5 __asm__("r5");
|
||||
register uintptr_t r6 __asm__("r6");
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_INT_SET_CONFIG);
|
||||
r3 = interrupt;
|
||||
r4 = config;
|
||||
r5 = priority;
|
||||
r6 = destination;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6)
|
||||
: : EV_HCALL_CLOBBERS4
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* ev_int_get_config - return the config of the specified interrupt
|
||||
* @interrupt: the interrupt number
|
||||
* @config: returned configuration for this interrupt
|
||||
* @priority: returned interrupt priority
|
||||
* @destination: returned destination CPU number
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_int_get_config(unsigned int interrupt,
|
||||
uint32_t *config, unsigned int *priority, uint32_t *destination)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
register uintptr_t r5 __asm__("r5");
|
||||
register uintptr_t r6 __asm__("r6");
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_INT_GET_CONFIG);
|
||||
r3 = interrupt;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5), "=r" (r6)
|
||||
: : EV_HCALL_CLOBBERS4
|
||||
);
|
||||
|
||||
*config = r4;
|
||||
*priority = r5;
|
||||
*destination = r6;
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* ev_int_set_mask - sets the mask for the specified interrupt source
|
||||
* @interrupt: the interrupt number
|
||||
* @mask: 0=enable interrupts, 1=disable interrupts
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_int_set_mask(unsigned int interrupt,
|
||||
unsigned int mask)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_INT_SET_MASK);
|
||||
r3 = interrupt;
|
||||
r4 = mask;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "+r" (r4)
|
||||
: : EV_HCALL_CLOBBERS2
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* ev_int_get_mask - returns the mask for the specified interrupt source
|
||||
* @interrupt: the interrupt number
|
||||
* @mask: returned mask for this interrupt (0=enabled, 1=disabled)
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_int_get_mask(unsigned int interrupt,
|
||||
unsigned int *mask)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_INT_GET_MASK);
|
||||
r3 = interrupt;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "=r" (r4)
|
||||
: : EV_HCALL_CLOBBERS2
|
||||
);
|
||||
|
||||
*mask = r4;
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* ev_int_eoi - signal the end of interrupt processing
|
||||
* @interrupt: the interrupt number
|
||||
*
|
||||
* This function signals the end of processing for the the specified
|
||||
* interrupt, which must be the interrupt currently in service. By
|
||||
* definition, this is also the highest-priority interrupt.
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_int_eoi(unsigned int interrupt)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_INT_EOI);
|
||||
r3 = interrupt;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* ev_byte_channel_send - send characters to a byte stream
|
||||
* @handle: byte stream handle
|
||||
* @count: (input) num of chars to send, (output) num chars sent
|
||||
* @buffer: pointer to a 16-byte buffer
|
||||
*
|
||||
* @buffer must be at least 16 bytes long, because all 16 bytes will be
|
||||
* read from memory into registers, even if count < 16.
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_byte_channel_send(unsigned int handle,
|
||||
unsigned int *count, const char buffer[EV_BYTE_CHANNEL_MAX_BYTES])
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
register uintptr_t r5 __asm__("r5");
|
||||
register uintptr_t r6 __asm__("r6");
|
||||
register uintptr_t r7 __asm__("r7");
|
||||
register uintptr_t r8 __asm__("r8");
|
||||
const uint32_t *p = (const uint32_t *) buffer;
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_SEND);
|
||||
r3 = handle;
|
||||
r4 = *count;
|
||||
r5 = be32_to_cpu(p[0]);
|
||||
r6 = be32_to_cpu(p[1]);
|
||||
r7 = be32_to_cpu(p[2]);
|
||||
r8 = be32_to_cpu(p[3]);
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3),
|
||||
"+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), "+r" (r8)
|
||||
: : EV_HCALL_CLOBBERS6
|
||||
);
|
||||
|
||||
*count = r4;
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* ev_byte_channel_receive - fetch characters from a byte channel
|
||||
* @handle: byte channel handle
|
||||
* @count: (input) max num of chars to receive, (output) num chars received
|
||||
* @buffer: pointer to a 16-byte buffer
|
||||
*
|
||||
* The size of @buffer must be at least 16 bytes, even if you request fewer
|
||||
* than 16 characters, because we always write 16 bytes to @buffer. This is
|
||||
* for performance reasons.
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_byte_channel_receive(unsigned int handle,
|
||||
unsigned int *count, char buffer[EV_BYTE_CHANNEL_MAX_BYTES])
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
register uintptr_t r5 __asm__("r5");
|
||||
register uintptr_t r6 __asm__("r6");
|
||||
register uintptr_t r7 __asm__("r7");
|
||||
register uintptr_t r8 __asm__("r8");
|
||||
uint32_t *p = (uint32_t *) buffer;
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_RECEIVE);
|
||||
r3 = handle;
|
||||
r4 = *count;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "+r" (r4),
|
||||
"=r" (r5), "=r" (r6), "=r" (r7), "=r" (r8)
|
||||
: : EV_HCALL_CLOBBERS6
|
||||
);
|
||||
|
||||
*count = r4;
|
||||
p[0] = cpu_to_be32(r5);
|
||||
p[1] = cpu_to_be32(r6);
|
||||
p[2] = cpu_to_be32(r7);
|
||||
p[3] = cpu_to_be32(r8);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* ev_byte_channel_poll - returns the status of the byte channel buffers
|
||||
* @handle: byte channel handle
|
||||
* @rx_count: returned count of bytes in receive queue
|
||||
* @tx_count: returned count of free space in transmit queue
|
||||
*
|
||||
* This function reports the amount of data in the receive queue (i.e. the
|
||||
* number of bytes you can read), and the amount of free space in the transmit
|
||||
* queue (i.e. the number of bytes you can write).
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_byte_channel_poll(unsigned int handle,
|
||||
unsigned int *rx_count, unsigned int *tx_count)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
register uintptr_t r5 __asm__("r5");
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_POLL);
|
||||
r3 = handle;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5)
|
||||
: : EV_HCALL_CLOBBERS3
|
||||
);
|
||||
|
||||
*rx_count = r4;
|
||||
*tx_count = r5;
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* ev_int_iack - acknowledge an interrupt
|
||||
* @handle: handle to the target interrupt controller
|
||||
* @vector: returned interrupt vector
|
||||
*
|
||||
* If handle is zero, the function returns the next interrupt source
|
||||
* number to be handled irrespective of the hierarchy or cascading
|
||||
* of interrupt controllers. If non-zero, specifies a handle to the
|
||||
* interrupt controller that is the target of the acknowledge.
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_int_iack(unsigned int handle,
|
||||
unsigned int *vector)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_INT_IACK);
|
||||
r3 = handle;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "=r" (r4)
|
||||
: : EV_HCALL_CLOBBERS2
|
||||
);
|
||||
|
||||
*vector = r4;
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* ev_doorbell_send - send a doorbell to another partition
|
||||
* @handle: doorbell send handle
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_doorbell_send(unsigned int handle)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_DOORBELL_SEND);
|
||||
r3 = handle;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* ev_idle -- wait for next interrupt on this core
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int ev_idle(void)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = EV_HCALL_TOKEN(EV_IDLE);
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "=r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -48,30 +48,33 @@
|
|||
#define EX_R14 (4 * 8)
|
||||
#define EX_R15 (5 * 8)
|
||||
|
||||
/* The TLB miss exception uses different slots */
|
||||
/*
|
||||
* The TLB miss exception uses different slots.
|
||||
*
|
||||
* The bolted variant uses only the first six fields,
|
||||
* which in combination with pgd and kernel_pgd fits in
|
||||
* one 64-byte cache line.
|
||||
*/
|
||||
|
||||
#define EX_TLB_R10 ( 0 * 8)
|
||||
#define EX_TLB_R11 ( 1 * 8)
|
||||
#define EX_TLB_R12 ( 2 * 8)
|
||||
#define EX_TLB_R13 ( 3 * 8)
|
||||
#define EX_TLB_R14 ( 4 * 8)
|
||||
#define EX_TLB_R15 ( 5 * 8)
|
||||
#define EX_TLB_R16 ( 6 * 8)
|
||||
#define EX_TLB_CR ( 7 * 8)
|
||||
#define EX_TLB_R14 ( 2 * 8)
|
||||
#define EX_TLB_R15 ( 3 * 8)
|
||||
#define EX_TLB_R16 ( 4 * 8)
|
||||
#define EX_TLB_CR ( 5 * 8)
|
||||
#define EX_TLB_R12 ( 6 * 8)
|
||||
#define EX_TLB_R13 ( 7 * 8)
|
||||
#define EX_TLB_DEAR ( 8 * 8) /* Level 0 and 2 only */
|
||||
#define EX_TLB_ESR ( 9 * 8) /* Level 0 and 2 only */
|
||||
#define EX_TLB_SRR0 (10 * 8)
|
||||
#define EX_TLB_SRR1 (11 * 8)
|
||||
#define EX_TLB_MMUCR0 (12 * 8) /* Level 0 */
|
||||
#define EX_TLB_MAS1 (12 * 8) /* Level 0 */
|
||||
#define EX_TLB_MAS2 (13 * 8) /* Level 0 */
|
||||
#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
|
||||
#define EX_TLB_R8 (14 * 8)
|
||||
#define EX_TLB_R9 (15 * 8)
|
||||
#define EX_TLB_LR (16 * 8)
|
||||
#define EX_TLB_SIZE (17 * 8)
|
||||
#define EX_TLB_R8 (12 * 8)
|
||||
#define EX_TLB_R9 (13 * 8)
|
||||
#define EX_TLB_LR (14 * 8)
|
||||
#define EX_TLB_SIZE (15 * 8)
|
||||
#else
|
||||
#define EX_TLB_SIZE (14 * 8)
|
||||
#define EX_TLB_SIZE (12 * 8)
|
||||
#endif
|
||||
|
||||
#define START_EXCEPTION(label) \
|
||||
|
|
@ -168,6 +171,16 @@ exc_##label##_book3e:
|
|||
ld r9,EX_TLB_R9(r12); \
|
||||
ld r8,EX_TLB_R8(r12); \
|
||||
mtlr r16;
|
||||
#define TLB_MISS_PROLOG_STATS_BOLTED \
|
||||
mflr r10; \
|
||||
std r8,PACA_EXTLB+EX_TLB_R8(r13); \
|
||||
std r9,PACA_EXTLB+EX_TLB_R9(r13); \
|
||||
std r10,PACA_EXTLB+EX_TLB_LR(r13);
|
||||
#define TLB_MISS_RESTORE_STATS_BOLTED \
|
||||
ld r16,PACA_EXTLB+EX_TLB_LR(r13); \
|
||||
ld r9,PACA_EXTLB+EX_TLB_R9(r13); \
|
||||
ld r8,PACA_EXTLB+EX_TLB_R8(r13); \
|
||||
mtlr r16;
|
||||
#define TLB_MISS_STATS_D(name) \
|
||||
addi r9,r13,MMSTAT_DSTATS+name; \
|
||||
bl .tlb_stat_inc;
|
||||
|
|
@ -183,17 +196,20 @@ exc_##label##_book3e:
|
|||
61: addi r9,r13,MMSTAT_ISTATS+name; \
|
||||
62: bl .tlb_stat_inc;
|
||||
#define TLB_MISS_STATS_SAVE_INFO \
|
||||
std r14,EX_TLB_ESR(r12); /* save ESR */ \
|
||||
|
||||
|
||||
std r14,EX_TLB_ESR(r12); /* save ESR */
|
||||
#define TLB_MISS_STATS_SAVE_INFO_BOLTED \
|
||||
std r14,PACA_EXTLB+EX_TLB_ESR(r13); /* save ESR */
|
||||
#else
|
||||
#define TLB_MISS_PROLOG_STATS
|
||||
#define TLB_MISS_RESTORE_STATS
|
||||
#define TLB_MISS_PROLOG_STATS_BOLTED
|
||||
#define TLB_MISS_RESTORE_STATS_BOLTED
|
||||
#define TLB_MISS_STATS_D(name)
|
||||
#define TLB_MISS_STATS_I(name)
|
||||
#define TLB_MISS_STATS_X(name)
|
||||
#define TLB_MISS_STATS_Y(name)
|
||||
#define TLB_MISS_STATS_SAVE_INFO
|
||||
#define TLB_MISS_STATS_SAVE_INFO_BOLTED
|
||||
#endif
|
||||
|
||||
#define SET_IVOR(vector_number, vector_offset) \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,655 @@
|
|||
/*
|
||||
* Freescale hypervisor call interface
|
||||
*
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Timur Tabi <timur@freescale.com>
|
||||
*
|
||||
* This file is provided under a dual BSD/GPL license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_HCALLS_H
|
||||
#define _FSL_HCALLS_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/epapr_hcalls.h>
|
||||
|
||||
#define FH_API_VERSION 1
|
||||
|
||||
#define FH_ERR_GET_INFO 1
|
||||
#define FH_PARTITION_GET_DTPROP 2
|
||||
#define FH_PARTITION_SET_DTPROP 3
|
||||
#define FH_PARTITION_RESTART 4
|
||||
#define FH_PARTITION_GET_STATUS 5
|
||||
#define FH_PARTITION_START 6
|
||||
#define FH_PARTITION_STOP 7
|
||||
#define FH_PARTITION_MEMCPY 8
|
||||
#define FH_DMA_ENABLE 9
|
||||
#define FH_DMA_DISABLE 10
|
||||
#define FH_SEND_NMI 11
|
||||
#define FH_VMPIC_GET_MSIR 12
|
||||
#define FH_SYSTEM_RESET 13
|
||||
#define FH_GET_CORE_STATE 14
|
||||
#define FH_ENTER_NAP 15
|
||||
#define FH_EXIT_NAP 16
|
||||
#define FH_CLAIM_DEVICE 17
|
||||
#define FH_PARTITION_STOP_DMA 18
|
||||
|
||||
/* vendor ID: Freescale Semiconductor */
|
||||
#define FH_HCALL_TOKEN(num) _EV_HCALL_TOKEN(EV_FSL_VENDOR_ID, num)
|
||||
|
||||
/*
|
||||
* We use "uintptr_t" to define a register because it's guaranteed to be a
|
||||
* 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit
|
||||
* platform.
|
||||
*
|
||||
* All registers are either input/output or output only. Registers that are
|
||||
* initialized before making the hypercall are input/output. All
|
||||
* input/output registers are represented with "+r". Output-only registers
|
||||
* are represented with "=r". Do not specify any unused registers. The
|
||||
* clobber list will tell the compiler that the hypercall modifies those
|
||||
* registers, which is good enough.
|
||||
*/
|
||||
|
||||
/**
|
||||
* fh_send_nmi - send NMI to virtual cpu(s).
|
||||
* @vcpu_mask: send NMI to virtual cpu(s) specified by this mask.
|
||||
*
|
||||
* Returns 0 for success, or EINVAL for invalid vcpu_mask.
|
||||
*/
|
||||
static inline unsigned int fh_send_nmi(unsigned int vcpu_mask)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_SEND_NMI);
|
||||
r3 = vcpu_mask;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/* Arbitrary limits to avoid excessive memory allocation in hypervisor */
|
||||
#define FH_DTPROP_MAX_PATHLEN 4096
|
||||
#define FH_DTPROP_MAX_PROPLEN 32768
|
||||
|
||||
/**
|
||||
* fh_partiton_get_dtprop - get a property from a guest device tree.
|
||||
* @handle: handle of partition whose device tree is to be accessed
|
||||
* @dtpath_addr: physical address of device tree path to access
|
||||
* @propname_addr: physical address of name of property
|
||||
* @propvalue_addr: physical address of property value buffer
|
||||
* @propvalue_len: length of buffer on entry, length of property on return
|
||||
*
|
||||
* Returns zero on success, non-zero on error.
|
||||
*/
|
||||
static inline unsigned int fh_partition_get_dtprop(int handle,
|
||||
uint64_t dtpath_addr,
|
||||
uint64_t propname_addr,
|
||||
uint64_t propvalue_addr,
|
||||
uint32_t *propvalue_len)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
register uintptr_t r5 __asm__("r5");
|
||||
register uintptr_t r6 __asm__("r6");
|
||||
register uintptr_t r7 __asm__("r7");
|
||||
register uintptr_t r8 __asm__("r8");
|
||||
register uintptr_t r9 __asm__("r9");
|
||||
register uintptr_t r10 __asm__("r10");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_PARTITION_GET_DTPROP);
|
||||
r3 = handle;
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
r4 = dtpath_addr >> 32;
|
||||
r6 = propname_addr >> 32;
|
||||
r8 = propvalue_addr >> 32;
|
||||
#else
|
||||
r4 = 0;
|
||||
r6 = 0;
|
||||
r8 = 0;
|
||||
#endif
|
||||
r5 = (uint32_t)dtpath_addr;
|
||||
r7 = (uint32_t)propname_addr;
|
||||
r9 = (uint32_t)propvalue_addr;
|
||||
r10 = *propvalue_len;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11),
|
||||
"+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7),
|
||||
"+r" (r8), "+r" (r9), "+r" (r10)
|
||||
: : EV_HCALL_CLOBBERS8
|
||||
);
|
||||
|
||||
*propvalue_len = r4;
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set a property in a guest device tree.
|
||||
* @handle: handle of partition whose device tree is to be accessed
|
||||
* @dtpath_addr: physical address of device tree path to access
|
||||
* @propname_addr: physical address of name of property
|
||||
* @propvalue_addr: physical address of property value
|
||||
* @propvalue_len: length of property
|
||||
*
|
||||
* Returns zero on success, non-zero on error.
|
||||
*/
|
||||
static inline unsigned int fh_partition_set_dtprop(int handle,
|
||||
uint64_t dtpath_addr,
|
||||
uint64_t propname_addr,
|
||||
uint64_t propvalue_addr,
|
||||
uint32_t propvalue_len)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
register uintptr_t r6 __asm__("r6");
|
||||
register uintptr_t r8 __asm__("r8");
|
||||
register uintptr_t r5 __asm__("r5");
|
||||
register uintptr_t r7 __asm__("r7");
|
||||
register uintptr_t r9 __asm__("r9");
|
||||
register uintptr_t r10 __asm__("r10");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_PARTITION_SET_DTPROP);
|
||||
r3 = handle;
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
r4 = dtpath_addr >> 32;
|
||||
r6 = propname_addr >> 32;
|
||||
r8 = propvalue_addr >> 32;
|
||||
#else
|
||||
r4 = 0;
|
||||
r6 = 0;
|
||||
r8 = 0;
|
||||
#endif
|
||||
r5 = (uint32_t)dtpath_addr;
|
||||
r7 = (uint32_t)propname_addr;
|
||||
r9 = (uint32_t)propvalue_addr;
|
||||
r10 = propvalue_len;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11),
|
||||
"+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7),
|
||||
"+r" (r8), "+r" (r9), "+r" (r10)
|
||||
: : EV_HCALL_CLOBBERS8
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* fh_partition_restart - reboot the current partition
|
||||
* @partition: partition ID
|
||||
*
|
||||
* Returns an error code if reboot failed. Does not return if it succeeds.
|
||||
*/
|
||||
static inline unsigned int fh_partition_restart(unsigned int partition)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_PARTITION_RESTART);
|
||||
r3 = partition;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
#define FH_PARTITION_STOPPED 0
|
||||
#define FH_PARTITION_RUNNING 1
|
||||
#define FH_PARTITION_STARTING 2
|
||||
#define FH_PARTITION_STOPPING 3
|
||||
#define FH_PARTITION_PAUSING 4
|
||||
#define FH_PARTITION_PAUSED 5
|
||||
#define FH_PARTITION_RESUMING 6
|
||||
|
||||
/**
|
||||
* fh_partition_get_status - gets the status of a partition
|
||||
* @partition: partition ID
|
||||
* @status: returned status code
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_partition_get_status(unsigned int partition,
|
||||
unsigned int *status)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_PARTITION_GET_STATUS);
|
||||
r3 = partition;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "=r" (r4)
|
||||
: : EV_HCALL_CLOBBERS2
|
||||
);
|
||||
|
||||
*status = r4;
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* fh_partition_start - boots and starts execution of the specified partition
|
||||
* @partition: partition ID
|
||||
* @entry_point: guest physical address to start execution
|
||||
*
|
||||
* The hypervisor creates a 1-to-1 virtual/physical IMA mapping, so at boot
|
||||
* time, guest physical address are the same as guest virtual addresses.
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_partition_start(unsigned int partition,
|
||||
uint32_t entry_point, int load)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
register uintptr_t r5 __asm__("r5");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_PARTITION_START);
|
||||
r3 = partition;
|
||||
r4 = entry_point;
|
||||
r5 = load;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5)
|
||||
: : EV_HCALL_CLOBBERS3
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* fh_partition_stop - stops another partition
|
||||
* @partition: partition ID
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_partition_stop(unsigned int partition)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_PARTITION_STOP);
|
||||
r3 = partition;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* struct fh_sg_list: definition of the fh_partition_memcpy S/G list
|
||||
* @source: guest physical address to copy from
|
||||
* @target: guest physical address to copy to
|
||||
* @size: number of bytes to copy
|
||||
* @reserved: reserved, must be zero
|
||||
*
|
||||
* The scatter/gather list for fh_partition_memcpy() is an array of these
|
||||
* structures. The array must be guest physically contiguous.
|
||||
*
|
||||
* This structure must be aligned on 32-byte boundary, so that no single
|
||||
* strucuture can span two pages.
|
||||
*/
|
||||
struct fh_sg_list {
|
||||
uint64_t source; /**< guest physical address to copy from */
|
||||
uint64_t target; /**< guest physical address to copy to */
|
||||
uint64_t size; /**< number of bytes to copy */
|
||||
uint64_t reserved; /**< reserved, must be zero */
|
||||
} __attribute__ ((aligned(32)));
|
||||
|
||||
/**
|
||||
* fh_partition_memcpy - copies data from one guest to another
|
||||
* @source: the ID of the partition to copy from
|
||||
* @target: the ID of the partition to copy to
|
||||
* @sg_list: guest physical address of an array of &fh_sg_list structures
|
||||
* @count: the number of entries in @sg_list
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_partition_memcpy(unsigned int source,
|
||||
unsigned int target, phys_addr_t sg_list, unsigned int count)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
register uintptr_t r5 __asm__("r5");
|
||||
register uintptr_t r6 __asm__("r6");
|
||||
register uintptr_t r7 __asm__("r7");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_PARTITION_MEMCPY);
|
||||
r3 = source;
|
||||
r4 = target;
|
||||
r5 = (uint32_t) sg_list;
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
r6 = sg_list >> 32;
|
||||
#else
|
||||
r6 = 0;
|
||||
#endif
|
||||
r7 = count;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11),
|
||||
"+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7)
|
||||
: : EV_HCALL_CLOBBERS5
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* fh_dma_enable - enable DMA for the specified device
|
||||
* @liodn: the LIODN of the I/O device for which to enable DMA
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_dma_enable(unsigned int liodn)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_DMA_ENABLE);
|
||||
r3 = liodn;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* fh_dma_disable - disable DMA for the specified device
|
||||
* @liodn: the LIODN of the I/O device for which to disable DMA
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_dma_disable(unsigned int liodn)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_DMA_DISABLE);
|
||||
r3 = liodn;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* fh_vmpic_get_msir - returns the MPIC-MSI register value
|
||||
* @interrupt: the interrupt number
|
||||
* @msir_val: returned MPIC-MSI register value
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_vmpic_get_msir(unsigned int interrupt,
|
||||
unsigned int *msir_val)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_VMPIC_GET_MSIR);
|
||||
r3 = interrupt;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "=r" (r4)
|
||||
: : EV_HCALL_CLOBBERS2
|
||||
);
|
||||
|
||||
*msir_val = r4;
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* fh_system_reset - reset the system
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_system_reset(void)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_SYSTEM_RESET);
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "=r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* fh_err_get_info - get platform error information
|
||||
* @queue id:
|
||||
* 0 for guest error event queue
|
||||
* 1 for global error event queue
|
||||
*
|
||||
* @pointer to store the platform error data:
|
||||
* platform error data is returned in registers r4 - r11
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_err_get_info(int queue, uint32_t *bufsize,
|
||||
uint32_t addr_hi, uint32_t addr_lo, int peek)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
register uintptr_t r5 __asm__("r5");
|
||||
register uintptr_t r6 __asm__("r6");
|
||||
register uintptr_t r7 __asm__("r7");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_ERR_GET_INFO);
|
||||
r3 = queue;
|
||||
r4 = *bufsize;
|
||||
r5 = addr_hi;
|
||||
r6 = addr_lo;
|
||||
r7 = peek;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6),
|
||||
"+r" (r7)
|
||||
: : EV_HCALL_CLOBBERS5
|
||||
);
|
||||
|
||||
*bufsize = r4;
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
|
||||
#define FH_VCPU_RUN 0
|
||||
#define FH_VCPU_IDLE 1
|
||||
#define FH_VCPU_NAP 2
|
||||
|
||||
/**
|
||||
* fh_get_core_state - get the state of a vcpu
|
||||
*
|
||||
* @handle: handle of partition containing the vcpu
|
||||
* @vcpu: vcpu number within the partition
|
||||
* @state:the current state of the vcpu, see FH_VCPU_*
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_get_core_state(unsigned int handle,
|
||||
unsigned int vcpu, unsigned int *state)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_GET_CORE_STATE);
|
||||
r3 = handle;
|
||||
r4 = vcpu;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "+r" (r4)
|
||||
: : EV_HCALL_CLOBBERS2
|
||||
);
|
||||
|
||||
*state = r4;
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* fh_enter_nap - enter nap on a vcpu
|
||||
*
|
||||
* Note that though the API supports entering nap on a vcpu other
|
||||
* than the caller, this may not be implmented and may return EINVAL.
|
||||
*
|
||||
* @handle: handle of partition containing the vcpu
|
||||
* @vcpu: vcpu number within the partition
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_enter_nap(unsigned int handle, unsigned int vcpu)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_ENTER_NAP);
|
||||
r3 = handle;
|
||||
r4 = vcpu;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "+r" (r4)
|
||||
: : EV_HCALL_CLOBBERS2
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* fh_exit_nap - exit nap on a vcpu
|
||||
* @handle: handle of partition containing the vcpu
|
||||
* @vcpu: vcpu number within the partition
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_exit_nap(unsigned int handle, unsigned int vcpu)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
register uintptr_t r4 __asm__("r4");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_EXIT_NAP);
|
||||
r3 = handle;
|
||||
r4 = vcpu;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3), "+r" (r4)
|
||||
: : EV_HCALL_CLOBBERS2
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
/**
|
||||
* fh_claim_device - claim a "claimable" shared device
|
||||
* @handle: fsl,hv-device-handle of node to claim
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_claim_device(unsigned int handle)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_CLAIM_DEVICE);
|
||||
r3 = handle;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
|
||||
/**
|
||||
* Run deferred DMA disabling on a partition's private devices
|
||||
*
|
||||
* This applies to devices which a partition owns either privately,
|
||||
* or which are claimable and still actively owned by that partition,
|
||||
* and which do not have the no-dma-disable property.
|
||||
*
|
||||
* @handle: partition (must be stopped) whose DMA is to be disabled
|
||||
*
|
||||
* Returns 0 for success, or an error code.
|
||||
*/
|
||||
static inline unsigned int fh_partition_stop_dma(unsigned int handle)
|
||||
{
|
||||
register uintptr_t r11 __asm__("r11");
|
||||
register uintptr_t r3 __asm__("r3");
|
||||
|
||||
r11 = FH_HCALL_TOKEN(FH_PARTITION_STOP_DMA);
|
||||
r3 = handle;
|
||||
|
||||
__asm__ __volatile__ ("sc 1"
|
||||
: "+r" (r11), "+r" (r3)
|
||||
: : EV_HCALL_CLOBBERS1
|
||||
);
|
||||
|
||||
return r3;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
#ifndef _HVSI_H
|
||||
#define _HVSI_H
|
||||
|
||||
#define VS_DATA_PACKET_HEADER 0xff
|
||||
#define VS_CONTROL_PACKET_HEADER 0xfe
|
||||
#define VS_QUERY_PACKET_HEADER 0xfd
|
||||
#define VS_QUERY_RESPONSE_PACKET_HEADER 0xfc
|
||||
|
||||
/* control verbs */
|
||||
#define VSV_SET_MODEM_CTL 1 /* to service processor only */
|
||||
#define VSV_MODEM_CTL_UPDATE 2 /* from service processor only */
|
||||
#define VSV_CLOSE_PROTOCOL 3
|
||||
|
||||
/* query verbs */
|
||||
#define VSV_SEND_VERSION_NUMBER 1
|
||||
#define VSV_SEND_MODEM_CTL_STATUS 2
|
||||
|
||||
/* yes, these masks are not consecutive. */
|
||||
#define HVSI_TSDTR 0x01
|
||||
#define HVSI_TSCD 0x20
|
||||
|
||||
#define HVSI_MAX_OUTGOING_DATA 12
|
||||
#define HVSI_VERSION 1
|
||||
|
||||
struct hvsi_header {
|
||||
uint8_t type;
|
||||
uint8_t len;
|
||||
uint16_t seqno;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct hvsi_data {
|
||||
struct hvsi_header hdr;
|
||||
uint8_t data[HVSI_MAX_OUTGOING_DATA];
|
||||
} __attribute__((packed));
|
||||
|
||||
struct hvsi_control {
|
||||
struct hvsi_header hdr;
|
||||
uint16_t verb;
|
||||
/* optional depending on verb: */
|
||||
uint32_t word;
|
||||
uint32_t mask;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct hvsi_query {
|
||||
struct hvsi_header hdr;
|
||||
uint16_t verb;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct hvsi_query_response {
|
||||
struct hvsi_header hdr;
|
||||
uint16_t verb;
|
||||
uint16_t query_seqno;
|
||||
union {
|
||||
uint8_t version;
|
||||
uint32_t mctrl_word;
|
||||
} u;
|
||||
} __attribute__((packed));
|
||||
|
||||
/* hvsi lib struct definitions */
|
||||
#define HVSI_INBUF_SIZE 255
|
||||
struct tty_struct;
|
||||
struct hvsi_priv {
|
||||
unsigned int inbuf_len; /* data in input buffer */
|
||||
unsigned char inbuf[HVSI_INBUF_SIZE];
|
||||
unsigned int inbuf_cur; /* Cursor in input buffer */
|
||||
unsigned int inbuf_pktlen; /* packet lenght from cursor */
|
||||
atomic_t seqno; /* packet sequence number */
|
||||
unsigned int opened:1; /* driver opened */
|
||||
unsigned int established:1; /* protocol established */
|
||||
unsigned int is_console:1; /* used as a kernel console device */
|
||||
unsigned int mctrl_update:1; /* modem control updated */
|
||||
unsigned short mctrl; /* modem control */
|
||||
struct tty_struct *tty; /* tty structure */
|
||||
int (*get_chars)(uint32_t termno, char *buf, int count);
|
||||
int (*put_chars)(uint32_t termno, const char *buf, int count);
|
||||
uint32_t termno;
|
||||
};
|
||||
|
||||
/* hvsi lib functions */
|
||||
struct hvc_struct;
|
||||
extern void hvsilib_init(struct hvsi_priv *pv,
|
||||
int (*get_chars)(uint32_t termno, char *buf, int count),
|
||||
int (*put_chars)(uint32_t termno, const char *buf,
|
||||
int count),
|
||||
int termno, int is_console);
|
||||
extern int hvsilib_open(struct hvsi_priv *pv, struct hvc_struct *hp);
|
||||
extern void hvsilib_close(struct hvsi_priv *pv, struct hvc_struct *hp);
|
||||
extern int hvsilib_read_mctrl(struct hvsi_priv *pv);
|
||||
extern int hvsilib_write_mctrl(struct hvsi_priv *pv, int dtr);
|
||||
extern void hvsilib_establish(struct hvsi_priv *pv);
|
||||
extern int hvsilib_get_chars(struct hvsi_priv *pv, char *buf, int count);
|
||||
extern int hvsilib_put_chars(struct hvsi_priv *pv, const char *buf, int count);
|
||||
|
||||
#endif /* _HVSI_H */
|
||||
|
|
@ -330,5 +330,7 @@ extern int call_handle_irq(int irq, void *p1,
|
|||
struct thread_info *tp, void *func);
|
||||
extern void do_IRQ(struct pt_regs *regs);
|
||||
|
||||
int irq_choose_cpu(const struct cpumask *mask);
|
||||
|
||||
#endif /* _ASM_IRQ_H */
|
||||
#endif /* __KERNEL__ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,47 @@
|
|||
#ifndef _ASM_POWERPC_JUMP_LABEL_H
|
||||
#define _ASM_POWERPC_JUMP_LABEL_H
|
||||
|
||||
/*
|
||||
* Copyright 2010 Michael Ellerman, IBM Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/feature-fixups.h>
|
||||
|
||||
#define JUMP_ENTRY_TYPE stringify_in_c(FTR_ENTRY_LONG)
|
||||
#define JUMP_LABEL_NOP_SIZE 4
|
||||
|
||||
static __always_inline bool arch_static_branch(struct jump_label_key *key)
|
||||
{
|
||||
asm goto("1:\n\t"
|
||||
"nop\n\t"
|
||||
".pushsection __jump_table, \"aw\"\n\t"
|
||||
".align 4\n\t"
|
||||
JUMP_ENTRY_TYPE "1b, %l[l_yes], %c0\n\t"
|
||||
".popsection \n\t"
|
||||
: : "i" (key) : : l_yes);
|
||||
return false;
|
||||
l_yes:
|
||||
return true;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC64
|
||||
typedef u64 jump_label_t;
|
||||
#else
|
||||
typedef u32 jump_label_t;
|
||||
#endif
|
||||
|
||||
struct jump_entry {
|
||||
jump_label_t code;
|
||||
jump_label_t target;
|
||||
jump_label_t key;
|
||||
jump_label_t pad;
|
||||
};
|
||||
|
||||
#endif /* _ASM_POWERPC_JUMP_LABEL_H */
|
||||
|
|
@ -115,14 +115,24 @@
|
|||
#ifndef __ASSEMBLY__
|
||||
#include <asm/cputable.h>
|
||||
|
||||
#ifdef CONFIG_PPC_FSL_BOOK3E
|
||||
#include <asm/percpu.h>
|
||||
DECLARE_PER_CPU(int, next_tlbcam_idx);
|
||||
#endif
|
||||
|
||||
static inline int mmu_has_feature(unsigned long feature)
|
||||
{
|
||||
return (cur_cpu_spec->mmu_features & feature);
|
||||
}
|
||||
|
||||
static inline void mmu_clear_feature(unsigned long feature)
|
||||
{
|
||||
cur_cpu_spec->mmu_features &= ~feature;
|
||||
}
|
||||
|
||||
extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
|
||||
|
||||
/* MMU initialization (64-bit only fo now) */
|
||||
/* MMU initialization */
|
||||
extern void early_init_mmu(void);
|
||||
extern void early_init_mmu_secondary(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
#ifdef CONFIG_PPC_PSERIES
|
||||
extern int pSeries_reconfig_notifier_register(struct notifier_block *);
|
||||
extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
|
||||
extern struct blocking_notifier_head pSeries_reconfig_chain;
|
||||
extern int pSeries_reconfig_notify(unsigned long action, void *p);
|
||||
/* Not the best place to put this, will be fixed when we move some
|
||||
* of the rtas suspend-me stuff to pseries */
|
||||
extern void pSeries_coalesce_init(void);
|
||||
|
|
|
|||
|
|
@ -103,11 +103,12 @@ struct paca_struct {
|
|||
#endif /* CONFIG_PPC_STD_MMU_64 */
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3E
|
||||
pgd_t *pgd; /* Current PGD */
|
||||
pgd_t *kernel_pgd; /* Kernel PGD */
|
||||
u64 exgen[8] __attribute__((aligned(0x80)));
|
||||
/* Keep pgd in the same cacheline as the start of extlb */
|
||||
pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
|
||||
pgd_t *kernel_pgd; /* Kernel PGD */
|
||||
/* We can have up to 3 levels of reentrancy in the TLB miss handler */
|
||||
u64 extlb[3][EX_TLB_SIZE / sizeof(u64)] __attribute__((aligned(0x80)));
|
||||
u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
|
||||
u64 exmc[8]; /* used for machine checks */
|
||||
u64 excrit[8]; /* used for crit interrupts */
|
||||
u64 exdbg[8]; /* used for debug interrupts */
|
||||
|
|
|
|||
|
|
@ -357,7 +357,8 @@ void pgtable_cache_init(void);
|
|||
/*
|
||||
* find_linux_pte returns the address of a linux pte for a given
|
||||
* effective address and directory. If not found, it returns zero.
|
||||
*/static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
|
||||
*/
|
||||
static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
|
||||
{
|
||||
pgd_t *pg;
|
||||
pud_t *pu;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/cache.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/types.h>
|
||||
|
||||
|
|
@ -156,6 +157,10 @@ struct thread_struct {
|
|||
#endif
|
||||
struct pt_regs *regs; /* Pointer to saved register state */
|
||||
mm_segment_t fs; /* for get_fs() validation */
|
||||
#ifdef CONFIG_BOOKE
|
||||
/* BookE base exception scratch space; align on cacheline */
|
||||
unsigned long normsave[8] ____cacheline_aligned;
|
||||
#endif
|
||||
#ifdef CONFIG_PPC32
|
||||
void *pgdir; /* root of page-table tree */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -889,8 +889,8 @@
|
|||
#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
|
||||
#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
|
||||
#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
|
||||
#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG6R
|
||||
#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG6W
|
||||
#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
|
||||
#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
|
||||
#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
|
||||
#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
|
||||
#ifdef CONFIG_E200
|
||||
|
|
|
|||
|
|
@ -3,4 +3,8 @@
|
|||
|
||||
#include <asm-generic/setup.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void ppc_printk_progress(char *s, unsigned short hex);
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_POWERPC_SETUP_H */
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
#include <asm/percpu.h>
|
||||
|
||||
extern int boot_cpuid;
|
||||
extern int boot_cpu_count;
|
||||
extern int spinning_secondaries;
|
||||
|
||||
extern void cpu_die(void);
|
||||
|
||||
|
|
@ -119,7 +119,6 @@ extern const char *smp_ipi_name[];
|
|||
/* for irq controllers with only a single ipi */
|
||||
extern void smp_muxed_ipi_set_data(int cpu, unsigned long data);
|
||||
extern void smp_muxed_ipi_message_pass(int cpu, int msg);
|
||||
extern void smp_muxed_ipi_resend(void);
|
||||
extern irqreturn_t smp_ipi_demux(void);
|
||||
|
||||
void smp_init_iSeries(void);
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ extern void udbg_adb_init_early(void);
|
|||
|
||||
extern void __init udbg_early_init(void);
|
||||
extern void __init udbg_init_debug_lpar(void);
|
||||
extern void __init udbg_init_debug_lpar_hvsi(void);
|
||||
extern void __init udbg_init_pmac_realmode(void);
|
||||
extern void __init udbg_init_maple_realmode(void);
|
||||
extern void __init udbg_init_pas_realmode(void);
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o
|
|||
obj-$(CONFIG_44x) += cpu_setup_44x.o
|
||||
obj-$(CONFIG_PPC_FSL_BOOK3E) += cpu_setup_fsl_booke.o dbell.o
|
||||
obj-$(CONFIG_PPC_BOOK3E_64) += dbell.o
|
||||
obj-$(CONFIG_JUMP_LABEL) += jump_label.o
|
||||
|
||||
extra-y := head_$(CONFIG_WORD_SIZE).o
|
||||
extra-$(CONFIG_40x) := head_40x.o
|
||||
|
|
|
|||
|
|
@ -82,6 +82,9 @@ int main(void)
|
|||
DEFINE(KSP, offsetof(struct thread_struct, ksp));
|
||||
DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
|
||||
DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
|
||||
#ifdef CONFIG_BOOKE
|
||||
DEFINE(THREAD_NORMSAVES, offsetof(struct thread_struct, normsave[0]));
|
||||
#endif
|
||||
DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode));
|
||||
DEFINE(THREAD_FPR0, offsetof(struct thread_struct, fpr[0]));
|
||||
DEFINE(THREAD_FPSCR, offsetof(struct thread_struct, fpscr));
|
||||
|
|
|
|||
|
|
@ -242,12 +242,8 @@ static void crash_kexec_wait_realmode(int cpu)
|
|||
|
||||
while (paca[i].kexec_state < KEXEC_STATE_REAL_MODE) {
|
||||
barrier();
|
||||
if (!cpu_possible(i)) {
|
||||
if (!cpu_possible(i) || !cpu_online(i) || (msecs <= 0))
|
||||
break;
|
||||
}
|
||||
if (!cpu_online(i)) {
|
||||
break;
|
||||
}
|
||||
msecs--;
|
||||
mdelay(1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -161,9 +161,7 @@ int dma_set_mask(struct device *dev, u64 dma_mask)
|
|||
|
||||
if (ppc_md.dma_set_mask)
|
||||
return ppc_md.dma_set_mask(dev, dma_mask);
|
||||
if (unlikely(dma_ops == NULL))
|
||||
return -EIO;
|
||||
if (dma_ops->set_dma_mask != NULL)
|
||||
if ((dma_ops != NULL) && (dma_ops->set_dma_mask != NULL))
|
||||
return dma_ops->set_dma_mask(dev, dma_mask);
|
||||
if (!dev->dma_mask || !dma_supported(dev, dma_mask))
|
||||
return -EIO;
|
||||
|
|
|
|||
|
|
@ -120,6 +120,12 @@
|
|||
std r14,PACA_EXMC+EX_R14(r13); \
|
||||
std r15,PACA_EXMC+EX_R15(r13)
|
||||
|
||||
#define PROLOG_ADDITION_DOORBELL_GEN \
|
||||
lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
|
||||
cmpwi cr0,r11,0; /* yes -> go out of line */ \
|
||||
beq masked_doorbell_book3e
|
||||
|
||||
|
||||
/* Core exception code for all exceptions except TLB misses.
|
||||
* XXX: Needs to make SPRN_SPRG_GEN depend on exception type
|
||||
*/
|
||||
|
|
@ -522,7 +528,13 @@ kernel_dbg_exc:
|
|||
MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE)
|
||||
|
||||
/* Doorbell interrupt */
|
||||
MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE)
|
||||
START_EXCEPTION(doorbell)
|
||||
NORMAL_EXCEPTION_PROLOG(0x2070, PROLOG_ADDITION_DOORBELL)
|
||||
EXCEPTION_COMMON(0x2070, PACA_EXGEN, INTS_DISABLE_ALL)
|
||||
CHECK_NAPPING()
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl .doorbell_exception
|
||||
b .ret_from_except_lite
|
||||
|
||||
/* Doorbell critical Interrupt */
|
||||
START_EXCEPTION(doorbell_crit);
|
||||
|
|
@ -545,8 +557,16 @@ kernel_dbg_exc:
|
|||
* An interrupt came in while soft-disabled; clear EE in SRR1,
|
||||
* clear paca->hard_enabled and return.
|
||||
*/
|
||||
masked_doorbell_book3e:
|
||||
mtcr r10
|
||||
/* Resend the doorbell to fire again when ints enabled */
|
||||
mfspr r10,SPRN_PIR
|
||||
PPC_MSGSND(r10)
|
||||
b masked_interrupt_book3e_common
|
||||
|
||||
masked_interrupt_book3e:
|
||||
mtcr r10
|
||||
masked_interrupt_book3e_common:
|
||||
stb r11,PACAHARDIRQEN(r13)
|
||||
mfspr r10,SPRN_SRR1
|
||||
rldicl r11,r10,48,1 /* clear MSR_EE */
|
||||
|
|
|
|||
|
|
@ -93,6 +93,30 @@ _ENTRY(_start);
|
|||
|
||||
bl early_init
|
||||
|
||||
#ifdef CONFIG_RELOCATABLE
|
||||
/*
|
||||
* r25 will contain RPN/ERPN for the start address of memory
|
||||
*
|
||||
* Add the difference between KERNELBASE and PAGE_OFFSET to the
|
||||
* start of physical memory to get kernstart_addr.
|
||||
*/
|
||||
lis r3,kernstart_addr@ha
|
||||
la r3,kernstart_addr@l(r3)
|
||||
|
||||
lis r4,KERNELBASE@h
|
||||
ori r4,r4,KERNELBASE@l
|
||||
lis r5,PAGE_OFFSET@h
|
||||
ori r5,r5,PAGE_OFFSET@l
|
||||
subf r4,r5,r4
|
||||
|
||||
rlwinm r6,r25,0,28,31 /* ERPN */
|
||||
rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
|
||||
add r7,r7,r4
|
||||
|
||||
stw r6,0(r3)
|
||||
stw r7,4(r3)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Decide what sort of machine this is and initialize the MMU.
|
||||
*/
|
||||
|
|
@ -1001,9 +1025,6 @@ clear_utlb_entry:
|
|||
lis r3,PAGE_OFFSET@h
|
||||
ori r3,r3,PAGE_OFFSET@l
|
||||
|
||||
/* Kernel is at the base of RAM */
|
||||
li r4, 0 /* Load the kernel physical address */
|
||||
|
||||
/* Load the kernel PID = 0 */
|
||||
li r0,0
|
||||
mtspr SPRN_PID,r0
|
||||
|
|
@ -1013,9 +1034,8 @@ clear_utlb_entry:
|
|||
clrrwi r3,r3,12 /* Mask off the effective page number */
|
||||
ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M
|
||||
|
||||
/* Word 1 */
|
||||
clrrwi r4,r4,12 /* Mask off the real page number */
|
||||
/* ERPN is 0 for first 4GB page */
|
||||
/* Word 1 - use r25. RPN is the same as the original entry */
|
||||
|
||||
/* Word 2 */
|
||||
li r5,0
|
||||
ori r5,r5,PPC47x_TLB2_S_RWX
|
||||
|
|
@ -1026,7 +1046,7 @@ clear_utlb_entry:
|
|||
/* We write to way 0 and bolted 0 */
|
||||
lis r0,0x8800
|
||||
tlbwe r3,r0,0
|
||||
tlbwe r4,r0,1
|
||||
tlbwe r25,r0,1
|
||||
tlbwe r5,r0,2
|
||||
|
||||
/*
|
||||
|
|
@ -1124,7 +1144,13 @@ head_start_common:
|
|||
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
|
||||
mtspr SPRN_IVPR,r4
|
||||
|
||||
addis r22,r22,KERNELBASE@h
|
||||
/*
|
||||
* If the kernel was loaded at a non-zero 256 MB page, we need to
|
||||
* mask off the most significant 4 bits to get the relative address
|
||||
* from the start of physical memory
|
||||
*/
|
||||
rlwinm r22,r22,0,4,31
|
||||
addis r22,r22,PAGE_OFFSET@h
|
||||
mtlr r22
|
||||
isync
|
||||
blr
|
||||
|
|
|
|||
|
|
@ -255,7 +255,7 @@ generic_secondary_common_init:
|
|||
mtctr r23
|
||||
bctrl
|
||||
|
||||
3: LOAD_REG_ADDR(r3, boot_cpu_count) /* Decrement boot_cpu_count */
|
||||
3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
|
||||
lwarx r4,0,r3
|
||||
subi r4,r4,1
|
||||
stwcx. r4,0,r3
|
||||
|
|
|
|||
|
|
@ -20,33 +20,43 @@
|
|||
addi reg,reg,val@l
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macro used to get to thread save registers.
|
||||
* Note that entries 0-3 are used for the prolog code, and the remaining
|
||||
* entries are available for specific exception use in the event a handler
|
||||
* requires more than 4 scratch registers.
|
||||
*/
|
||||
#define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
|
||||
|
||||
#define NORMAL_EXCEPTION_PROLOG \
|
||||
mtspr SPRN_SPRG_WSCRATCH0,r10;/* save two registers to work with */\
|
||||
mtspr SPRN_SPRG_WSCRATCH1,r11; \
|
||||
mtspr SPRN_SPRG_WSCRATCH2,r1; \
|
||||
mfcr r10; /* save CR in r10 for now */\
|
||||
mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
|
||||
mfspr r10, SPRN_SPRG_THREAD; \
|
||||
stw r11, THREAD_NORMSAVE(0)(r10); \
|
||||
stw r13, THREAD_NORMSAVE(2)(r10); \
|
||||
mfcr r13; /* save CR in r13 for now */\
|
||||
mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
|
||||
andi. r11,r11,MSR_PR; \
|
||||
mr r11, r1; \
|
||||
beq 1f; \
|
||||
mfspr r1,SPRN_SPRG_THREAD; /* if from user, start at top of */\
|
||||
lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
|
||||
ALLOC_STACK_FRAME(r1, THREAD_SIZE); \
|
||||
1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
|
||||
mr r11,r1; \
|
||||
stw r10,_CCR(r11); /* save various registers */\
|
||||
/* if from user, start at top of this thread's kernel stack */ \
|
||||
lwz r11, THREAD_INFO-THREAD(r10); \
|
||||
ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
|
||||
1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
|
||||
stw r13, _CCR(r11); /* save various registers */ \
|
||||
stw r12,GPR12(r11); \
|
||||
stw r9,GPR9(r11); \
|
||||
mfspr r10,SPRN_SPRG_RSCRATCH0; \
|
||||
stw r10,GPR10(r11); \
|
||||
mfspr r12,SPRN_SPRG_RSCRATCH1; \
|
||||
mfspr r13, SPRN_SPRG_RSCRATCH0; \
|
||||
stw r13, GPR10(r11); \
|
||||
lwz r12, THREAD_NORMSAVE(0)(r10); \
|
||||
stw r12,GPR11(r11); \
|
||||
lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
|
||||
mflr r10; \
|
||||
stw r10,_LINK(r11); \
|
||||
mfspr r10,SPRN_SPRG_RSCRATCH2; \
|
||||
mfspr r12,SPRN_SRR0; \
|
||||
stw r10,GPR1(r11); \
|
||||
stw r1, GPR1(r11); \
|
||||
mfspr r9,SPRN_SRR1; \
|
||||
stw r10,0(r11); \
|
||||
stw r1, 0(r11); \
|
||||
mr r1, r11; \
|
||||
rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
|
||||
stw r0,GPR0(r11); \
|
||||
lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
|
||||
|
|
|
|||
|
|
@ -346,11 +346,12 @@ interrupt_base:
|
|||
/* Data TLB Error Interrupt */
|
||||
START_EXCEPTION(DataTLBError)
|
||||
mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
|
||||
mtspr SPRN_SPRG_WSCRATCH1, r11
|
||||
mtspr SPRN_SPRG_WSCRATCH2, r12
|
||||
mtspr SPRN_SPRG_WSCRATCH3, r13
|
||||
mfcr r11
|
||||
mtspr SPRN_SPRG_WSCRATCH4, r11
|
||||
mfspr r10, SPRN_SPRG_THREAD
|
||||
stw r11, THREAD_NORMSAVE(0)(r10)
|
||||
stw r12, THREAD_NORMSAVE(1)(r10)
|
||||
stw r13, THREAD_NORMSAVE(2)(r10)
|
||||
mfcr r13
|
||||
stw r13, THREAD_NORMSAVE(3)(r10)
|
||||
mfspr r10, SPRN_DEAR /* Get faulting address */
|
||||
|
||||
/* If we are faulting a kernel address, we have to use the
|
||||
|
|
@ -416,11 +417,12 @@ interrupt_base:
|
|||
/* The bailout. Restore registers to pre-exception conditions
|
||||
* and call the heavyweights to help us out.
|
||||
*/
|
||||
mfspr r11, SPRN_SPRG_RSCRATCH4
|
||||
mfspr r10, SPRN_SPRG_THREAD
|
||||
lwz r11, THREAD_NORMSAVE(3)(r10)
|
||||
mtcr r11
|
||||
mfspr r13, SPRN_SPRG_RSCRATCH3
|
||||
mfspr r12, SPRN_SPRG_RSCRATCH2
|
||||
mfspr r11, SPRN_SPRG_RSCRATCH1
|
||||
lwz r13, THREAD_NORMSAVE(2)(r10)
|
||||
lwz r12, THREAD_NORMSAVE(1)(r10)
|
||||
lwz r11, THREAD_NORMSAVE(0)(r10)
|
||||
mfspr r10, SPRN_SPRG_RSCRATCH0
|
||||
b DataStorage
|
||||
|
||||
|
|
@ -432,11 +434,12 @@ interrupt_base:
|
|||
*/
|
||||
START_EXCEPTION(InstructionTLBError)
|
||||
mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
|
||||
mtspr SPRN_SPRG_WSCRATCH1, r11
|
||||
mtspr SPRN_SPRG_WSCRATCH2, r12
|
||||
mtspr SPRN_SPRG_WSCRATCH3, r13
|
||||
mfcr r11
|
||||
mtspr SPRN_SPRG_WSCRATCH4, r11
|
||||
mfspr r10, SPRN_SPRG_THREAD
|
||||
stw r11, THREAD_NORMSAVE(0)(r10)
|
||||
stw r12, THREAD_NORMSAVE(1)(r10)
|
||||
stw r13, THREAD_NORMSAVE(2)(r10)
|
||||
mfcr r13
|
||||
stw r13, THREAD_NORMSAVE(3)(r10)
|
||||
mfspr r10, SPRN_SRR0 /* Get faulting address */
|
||||
|
||||
/* If we are faulting a kernel address, we have to use the
|
||||
|
|
@ -496,11 +499,12 @@ interrupt_base:
|
|||
/* The bailout. Restore registers to pre-exception conditions
|
||||
* and call the heavyweights to help us out.
|
||||
*/
|
||||
mfspr r11, SPRN_SPRG_RSCRATCH4
|
||||
mfspr r10, SPRN_SPRG_THREAD
|
||||
lwz r11, THREAD_NORMSAVE(3)(r10)
|
||||
mtcr r11
|
||||
mfspr r13, SPRN_SPRG_RSCRATCH3
|
||||
mfspr r12, SPRN_SPRG_RSCRATCH2
|
||||
mfspr r11, SPRN_SPRG_RSCRATCH1
|
||||
lwz r13, THREAD_NORMSAVE(2)(r10)
|
||||
lwz r12, THREAD_NORMSAVE(1)(r10)
|
||||
lwz r11, THREAD_NORMSAVE(0)(r10)
|
||||
mfspr r10, SPRN_SPRG_RSCRATCH0
|
||||
b InstructionStorage
|
||||
|
||||
|
|
@ -621,11 +625,12 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
|
|||
tlbwe
|
||||
|
||||
/* Done...restore registers and get out of here. */
|
||||
mfspr r11, SPRN_SPRG_RSCRATCH4
|
||||
mfspr r10, SPRN_SPRG_THREAD
|
||||
lwz r11, THREAD_NORMSAVE(3)(r10)
|
||||
mtcr r11
|
||||
mfspr r13, SPRN_SPRG_RSCRATCH3
|
||||
mfspr r12, SPRN_SPRG_RSCRATCH2
|
||||
mfspr r11, SPRN_SPRG_RSCRATCH1
|
||||
lwz r13, THREAD_NORMSAVE(2)(r10)
|
||||
lwz r12, THREAD_NORMSAVE(1)(r10)
|
||||
lwz r11, THREAD_NORMSAVE(0)(r10)
|
||||
mfspr r10, SPRN_SPRG_RSCRATCH0
|
||||
rfi /* Force context change */
|
||||
|
||||
|
|
|
|||
|
|
@ -26,6 +26,17 @@ _GLOBAL(e500_idle)
|
|||
ori r4,r4,_TLF_NAPPING /* so when we take an exception */
|
||||
stw r4,TI_LOCAL_FLAGS(r3) /* it will return to our caller */
|
||||
|
||||
#ifdef CONFIG_E500MC
|
||||
wrteei 1
|
||||
1: wait
|
||||
|
||||
/*
|
||||
* Guard against spurious wakeups (e.g. from a hypervisor) --
|
||||
* any real interrupt will cause us to return to LR due to
|
||||
* _TLF_NAPPING.
|
||||
*/
|
||||
b 1b
|
||||
#else
|
||||
/* Check if we can nap or doze, put HID0 mask in r3 */
|
||||
lis r3,0
|
||||
BEGIN_FTR_SECTION
|
||||
|
|
@ -72,6 +83,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
|
|||
mtmsr r7
|
||||
isync
|
||||
2: b 2b
|
||||
#endif /* !E500MC */
|
||||
|
||||
/*
|
||||
* Return from NAP/DOZE mode, restore some CPU specific registers,
|
||||
|
|
|
|||
|
|
@ -157,12 +157,6 @@ notrace void arch_local_irq_restore(unsigned long en)
|
|||
if (get_hard_enabled())
|
||||
return;
|
||||
|
||||
#if defined(CONFIG_BOOKE) && defined(CONFIG_SMP)
|
||||
/* Check for pending doorbell interrupts and resend to ourself */
|
||||
if (cpu_has_feature(CPU_FTR_DBELL))
|
||||
smp_muxed_ipi_resend();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Need to hard-enable interrupts here. Since currently disabled,
|
||||
* no need to take further asm precautions against preemption; but
|
||||
|
|
@ -457,11 +451,18 @@ static inline void do_softirq_onstack(void)
|
|||
curtp = current_thread_info();
|
||||
irqtp = softirq_ctx[smp_processor_id()];
|
||||
irqtp->task = curtp->task;
|
||||
irqtp->flags = 0;
|
||||
current->thread.ksp_limit = (unsigned long)irqtp +
|
||||
_ALIGN_UP(sizeof(struct thread_info), 16);
|
||||
call_do_softirq(irqtp);
|
||||
current->thread.ksp_limit = saved_sp_limit;
|
||||
irqtp->task = NULL;
|
||||
|
||||
/* Set any flag that may have been set on the
|
||||
* alternate stack
|
||||
*/
|
||||
if (irqtp->flags)
|
||||
set_bits(irqtp->flags, &curtp->flags);
|
||||
}
|
||||
|
||||
void do_softirq(void)
|
||||
|
|
@ -750,7 +751,7 @@ unsigned int irq_create_mapping(struct irq_host *host,
|
|||
if (irq_setup_virq(host, virq, hwirq))
|
||||
return NO_IRQ;
|
||||
|
||||
printk(KERN_DEBUG "irq: irq %lu on host %s mapped to virtual irq %u\n",
|
||||
pr_debug("irq: irq %lu on host %s mapped to virtual irq %u\n",
|
||||
hwirq, host->of_node ? host->of_node->full_name : "null", virq);
|
||||
|
||||
return virq;
|
||||
|
|
@ -882,6 +883,41 @@ unsigned int irq_find_mapping(struct irq_host *host,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(irq_find_mapping);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
int irq_choose_cpu(const struct cpumask *mask)
|
||||
{
|
||||
int cpuid;
|
||||
|
||||
if (cpumask_equal(mask, cpu_all_mask)) {
|
||||
static int irq_rover;
|
||||
static DEFINE_RAW_SPINLOCK(irq_rover_lock);
|
||||
unsigned long flags;
|
||||
|
||||
/* Round-robin distribution... */
|
||||
do_round_robin:
|
||||
raw_spin_lock_irqsave(&irq_rover_lock, flags);
|
||||
|
||||
irq_rover = cpumask_next(irq_rover, cpu_online_mask);
|
||||
if (irq_rover >= nr_cpu_ids)
|
||||
irq_rover = cpumask_first(cpu_online_mask);
|
||||
|
||||
cpuid = irq_rover;
|
||||
|
||||
raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
|
||||
} else {
|
||||
cpuid = cpumask_first_and(mask, cpu_online_mask);
|
||||
if (cpuid >= nr_cpu_ids)
|
||||
goto do_round_robin;
|
||||
}
|
||||
|
||||
return get_hard_smp_processor_id(cpuid);
|
||||
}
|
||||
#else
|
||||
int irq_choose_cpu(const struct cpumask *mask)
|
||||
{
|
||||
return hard_smp_processor_id();
|
||||
}
|
||||
#endif
|
||||
|
||||
unsigned int irq_radix_revmap_lookup(struct irq_host *host,
|
||||
irq_hw_number_t hwirq)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2010 Michael Ellerman, IBM Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/jump_label.h>
|
||||
#include <asm/code-patching.h>
|
||||
|
||||
void arch_jump_label_transform(struct jump_entry *entry,
|
||||
enum jump_label_type type)
|
||||
{
|
||||
u32 *addr = (u32 *)(unsigned long)entry->code;
|
||||
|
||||
if (type == JUMP_LABEL_ENABLE)
|
||||
patch_branch(addr, entry->target, 0);
|
||||
else
|
||||
patch_instruction(addr, PPC_INST_NOP);
|
||||
}
|
||||
|
|
@ -339,7 +339,7 @@ _GLOBAL(real_205_writeb)
|
|||
#endif /* CONFIG_PPC_PASEMI */
|
||||
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_PMAC64
|
||||
#if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
|
||||
/*
|
||||
* SCOM access functions for 970 (FX only for now)
|
||||
*
|
||||
|
|
@ -408,7 +408,7 @@ _GLOBAL(scom970_write)
|
|||
/* restore interrupts */
|
||||
mtmsrd r5,1
|
||||
blr
|
||||
#endif /* CONFIG_CPU_FREQ_PMAC64 */
|
||||
#endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
|
||||
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -410,7 +410,7 @@ struct power_pmu mpc7450_pmu = {
|
|||
.cache_events = &mpc7450_cache_events,
|
||||
};
|
||||
|
||||
static int init_mpc7450_pmu(void)
|
||||
static int __init init_mpc7450_pmu(void)
|
||||
{
|
||||
if (!cur_cpu_spec->oprofile_cpu_type ||
|
||||
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450"))
|
||||
|
|
|
|||
|
|
@ -1731,3 +1731,21 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
|
|||
if (mode == PCI_PROBE_NORMAL)
|
||||
hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
|
||||
}
|
||||
|
||||
static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
|
||||
{
|
||||
int i, class = dev->class >> 8;
|
||||
|
||||
if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
|
||||
class == PCI_CLASS_BRIDGE_OTHER) &&
|
||||
(dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
|
||||
(dev->bus->parent == NULL)) {
|
||||
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
||||
dev->resource[i].start = 0;
|
||||
dev->resource[i].end = 0;
|
||||
dev->resource[i].flags = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
|
||||
|
|
|
|||
|
|
@ -50,25 +50,6 @@ static int pci_bus_count;
|
|||
struct pci_dev *isa_bridge_pcidev;
|
||||
EXPORT_SYMBOL_GPL(isa_bridge_pcidev);
|
||||
|
||||
static void
|
||||
fixup_hide_host_resource_fsl(struct pci_dev *dev)
|
||||
{
|
||||
int i, class = dev->class >> 8;
|
||||
|
||||
if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
|
||||
class == PCI_CLASS_BRIDGE_OTHER) &&
|
||||
(dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
|
||||
(dev->bus->parent == NULL)) {
|
||||
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
||||
dev->resource[i].start = 0;
|
||||
dev->resource[i].end = 0;
|
||||
dev->resource[i].flags = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
|
||||
|
||||
static void
|
||||
fixup_cpc710_pci64(struct pci_dev* dev)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1408,7 +1408,7 @@ power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu
|
|||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
int register_power_pmu(struct power_pmu *pmu)
|
||||
int __cpuinit register_power_pmu(struct power_pmu *pmu)
|
||||
{
|
||||
if (ppmu)
|
||||
return -EBUSY; /* something's already registered */
|
||||
|
|
|
|||
|
|
@ -609,7 +609,7 @@ static struct power_pmu power4_pmu = {
|
|||
.cache_events = &power4_cache_events,
|
||||
};
|
||||
|
||||
static int init_power4_pmu(void)
|
||||
static int __init init_power4_pmu(void)
|
||||
{
|
||||
if (!cur_cpu_spec->oprofile_cpu_type ||
|
||||
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power4"))
|
||||
|
|
|
|||
|
|
@ -677,7 +677,7 @@ static struct power_pmu power5p_pmu = {
|
|||
.cache_events = &power5p_cache_events,
|
||||
};
|
||||
|
||||
static int init_power5p_pmu(void)
|
||||
static int __init init_power5p_pmu(void)
|
||||
{
|
||||
if (!cur_cpu_spec->oprofile_cpu_type ||
|
||||
(strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5+")
|
||||
|
|
|
|||
|
|
@ -617,7 +617,7 @@ static struct power_pmu power5_pmu = {
|
|||
.cache_events = &power5_cache_events,
|
||||
};
|
||||
|
||||
static int init_power5_pmu(void)
|
||||
static int __init init_power5_pmu(void)
|
||||
{
|
||||
if (!cur_cpu_spec->oprofile_cpu_type ||
|
||||
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5"))
|
||||
|
|
|
|||
|
|
@ -540,7 +540,7 @@ static struct power_pmu power6_pmu = {
|
|||
.cache_events = &power6_cache_events,
|
||||
};
|
||||
|
||||
static int init_power6_pmu(void)
|
||||
static int __init init_power6_pmu(void)
|
||||
{
|
||||
if (!cur_cpu_spec->oprofile_cpu_type ||
|
||||
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
|
||||
|
|
|
|||
|
|
@ -365,7 +365,7 @@ static struct power_pmu power7_pmu = {
|
|||
.cache_events = &power7_cache_events,
|
||||
};
|
||||
|
||||
static int init_power7_pmu(void)
|
||||
static int __init init_power7_pmu(void)
|
||||
{
|
||||
if (!cur_cpu_spec->oprofile_cpu_type ||
|
||||
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
|
||||
|
|
|
|||
|
|
@ -489,7 +489,7 @@ static struct power_pmu ppc970_pmu = {
|
|||
.cache_events = &ppc970_cache_events,
|
||||
};
|
||||
|
||||
static int init_ppc970_pmu(void)
|
||||
static int __init init_ppc970_pmu(void)
|
||||
{
|
||||
if (!cur_cpu_spec->oprofile_cpu_type ||
|
||||
(strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970")
|
||||
|
|
|
|||
|
|
@ -654,6 +654,8 @@ void show_regs(struct pt_regs * regs)
|
|||
printbits(regs->msr, msr_bits);
|
||||
printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
|
||||
trap = TRAP(regs);
|
||||
if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
|
||||
printk("CFAR: "REG"\n", regs->orig_gpr3);
|
||||
if (trap == 0x300 || trap == 0x600)
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
|
||||
|
|
@ -835,8 +837,6 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
|
|||
unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
|
||||
#endif
|
||||
|
||||
set_fs(USER_DS);
|
||||
|
||||
/*
|
||||
* If we exec out of a kernel thread then thread.regs will not be
|
||||
* set. Do it now.
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@ unsigned long tce_alloc_start, tce_alloc_end;
|
|||
u64 ppc64_rma_size;
|
||||
#endif
|
||||
static phys_addr_t first_memblock_size;
|
||||
static int __initdata boot_cpu_count;
|
||||
|
||||
static int __init early_parse_mem(char *p)
|
||||
{
|
||||
|
|
@ -769,6 +770,13 @@ void __init early_init_devtree(void *params)
|
|||
*/
|
||||
of_scan_flat_dt(early_init_dt_scan_cpus, NULL);
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(CONFIG_PPC64)
|
||||
/* We'll later wait for secondaries to check in; there are
|
||||
* NCPUS-1 non-boot CPUs :-)
|
||||
*/
|
||||
spinning_secondaries = boot_cpu_count - 1;
|
||||
#endif
|
||||
|
||||
DBG(" <- early_init_devtree()\n");
|
||||
}
|
||||
|
||||
|
|
@ -862,16 +870,14 @@ static int prom_reconfig_notifier(struct notifier_block *nb,
|
|||
switch (action) {
|
||||
case PSERIES_RECONFIG_ADD:
|
||||
err = of_finish_dynamic_node(node);
|
||||
if (err < 0) {
|
||||
if (err < 0)
|
||||
printk(KERN_ERR "finish_node returned %d\n", err);
|
||||
err = NOTIFY_BAD;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
err = NOTIFY_DONE;
|
||||
err = 0;
|
||||
break;
|
||||
}
|
||||
return err;
|
||||
return notifier_from_errno(err);
|
||||
}
|
||||
|
||||
static struct notifier_block prom_reconfig_nb = {
|
||||
|
|
|
|||
|
|
@ -707,29 +707,14 @@ static int powerpc_debugfs_init(void)
|
|||
arch_initcall(powerpc_debugfs_init);
|
||||
#endif
|
||||
|
||||
static int ppc_dflt_bus_notify(struct notifier_block *nb,
|
||||
unsigned long action, void *data)
|
||||
void ppc_printk_progress(char *s, unsigned short hex)
|
||||
{
|
||||
struct device *dev = data;
|
||||
|
||||
/* We are only intereted in device addition */
|
||||
if (action != BUS_NOTIFY_ADD_DEVICE)
|
||||
return 0;
|
||||
|
||||
set_dma_ops(dev, &dma_direct_ops);
|
||||
|
||||
return NOTIFY_DONE;
|
||||
pr_info("%s\n", s);
|
||||
}
|
||||
|
||||
static struct notifier_block ppc_dflt_plat_bus_notifier = {
|
||||
.notifier_call = ppc_dflt_bus_notify,
|
||||
.priority = INT_MAX,
|
||||
};
|
||||
|
||||
static int __init setup_bus_notifier(void)
|
||||
void arch_setup_pdev_archdata(struct platform_device *pdev)
|
||||
{
|
||||
bus_register_notifier(&platform_bus_type, &ppc_dflt_plat_bus_notifier);
|
||||
return 0;
|
||||
pdev->archdata.dma_mask = DMA_BIT_MASK(32);
|
||||
pdev->dev.dma_mask = &pdev->archdata.dma_mask;
|
||||
set_dma_ops(&pdev->dev, &dma_direct_ops);
|
||||
}
|
||||
|
||||
arch_initcall(setup_bus_notifier);
|
||||
|
|
|
|||
|
|
@ -48,8 +48,8 @@ extern void bootx_init(unsigned long r4, unsigned long phys);
|
|||
|
||||
int boot_cpuid = -1;
|
||||
EXPORT_SYMBOL_GPL(boot_cpuid);
|
||||
int __initdata boot_cpu_count;
|
||||
int boot_cpuid_phys;
|
||||
EXPORT_SYMBOL_GPL(boot_cpuid_phys);
|
||||
|
||||
int smp_hw_index[NR_CPUS];
|
||||
|
||||
|
|
@ -127,6 +127,8 @@ notrace void __init machine_init(unsigned long dt_ptr)
|
|||
/* Do some early initialization based on the flat device tree */
|
||||
early_init_devtree(__va(dt_ptr));
|
||||
|
||||
early_init_mmu();
|
||||
|
||||
probe_machine();
|
||||
|
||||
setup_kdump_trampoline();
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@
|
|||
#endif
|
||||
|
||||
int boot_cpuid = 0;
|
||||
int __initdata boot_cpu_count;
|
||||
int __initdata spinning_secondaries;
|
||||
u64 ppc64_pft_size;
|
||||
|
||||
/* Pick defaults since we might want to patch instructions
|
||||
|
|
@ -254,11 +254,11 @@ void smp_release_cpus(void)
|
|||
for (i = 0; i < 100000; i++) {
|
||||
mb();
|
||||
HMT_low();
|
||||
if (boot_cpu_count == 0)
|
||||
if (spinning_secondaries == 0)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
DBG("boot_cpu_count = %d\n", boot_cpu_count);
|
||||
DBG("spinning_secondaries = %d\n", spinning_secondaries);
|
||||
|
||||
DBG(" <- smp_release_cpus()\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -202,14 +202,6 @@ void smp_muxed_ipi_message_pass(int cpu, int msg)
|
|||
smp_ops->cause_ipi(cpu, info->data);
|
||||
}
|
||||
|
||||
void smp_muxed_ipi_resend(void)
|
||||
{
|
||||
struct cpu_messages *info = &__get_cpu_var(ipi_message);
|
||||
|
||||
if (info->messages)
|
||||
smp_ops->cause_ipi(smp_processor_id(), info->data);
|
||||
}
|
||||
|
||||
irqreturn_t smp_ipi_demux(void)
|
||||
{
|
||||
struct cpu_messages *info = &__get_cpu_var(ipi_message);
|
||||
|
|
@ -238,16 +230,26 @@ irqreturn_t smp_ipi_demux(void)
|
|||
}
|
||||
#endif /* CONFIG_PPC_SMP_MUXED_IPI */
|
||||
|
||||
static inline void do_message_pass(int cpu, int msg)
|
||||
{
|
||||
if (smp_ops->message_pass)
|
||||
smp_ops->message_pass(cpu, msg);
|
||||
#ifdef CONFIG_PPC_SMP_MUXED_IPI
|
||||
else
|
||||
smp_muxed_ipi_message_pass(cpu, msg);
|
||||
#endif
|
||||
}
|
||||
|
||||
void smp_send_reschedule(int cpu)
|
||||
{
|
||||
if (likely(smp_ops))
|
||||
smp_ops->message_pass(cpu, PPC_MSG_RESCHEDULE);
|
||||
do_message_pass(cpu, PPC_MSG_RESCHEDULE);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(smp_send_reschedule);
|
||||
|
||||
void arch_send_call_function_single_ipi(int cpu)
|
||||
{
|
||||
smp_ops->message_pass(cpu, PPC_MSG_CALL_FUNC_SINGLE);
|
||||
do_message_pass(cpu, PPC_MSG_CALL_FUNC_SINGLE);
|
||||
}
|
||||
|
||||
void arch_send_call_function_ipi_mask(const struct cpumask *mask)
|
||||
|
|
@ -255,7 +257,7 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask)
|
|||
unsigned int cpu;
|
||||
|
||||
for_each_cpu(cpu, mask)
|
||||
smp_ops->message_pass(cpu, PPC_MSG_CALL_FUNCTION);
|
||||
do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
|
||||
|
|
@ -269,7 +271,7 @@ void smp_send_debugger_break(void)
|
|||
|
||||
for_each_online_cpu(cpu)
|
||||
if (cpu != me)
|
||||
smp_ops->message_pass(cpu, PPC_MSG_DEBUGGER_BREAK);
|
||||
do_message_pass(cpu, PPC_MSG_DEBUGGER_BREAK);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -304,6 +306,10 @@ struct thread_info *current_set[NR_CPUS];
|
|||
static void __devinit smp_store_cpu_info(int id)
|
||||
{
|
||||
per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR);
|
||||
#ifdef CONFIG_PPC_FSL_BOOK3E
|
||||
per_cpu(next_tlbcam_idx, id)
|
||||
= (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init smp_prepare_cpus(unsigned int max_cpus)
|
||||
|
|
|
|||
|
|
@ -31,6 +31,9 @@ void __init udbg_early_init(void)
|
|||
#if defined(CONFIG_PPC_EARLY_DEBUG_LPAR)
|
||||
/* For LPAR machines that have an HVC console on vterm 0 */
|
||||
udbg_init_debug_lpar();
|
||||
#elif defined(CONFIG_PPC_EARLY_DEBUG_LPAR_HVSI)
|
||||
/* For LPAR machines that have an HVSI console on vterm 0 */
|
||||
udbg_init_debug_lpar_hvsi();
|
||||
#elif defined(CONFIG_PPC_EARLY_DEBUG_G5)
|
||||
/* For use on Apple G5 machines */
|
||||
udbg_init_pmac_realmode();
|
||||
|
|
@ -68,6 +71,8 @@ void __init udbg_early_init(void)
|
|||
|
||||
#ifdef CONFIG_PPC_EARLY_DEBUG
|
||||
console_loglevel = 10;
|
||||
|
||||
register_early_udbg_console();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -186,10 +186,11 @@ void __init MMU_init_hw(void)
|
|||
unsigned long __init mmu_mapin_ram(unsigned long top)
|
||||
{
|
||||
unsigned long addr;
|
||||
unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
|
||||
|
||||
/* Pin in enough TLBs to cover any lowmem not covered by the
|
||||
* initial 256M mapping established in head_44x.S */
|
||||
for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
|
||||
for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
|
||||
addr += PPC_PIN_SIZE) {
|
||||
if (mmu_has_feature(MMU_FTR_TYPE_47x))
|
||||
ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
|
||||
|
|
@ -218,19 +219,25 @@ unsigned long __init mmu_mapin_ram(unsigned long top)
|
|||
void setup_initial_memory_limit(phys_addr_t first_memblock_base,
|
||||
phys_addr_t first_memblock_size)
|
||||
{
|
||||
u64 size;
|
||||
|
||||
#ifndef CONFIG_RELOCATABLE
|
||||
/* We don't currently support the first MEMBLOCK not mapping 0
|
||||
* physical on those processors
|
||||
*/
|
||||
BUG_ON(first_memblock_base != 0);
|
||||
#endif
|
||||
|
||||
/* 44x has a 256M TLB entry pinned at boot */
|
||||
memblock_set_current_limit(min_t(u64, first_memblock_size, PPC_PIN_SIZE));
|
||||
size = (min_t(u64, first_memblock_size, PPC_PIN_SIZE));
|
||||
memblock_set_current_limit(first_memblock_base + size);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void __cpuinit mmu_init_secondary(int cpu)
|
||||
{
|
||||
unsigned long addr;
|
||||
unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
|
||||
|
||||
/* Pin in enough TLBs to cover any lowmem not covered by the
|
||||
* initial 256M mapping established in head_44x.S
|
||||
|
|
@ -241,7 +248,7 @@ void __cpuinit mmu_init_secondary(int cpu)
|
|||
* stack. current (r2) isn't initialized, smp_processor_id()
|
||||
* will not work, current thread info isn't accessible, ...
|
||||
*/
|
||||
for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
|
||||
for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
|
||||
addr += PPC_PIN_SIZE) {
|
||||
if (mmu_has_feature(MMU_FTR_TYPE_47x))
|
||||
ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
|
||||
|
|
|
|||
|
|
@ -191,38 +191,6 @@ void __init *early_get_page(void)
|
|||
return __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
|
||||
}
|
||||
|
||||
/* Free up now-unused memory */
|
||||
static void free_sec(unsigned long start, unsigned long end, const char *name)
|
||||
{
|
||||
unsigned long cnt = 0;
|
||||
|
||||
while (start < end) {
|
||||
ClearPageReserved(virt_to_page(start));
|
||||
init_page_count(virt_to_page(start));
|
||||
free_page(start);
|
||||
cnt++;
|
||||
start += PAGE_SIZE;
|
||||
}
|
||||
if (cnt) {
|
||||
printk(" %ldk %s", cnt << (PAGE_SHIFT - 10), name);
|
||||
totalram_pages += cnt;
|
||||
}
|
||||
}
|
||||
|
||||
void free_initmem(void)
|
||||
{
|
||||
#define FREESEC(TYPE) \
|
||||
free_sec((unsigned long)(&__ ## TYPE ## _begin), \
|
||||
(unsigned long)(&__ ## TYPE ## _end), \
|
||||
#TYPE);
|
||||
|
||||
printk ("Freeing unused kernel memory:");
|
||||
FREESEC(init);
|
||||
printk("\n");
|
||||
ppc_md.progress = NULL;
|
||||
#undef FREESEC
|
||||
}
|
||||
|
||||
#ifdef CONFIG_8xx /* No 8xx specific .c file to put that in ... */
|
||||
void setup_initial_memory_limit(phys_addr_t first_memblock_base,
|
||||
phys_addr_t first_memblock_size)
|
||||
|
|
|
|||
|
|
@ -83,22 +83,6 @@ EXPORT_SYMBOL_GPL(memstart_addr);
|
|||
phys_addr_t kernstart_addr;
|
||||
EXPORT_SYMBOL_GPL(kernstart_addr);
|
||||
|
||||
void free_initmem(void)
|
||||
{
|
||||
unsigned long addr;
|
||||
|
||||
addr = (unsigned long)__init_begin;
|
||||
for (; addr < (unsigned long)__init_end; addr += PAGE_SIZE) {
|
||||
memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
|
||||
ClearPageReserved(virt_to_page(addr));
|
||||
init_page_count(virt_to_page(addr));
|
||||
free_page(addr);
|
||||
totalram_pages++;
|
||||
}
|
||||
printk ("Freeing unused kernel memory: %luk freed\n",
|
||||
((unsigned long)__init_end - (unsigned long)__init_begin) >> 10);
|
||||
}
|
||||
|
||||
static void pgd_ctor(void *addr)
|
||||
{
|
||||
memset(addr, 0, PGD_TABLE_SIZE);
|
||||
|
|
|
|||
|
|
@ -249,7 +249,7 @@ static int __init mark_nonram_nosave(void)
|
|||
*/
|
||||
void __init paging_init(void)
|
||||
{
|
||||
unsigned long total_ram = memblock_phys_mem_size();
|
||||
unsigned long long total_ram = memblock_phys_mem_size();
|
||||
phys_addr_t top_of_ram = memblock_end_of_DRAM();
|
||||
unsigned long max_zone_pfns[MAX_NR_ZONES];
|
||||
|
||||
|
|
@ -269,7 +269,7 @@ void __init paging_init(void)
|
|||
kmap_prot = PAGE_KERNEL;
|
||||
#endif /* CONFIG_HIGHMEM */
|
||||
|
||||
printk(KERN_DEBUG "Top of RAM: 0x%llx, Total RAM: 0x%lx\n",
|
||||
printk(KERN_DEBUG "Top of RAM: 0x%llx, Total RAM: 0x%llx\n",
|
||||
(unsigned long long)top_of_ram, total_ram);
|
||||
printk(KERN_DEBUG "Memory hole size: %ldMB\n",
|
||||
(long int)((top_of_ram - total_ram) >> 20));
|
||||
|
|
@ -337,8 +337,9 @@ void __init mem_init(void)
|
|||
|
||||
highmem_mapnr = lowmem_end_addr >> PAGE_SHIFT;
|
||||
for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) {
|
||||
phys_addr_t paddr = (phys_addr_t)pfn << PAGE_SHIFT;
|
||||
struct page *page = pfn_to_page(pfn);
|
||||
if (memblock_is_reserved(pfn << PAGE_SHIFT))
|
||||
if (memblock_is_reserved(paddr))
|
||||
continue;
|
||||
ClearPageReserved(page);
|
||||
init_page_count(page);
|
||||
|
|
@ -352,6 +353,15 @@ void __init mem_init(void)
|
|||
}
|
||||
#endif /* CONFIG_HIGHMEM */
|
||||
|
||||
#if defined(CONFIG_PPC_FSL_BOOK3E) && !defined(CONFIG_SMP)
|
||||
/*
|
||||
* If smp is enabled, next_tlbcam_idx is initialized in the cpu up
|
||||
* functions.... do it here for the non-smp case.
|
||||
*/
|
||||
per_cpu(next_tlbcam_idx, smp_processor_id()) =
|
||||
(mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
|
||||
#endif
|
||||
|
||||
printk(KERN_INFO "Memory: %luk/%luk available (%luk kernel code, "
|
||||
"%luk reserved, %luk data, %luk bss, %luk init)\n",
|
||||
nr_free_pages() << (PAGE_SHIFT-10),
|
||||
|
|
@ -382,6 +392,25 @@ void __init mem_init(void)
|
|||
mem_init_done = 1;
|
||||
}
|
||||
|
||||
void free_initmem(void)
|
||||
{
|
||||
unsigned long addr;
|
||||
|
||||
ppc_md.progress = ppc_printk_progress;
|
||||
|
||||
addr = (unsigned long)__init_begin;
|
||||
for (; addr < (unsigned long)__init_end; addr += PAGE_SIZE) {
|
||||
memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
|
||||
ClearPageReserved(virt_to_page(addr));
|
||||
init_page_count(virt_to_page(addr));
|
||||
free_page(addr);
|
||||
totalram_pages++;
|
||||
}
|
||||
pr_info("Freeing unused kernel memory: %luk freed\n",
|
||||
((unsigned long)__init_end -
|
||||
(unsigned long)__init_begin) >> 10);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
void __init free_initrd_mem(unsigned long start, unsigned long end)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -177,3 +177,7 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
|
|||
flush_range(vma->vm_mm, start, end);
|
||||
}
|
||||
EXPORT_SYMBOL(flush_tlb_range);
|
||||
|
||||
void __init early_init_mmu(void)
|
||||
{
|
||||
}
|
||||
|
|
|
|||
|
|
@ -30,6 +30,212 @@
|
|||
#define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
|
||||
#define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
|
||||
|
||||
/**********************************************************************
|
||||
* *
|
||||
* TLB miss handling for Book3E with a bolted linear mapping *
|
||||
* No virtual page table, no nested TLB misses *
|
||||
* *
|
||||
**********************************************************************/
|
||||
|
||||
.macro tlb_prolog_bolted addr
|
||||
mtspr SPRN_SPRG_TLB_SCRATCH,r13
|
||||
mfspr r13,SPRN_SPRG_PACA
|
||||
std r10,PACA_EXTLB+EX_TLB_R10(r13)
|
||||
mfcr r10
|
||||
std r11,PACA_EXTLB+EX_TLB_R11(r13)
|
||||
std r16,PACA_EXTLB+EX_TLB_R16(r13)
|
||||
mfspr r16,\addr /* get faulting address */
|
||||
std r14,PACA_EXTLB+EX_TLB_R14(r13)
|
||||
ld r14,PACAPGD(r13)
|
||||
std r15,PACA_EXTLB+EX_TLB_R15(r13)
|
||||
std r10,PACA_EXTLB+EX_TLB_CR(r13)
|
||||
TLB_MISS_PROLOG_STATS_BOLTED
|
||||
.endm
|
||||
|
||||
.macro tlb_epilog_bolted
|
||||
ld r14,PACA_EXTLB+EX_TLB_CR(r13)
|
||||
ld r10,PACA_EXTLB+EX_TLB_R10(r13)
|
||||
ld r11,PACA_EXTLB+EX_TLB_R11(r13)
|
||||
mtcr r14
|
||||
ld r14,PACA_EXTLB+EX_TLB_R14(r13)
|
||||
ld r15,PACA_EXTLB+EX_TLB_R15(r13)
|
||||
TLB_MISS_RESTORE_STATS_BOLTED
|
||||
ld r16,PACA_EXTLB+EX_TLB_R16(r13)
|
||||
mfspr r13,SPRN_SPRG_TLB_SCRATCH
|
||||
.endm
|
||||
|
||||
/* Data TLB miss */
|
||||
START_EXCEPTION(data_tlb_miss_bolted)
|
||||
tlb_prolog_bolted SPRN_DEAR
|
||||
|
||||
/* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
|
||||
|
||||
/* We do the user/kernel test for the PID here along with the RW test
|
||||
*/
|
||||
/* We pre-test some combination of permissions to avoid double
|
||||
* faults:
|
||||
*
|
||||
* We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
|
||||
* ESR_ST is 0x00800000
|
||||
* _PAGE_BAP_SW is 0x00000010
|
||||
* So the shift is >> 19. This tests for supervisor writeability.
|
||||
* If the page happens to be supervisor writeable and not user
|
||||
* writeable, we will take a new fault later, but that should be
|
||||
* a rare enough case.
|
||||
*
|
||||
* We also move ESR_ST in _PAGE_DIRTY position
|
||||
* _PAGE_DIRTY is 0x00001000 so the shift is >> 11
|
||||
*
|
||||
* MAS1 is preset for all we need except for TID that needs to
|
||||
* be cleared for kernel translations
|
||||
*/
|
||||
|
||||
mfspr r11,SPRN_ESR
|
||||
|
||||
srdi r15,r16,60 /* get region */
|
||||
rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
|
||||
bne- dtlb_miss_fault_bolted
|
||||
|
||||
rlwinm r10,r11,32-19,27,27
|
||||
rlwimi r10,r11,32-16,19,19
|
||||
cmpwi r15,0
|
||||
ori r10,r10,_PAGE_PRESENT
|
||||
oris r11,r10,_PAGE_ACCESSED@h
|
||||
|
||||
TLB_MISS_STATS_SAVE_INFO_BOLTED
|
||||
bne tlb_miss_kernel_bolted
|
||||
|
||||
tlb_miss_common_bolted:
|
||||
/*
|
||||
* This is the guts of the TLB miss handler for bolted-linear.
|
||||
* We are entered with:
|
||||
*
|
||||
* r16 = faulting address
|
||||
* r15 = crap (free to use)
|
||||
* r14 = page table base
|
||||
* r13 = PACA
|
||||
* r11 = PTE permission mask
|
||||
* r10 = crap (free to use)
|
||||
*/
|
||||
rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
|
||||
cmpldi cr0,r14,0
|
||||
clrrdi r15,r15,3
|
||||
beq tlb_miss_fault_bolted
|
||||
|
||||
BEGIN_MMU_FTR_SECTION
|
||||
/* Set the TLB reservation and search for existing entry. Then load
|
||||
* the entry.
|
||||
*/
|
||||
PPC_TLBSRX_DOT(0,r16)
|
||||
ldx r14,r14,r15
|
||||
beq normal_tlb_miss_done
|
||||
MMU_FTR_SECTION_ELSE
|
||||
ldx r14,r14,r15
|
||||
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
|
||||
|
||||
#ifndef CONFIG_PPC_64K_PAGES
|
||||
rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
|
||||
clrrdi r15,r15,3
|
||||
|
||||
cmpldi cr0,r14,0
|
||||
beq tlb_miss_fault_bolted
|
||||
|
||||
ldx r14,r14,r15
|
||||
#endif /* CONFIG_PPC_64K_PAGES */
|
||||
|
||||
rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
|
||||
clrrdi r15,r15,3
|
||||
|
||||
cmpldi cr0,r14,0
|
||||
beq tlb_miss_fault_bolted
|
||||
|
||||
ldx r14,r14,r15
|
||||
|
||||
rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
|
||||
clrrdi r15,r15,3
|
||||
|
||||
cmpldi cr0,r14,0
|
||||
beq tlb_miss_fault_bolted
|
||||
|
||||
ldx r14,r14,r15
|
||||
|
||||
/* Check if required permissions are met */
|
||||
andc. r15,r11,r14
|
||||
rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
|
||||
bne- tlb_miss_fault_bolted
|
||||
|
||||
/* Now we build the MAS:
|
||||
*
|
||||
* MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
|
||||
* MAS 1 : Almost fully setup
|
||||
* - PID already updated by caller if necessary
|
||||
* - TSIZE need change if !base page size, not
|
||||
* yet implemented for now
|
||||
* MAS 2 : Defaults not useful, need to be redone
|
||||
* MAS 3+7 : Needs to be done
|
||||
*/
|
||||
clrrdi r11,r16,12 /* Clear low crap in EA */
|
||||
clrldi r15,r15,12 /* Clear crap at the top */
|
||||
rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
|
||||
rlwimi r15,r14,32-8,22,25 /* Move in U bits */
|
||||
mtspr SPRN_MAS2,r11
|
||||
andi. r11,r14,_PAGE_DIRTY
|
||||
rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
|
||||
|
||||
/* Mask out SW and UW if !DIRTY (XXX optimize this !) */
|
||||
bne 1f
|
||||
li r11,MAS3_SW|MAS3_UW
|
||||
andc r15,r15,r11
|
||||
1:
|
||||
mtspr SPRN_MAS7_MAS3,r15
|
||||
tlbwe
|
||||
|
||||
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
|
||||
tlb_epilog_bolted
|
||||
rfi
|
||||
|
||||
itlb_miss_kernel_bolted:
|
||||
li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
|
||||
oris r11,r11,_PAGE_ACCESSED@h
|
||||
tlb_miss_kernel_bolted:
|
||||
mfspr r10,SPRN_MAS1
|
||||
ld r14,PACA_KERNELPGD(r13)
|
||||
cmpldi cr0,r15,8 /* Check for vmalloc region */
|
||||
rlwinm r10,r10,0,16,1 /* Clear TID */
|
||||
mtspr SPRN_MAS1,r10
|
||||
beq+ tlb_miss_common_bolted
|
||||
|
||||
tlb_miss_fault_bolted:
|
||||
/* We need to check if it was an instruction miss */
|
||||
andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX
|
||||
bne itlb_miss_fault_bolted
|
||||
dtlb_miss_fault_bolted:
|
||||
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
|
||||
tlb_epilog_bolted
|
||||
b exc_data_storage_book3e
|
||||
itlb_miss_fault_bolted:
|
||||
TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
|
||||
tlb_epilog_bolted
|
||||
b exc_instruction_storage_book3e
|
||||
|
||||
/* Instruction TLB miss */
|
||||
START_EXCEPTION(instruction_tlb_miss_bolted)
|
||||
tlb_prolog_bolted SPRN_SRR0
|
||||
|
||||
rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
|
||||
srdi r15,r16,60 /* get region */
|
||||
TLB_MISS_STATS_SAVE_INFO_BOLTED
|
||||
bne- itlb_miss_fault_bolted
|
||||
|
||||
li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
|
||||
|
||||
/* We do the user/kernel test for the PID here along with the RW test
|
||||
*/
|
||||
|
||||
cmpldi cr0,r15,0 /* Check for user region */
|
||||
oris r11,r11,_PAGE_ACCESSED@h
|
||||
beq tlb_miss_common_bolted
|
||||
b itlb_miss_kernel_bolted
|
||||
|
||||
/**********************************************************************
|
||||
* *
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
#include <linux/preempt.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/of_fdt.h>
|
||||
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/tlb.h>
|
||||
|
|
@ -102,6 +103,12 @@ unsigned long linear_map_top; /* Top of linear mapping */
|
|||
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
||||
#ifdef CONFIG_PPC_FSL_BOOK3E
|
||||
/* next_tlbcam_idx is used to round-robin tlbcam entry assignment */
|
||||
DEFINE_PER_CPU(int, next_tlbcam_idx);
|
||||
EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Base TLB flushing operations:
|
||||
*
|
||||
|
|
@ -266,6 +273,17 @@ EXPORT_SYMBOL(flush_tlb_page);
|
|||
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
#ifdef CONFIG_PPC_47x
|
||||
void __init early_init_mmu_47x(void)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
if (of_get_flat_dt_prop(root, "cooperative-partition", NULL))
|
||||
mmu_clear_feature(MMU_FTR_USE_TLBIVAX_BCAST);
|
||||
#endif /* CONFIG_SMP */
|
||||
}
|
||||
#endif /* CONFIG_PPC_47x */
|
||||
|
||||
/*
|
||||
* Flush kernel TLB entries in the given range
|
||||
*/
|
||||
|
|
@ -443,14 +461,27 @@ static void setup_page_sizes(void)
|
|||
}
|
||||
}
|
||||
|
||||
static void setup_mmu_htw(void)
|
||||
static void __patch_exception(int exc, unsigned long addr)
|
||||
{
|
||||
extern unsigned int interrupt_base_book3e;
|
||||
extern unsigned int exc_data_tlb_miss_htw_book3e;
|
||||
extern unsigned int exc_instruction_tlb_miss_htw_book3e;
|
||||
unsigned int *ibase = &interrupt_base_book3e;
|
||||
|
||||
/* Our exceptions vectors start with a NOP and -then- a branch
|
||||
* to deal with single stepping from userspace which stops on
|
||||
* the second instruction. Thus we need to patch the second
|
||||
* instruction of the exception, not the first one
|
||||
*/
|
||||
|
||||
unsigned int *ibase = &interrupt_base_book3e;
|
||||
patch_branch(ibase + (exc / 4) + 1, addr, 0);
|
||||
}
|
||||
|
||||
#define patch_exception(exc, name) do { \
|
||||
extern unsigned int name; \
|
||||
__patch_exception((exc), (unsigned long)&name); \
|
||||
} while (0)
|
||||
|
||||
static void setup_mmu_htw(void)
|
||||
{
|
||||
/* Check if HW tablewalk is present, and if yes, enable it by:
|
||||
*
|
||||
* - patching the TLB miss handlers to branch to the
|
||||
|
|
@ -462,19 +493,12 @@ static void setup_mmu_htw(void)
|
|||
|
||||
if ((tlb0cfg & TLBnCFG_IND) &&
|
||||
(tlb0cfg & TLBnCFG_PT)) {
|
||||
/* Our exceptions vectors start with a NOP and -then- a branch
|
||||
* to deal with single stepping from userspace which stops on
|
||||
* the second instruction. Thus we need to patch the second
|
||||
* instruction of the exception, not the first one
|
||||
*/
|
||||
patch_branch(ibase + (0x1c0 / 4) + 1,
|
||||
(unsigned long)&exc_data_tlb_miss_htw_book3e, 0);
|
||||
patch_branch(ibase + (0x1e0 / 4) + 1,
|
||||
(unsigned long)&exc_instruction_tlb_miss_htw_book3e, 0);
|
||||
patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
|
||||
patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
|
||||
book3e_htw_enabled = 1;
|
||||
}
|
||||
pr_info("MMU: Book3E Page Tables %s\n",
|
||||
book3e_htw_enabled ? "Enabled" : "Disabled");
|
||||
pr_info("MMU: Book3E HW tablewalk %s\n",
|
||||
book3e_htw_enabled ? "enabled" : "not supported");
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -549,6 +573,9 @@ static void __early_init_mmu(int boot_cpu)
|
|||
/* limit memory so we dont have linear faults */
|
||||
memblock_enforce_memory_limit(linear_map_top);
|
||||
memblock_analyze();
|
||||
|
||||
patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
|
||||
patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -584,4 +611,11 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
|
|||
/* Finally limit subsequent allocations */
|
||||
memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
|
||||
}
|
||||
#else /* ! CONFIG_PPC64 */
|
||||
void __init early_init_mmu(void)
|
||||
{
|
||||
#ifdef CONFIG_PPC_47x
|
||||
early_init_mmu_47x();
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
|
|
|||
|
|
@ -67,6 +67,16 @@ config MPC85xx_RDB
|
|||
help
|
||||
This option enables support for the MPC85xx RDB (P2020 RDB) board
|
||||
|
||||
config P1010_RDB
|
||||
bool "Freescale P1010RDB"
|
||||
select DEFAULT_UIMAGE
|
||||
help
|
||||
This option enables support for the MPC85xx RDB (P1010 RDB) board
|
||||
|
||||
P1010RDB contains P1010Si, which provides CPU performance up to 800
|
||||
MHz and 1600 DMIPS, additional functionality and faster interfaces
|
||||
(DDR3/3L, SATA II, and PCI Express).
|
||||
|
||||
config P1022_DS
|
||||
bool "Freescale P1022 DS"
|
||||
select DEFAULT_UIMAGE
|
||||
|
|
@ -75,6 +85,12 @@ config P1022_DS
|
|||
help
|
||||
This option enables support for the Freescale P1022DS reference board.
|
||||
|
||||
config P1023_RDS
|
||||
bool "Freescale P1023 RDS"
|
||||
select DEFAULT_UIMAGE
|
||||
help
|
||||
This option enables support for the P1023 RDS board
|
||||
|
||||
config SOCRATES
|
||||
bool "Socrates"
|
||||
select DEFAULT_UIMAGE
|
||||
|
|
@ -155,6 +171,18 @@ config SBC8560
|
|||
help
|
||||
This option enables support for the Wind River SBC8560 board
|
||||
|
||||
config P2040_RDB
|
||||
bool "Freescale P2040 RDB"
|
||||
select DEFAULT_UIMAGE
|
||||
select PPC_E500MC
|
||||
select PHYS_64BIT
|
||||
select SWIOTLB
|
||||
select MPC8xxx_GPIO
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the P2040 RDB board
|
||||
|
||||
config P3041_DS
|
||||
bool "Freescale P3041 DS"
|
||||
select DEFAULT_UIMAGE
|
||||
|
|
@ -163,6 +191,7 @@ config P3041_DS
|
|||
select SWIOTLB
|
||||
select MPC8xxx_GPIO
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the P3041 DS board
|
||||
|
||||
|
|
@ -174,6 +203,7 @@ config P4080_DS
|
|||
select SWIOTLB
|
||||
select MPC8xxx_GPIO
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the P4080 DS board
|
||||
|
||||
|
|
@ -188,6 +218,7 @@ config P5020_DS
|
|||
select SWIOTLB
|
||||
select MPC8xxx_GPIO
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the P5020 DS board
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,10 @@ obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
|
|||
obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
|
||||
obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
|
||||
obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
|
||||
obj-$(CONFIG_P1010_RDB) += p1010rdb.o
|
||||
obj-$(CONFIG_P1022_DS) += p1022_ds.o
|
||||
obj-$(CONFIG_P1023_RDS) += p1023_rds.o
|
||||
obj-$(CONFIG_P2040_RDB) += p2040_rdb.o corenet_ds.o
|
||||
obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2009 Freescale Semiconductor Inc.
|
||||
* Copyright 2009-2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
|
|
@ -22,6 +22,7 @@
|
|||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/ppc-pci.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
|
|
@ -61,10 +62,6 @@ void __init corenet_ds_pic_init(void)
|
|||
mpic_init(mpic);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static int primary_phb_addr;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Setup the architecture
|
||||
*/
|
||||
|
|
@ -85,18 +82,19 @@ void __init corenet_ds_setup_arch(void)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
for_each_compatible_node(np, "pci", "fsl,p4080-pcie") {
|
||||
struct resource rsrc;
|
||||
of_address_to_resource(np, 0, &rsrc);
|
||||
if ((rsrc.start & 0xfffff) == primary_phb_addr)
|
||||
fsl_add_bridge(np, 1);
|
||||
else
|
||||
for_each_node_by_type(np, "pci") {
|
||||
if (of_device_is_compatible(np, "fsl,p4080-pcie") ||
|
||||
of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2")) {
|
||||
fsl_add_bridge(np, 0);
|
||||
|
||||
hose = pci_find_hose_for_OF_device(np);
|
||||
max = min(max, hose->dma_window_base_cur +
|
||||
hose->dma_window_size);
|
||||
hose = pci_find_hose_for_OF_device(np);
|
||||
max = min(max, hose->dma_window_base_cur +
|
||||
hose->dma_window_size);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC64
|
||||
pci_devs_phb_init();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
|
|
@ -116,6 +114,19 @@ static const struct of_device_id of_device_ids[] __devinitconst = {
|
|||
{
|
||||
.compatible = "fsl,rapidio-delta",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,p4080-pcie",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v2.2",
|
||||
},
|
||||
/* The following two are for the Freescale hypervisor */
|
||||
{
|
||||
.name = "hypervisor",
|
||||
},
|
||||
{
|
||||
.name = "handles",
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -83,7 +83,8 @@ void __init mpc85xx_ds_pic_init(void)
|
|||
if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
|
||||
mpic = mpic_alloc(np, r.start,
|
||||
MPIC_PRIMARY |
|
||||
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
|
||||
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
|
||||
MPIC_SINGLE_DEST_CPU,
|
||||
0, 256, " OpenPIC ");
|
||||
} else {
|
||||
mpic = mpic_alloc(np, r.start,
|
||||
|
|
|
|||
|
|
@ -58,10 +58,11 @@ void __init mpc85xx_rdb_pic_init(void)
|
|||
return;
|
||||
}
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,85XXRDB-CAMP")) {
|
||||
if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
|
||||
mpic = mpic_alloc(np, r.start,
|
||||
MPIC_PRIMARY |
|
||||
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
|
||||
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
|
||||
MPIC_SINGLE_DEST_CPU,
|
||||
0, 256, " OpenPIC ");
|
||||
} else {
|
||||
mpic = mpic_alloc(np, r.start,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* P1010RDB Board Setup
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
|
||||
void __init p1010_rdb_pic_init(void)
|
||||
{
|
||||
struct mpic *mpic;
|
||||
struct resource r;
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_node_by_type(NULL, "open-pic");
|
||||
if (np == NULL) {
|
||||
printk(KERN_ERR "Could not find open-pic node\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(np, 0, &r)) {
|
||||
printk(KERN_ERR "Failed to map mpic register space\n");
|
||||
of_node_put(np);
|
||||
return;
|
||||
}
|
||||
|
||||
mpic = mpic_alloc(np, r.start, MPIC_PRIMARY | MPIC_WANTS_RESET |
|
||||
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
|
||||
0, 256, " OpenPIC ");
|
||||
|
||||
BUG_ON(mpic == NULL);
|
||||
of_node_put(np);
|
||||
|
||||
mpic_init(mpic);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Setup the architecture
|
||||
*/
|
||||
static void __init p1010_rdb_setup_arch(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
struct device_node *np;
|
||||
#endif
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("p1010_rdb_setup_arch()", 0);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
for_each_node_by_type(np, "pci") {
|
||||
if (of_device_is_compatible(np, "fsl,p1010-pcie"))
|
||||
fsl_add_bridge(np, 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
|
||||
}
|
||||
|
||||
static struct of_device_id __initdata p1010rdb_ids[] = {
|
||||
{ .type = "soc", },
|
||||
{ .compatible = "soc", },
|
||||
{ .compatible = "simple-bus", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init p1010rdb_publish_devices(void)
|
||||
{
|
||||
return of_platform_bus_probe(NULL, p1010rdb_ids, NULL);
|
||||
}
|
||||
machine_device_initcall(p1010_rdb, p1010rdb_publish_devices);
|
||||
machine_arch_initcall(p1010_rdb, swiotlb_setup_bus_notifier);
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init p1010_rdb_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,P1010RDB"))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(p1010_rdb) {
|
||||
.name = "P1010 RDB",
|
||||
.probe = p1010_rdb_probe,
|
||||
.setup_arch = p1010_rdb_setup_arch,
|
||||
.init_IRQ = p1010_rdb_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
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Reference in New Issue