sh: sh7724: Update FSI/SPU2 clock
When FSI and Network (= NFS file system) were used at the same time, the I/O of FSI was unstable. This patch updates the SPU2 clock (which is used for FSI) to solve this issue. Special thanks to Jeremy. Signed-off-by: Jeremy Baker <Jeremy.Baker@renesas.com> Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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2 changed files with 15 additions and 5 deletions
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@ -1105,6 +1105,11 @@ static int __init arch_setup(void)
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gpio_request(GPIO_FN_FSIOBLRCK, NULL);
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gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
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/* set SPU2 clock to 83.4 MHz */
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clk = clk_get(NULL, "spu_clk");
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clk_set_rate(clk, clk_round_rate(clk, 83333333));
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clk_put(clk);
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/* change parent of FSI B */
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clk = clk_get(NULL, "fsib_clk");
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clk_register(&fsimckb_clk);
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@ -586,7 +586,7 @@ arch_initcall(arch_setup);
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static int __init devices_setup(void)
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{
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u16 sw = __raw_readw(SW4140); /* select camera, monitor */
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struct clk *fsia_clk;
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struct clk *clk;
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/* register board specific self-refresh code */
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sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
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@ -755,13 +755,18 @@ static int __init devices_setup(void)
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gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
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gpio_request(GPIO_FN_FSIIASD, NULL);
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/* set SPU2 clock to 83.4 MHz */
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clk = clk_get(NULL, "spu_clk");
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clk_set_rate(clk, clk_round_rate(clk, 83333333));
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clk_put(clk);
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/* change parent of FSI A */
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fsia_clk = clk_get(NULL, "fsia_clk");
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clk = clk_get(NULL, "fsia_clk");
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clk_register(&fsimcka_clk);
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clk_set_parent(fsia_clk, &fsimcka_clk);
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clk_set_rate(fsia_clk, 11000);
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clk_set_parent(clk, &fsimcka_clk);
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clk_set_rate(clk, 11000);
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clk_set_rate(&fsimcka_clk, 11000);
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clk_put(fsia_clk);
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clk_put(clk);
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/* SDHI0 connected to cn7 */
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gpio_request(GPIO_FN_SDHI0CD, NULL);
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