ARM: OMAP4: PM: Add support for OMAP4 dpll api's
Most of the dpll api's from dpll.c are reused for OMAP4. This patch does extend a few api's for OMAP4 support. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
This commit is contained in:
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a1391d2768
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5 changed files with 31 additions and 38 deletions
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@ -6,13 +6,14 @@
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obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
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obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
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omap-2-3-common = irq.o sdrc.o omap_hwmod.o
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omap-2-3-common = irq.o sdrc.o omap_hwmod.o
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omap-3-4-common = dpll.o
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prcm-common = prcm.o powerdomain.o
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prcm-common = prcm.o powerdomain.o
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clock-common = clock.o clock_common_data.o clockdomain.o
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clock-common = clock.o clock_common_data.o clockdomain.o
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obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
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obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
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obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
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obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
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dpll.o
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$(omap-3-4-common)
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obj-$(CONFIG_ARCH_OMAP4) += prcm.o clock.o
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obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o
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obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
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obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
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@ -249,6 +249,11 @@ u32 omap2_get_dpll_rate(struct clk *clk)
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if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
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if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
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v == OMAP3XXX_EN_DPLL_FRBYPASS)
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v == OMAP3XXX_EN_DPLL_FRBYPASS)
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return dd->clk_bypass->rate;
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return dd->clk_bypass->rate;
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} else if (cpu_is_omap44xx()) {
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if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
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v == OMAP4XXX_EN_DPLL_FRBYPASS ||
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v == OMAP4XXX_EN_DPLL_MNBYPASS)
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return dd->clk_bypass->rate;
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}
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}
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v = __raw_readl(dd->mult_div1_reg);
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v = __raw_readl(dd->mult_div1_reg);
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@ -36,6 +36,12 @@
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#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP3XXX_EN_DPLL_LOCKED 0x7
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#define OMAP3XXX_EN_DPLL_LOCKED 0x7
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/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
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#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP4XXX_EN_DPLL_LOCKED 0x7
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/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
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/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
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#define DPLL_LOW_POWER_STOP 0x1
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#define DPLL_LOW_POWER_STOP 0x1
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#define DPLL_LOW_POWER_BYPASS 0x5
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#define DPLL_LOW_POWER_BYPASS 0x5
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@ -22,31 +22,6 @@ struct clk_functions omap2_clk_functions = {
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.clk_disable_unused = omap2_clk_disable_unused,
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.clk_disable_unused = omap2_clk_disable_unused,
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};
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};
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/*
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* Dummy functions for DPLL control. Plan is to re-use
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* existing OMAP3 dpll control functions.
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*/
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unsigned long omap3_dpll_recalc(struct clk *clk)
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{
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return 0;
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}
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int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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{
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return 0;
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}
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int omap3_noncore_dpll_enable(struct clk *clk)
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{
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return 0;
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}
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void omap3_noncore_dpll_disable(struct clk *clk)
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{
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return;
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}
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const struct clkops clkops_noncore_dpll_ops = {
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const struct clkops clkops_noncore_dpll_ops = {
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.enable = &omap3_noncore_dpll_enable,
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.enable = &omap3_noncore_dpll_enable,
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.disable = &omap3_noncore_dpll_disable,
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.disable = &omap3_noncore_dpll_disable,
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@ -26,9 +26,9 @@
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#include <linux/limits.h>
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#include <linux/limits.h>
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#include <linux/bitops.h>
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#include <linux/bitops.h>
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#include <mach/cpu.h>
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#include <plat/cpu.h>
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#include <mach/clock.h>
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#include <plat/clock.h>
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#include <mach/sram.h>
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#include <plat/sram.h>
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#include <asm/div64.h>
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#include <asm/div64.h>
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#include <asm/clkdev.h>
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#include <asm/clkdev.h>
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@ -311,10 +311,12 @@ int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
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_omap3_noncore_dpll_bypass(clk);
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_omap3_noncore_dpll_bypass(clk);
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/* Set jitter correction */
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/* Set jitter correction */
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if (!cpu_is_omap44xx()) {
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v = __raw_readl(dd->control_reg);
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v = __raw_readl(dd->control_reg);
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v &= ~dd->freqsel_mask;
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v &= ~dd->freqsel_mask;
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v |= freqsel << __ffs(dd->freqsel_mask);
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v |= freqsel << __ffs(dd->freqsel_mask);
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__raw_writel(v, dd->control_reg);
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__raw_writel(v, dd->control_reg);
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}
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/* Set DPLL multiplier, divider */
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/* Set DPLL multiplier, divider */
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v = __raw_readl(dd->mult_div1_reg);
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v = __raw_readl(dd->mult_div1_reg);
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@ -346,7 +348,7 @@ int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
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int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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{
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{
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struct clk *new_parent = NULL;
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struct clk *new_parent = NULL;
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u16 freqsel;
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u16 freqsel = 0;
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struct dpll_data *dd;
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struct dpll_data *dd;
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int ret;
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int ret;
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@ -382,9 +384,13 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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if (dd->last_rounded_rate == 0)
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if (dd->last_rounded_rate == 0)
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return -EINVAL;
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return -EINVAL;
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freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
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/* No freqsel on OMAP4 */
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if (!cpu_is_omap44xx()) {
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freqsel = _omap3_dpll_compute_freqsel(clk,
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dd->last_rounded_n);
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if (!freqsel)
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if (!freqsel)
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WARN_ON(1);
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WARN_ON(1);
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}
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pr_debug("clock: %s: set rate: locking rate to %lu.\n",
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pr_debug("clock: %s: set rate: locking rate to %lu.\n",
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clk->name, rate);
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clk->name, rate);
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