[SCSI] aic79xx: Sequencer update
Update sequencer code to Adaptec version 2.0.12-6.3.9. Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
This commit is contained in:
Hannes Reinecke
James Bottomley
parent
ba62cd2d01
commit
11668bb673
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@ -75,8 +75,7 @@ struct scb_platform_data;
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#define INITIATOR_WILDCARD (~0)
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#define SCB_LIST_NULL 0xFF00
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#define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL))
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#define QOUTFIFO_ENTRY_VALID 0x8000
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#define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000))
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#define QOUTFIFO_ENTRY_VALID 0x80
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#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
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#define SCSIID_TARGET(ahd, scsiid) \
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@ -1053,6 +1052,13 @@ typedef uint8_t ahd_mode_state;
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typedef void ahd_callback_t (void *);
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struct ahd_completion
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{
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uint16_t tag;
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uint8_t sg_status;
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uint8_t valid_tag;
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};
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struct ahd_softc {
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bus_space_tag_t tags[2];
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bus_space_handle_t bshs[2];
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@ -1142,11 +1148,11 @@ struct ahd_softc {
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struct seeprom_config *seep_config;
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/* Command Queues */
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struct ahd_completion *qoutfifo;
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uint16_t qoutfifonext;
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uint16_t qoutfifonext_valid_tag;
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uint16_t qinfifonext;
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uint16_t qinfifo[AHD_SCB_MAX];
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uint16_t *qoutfifo;
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/*
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* Our qfreeze count. The sequencer compares
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@ -39,7 +39,7 @@
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*
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* $FreeBSD$
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*/
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VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $"
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VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $"
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/*
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* This file is processed by the aic7xxx_asm utility for use in assembling
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@ -65,13 +65,6 @@ VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $"
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mvi MODE_PTR, MK_MODE(src, dst); \
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}
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#define TOGGLE_DFF_MODE \
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if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
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call toggle_dff_mode_work_around; \
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} else { \
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xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \
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}
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#define RESTORE_MODE(mode) \
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if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
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mov mode call set_mode_work_around; \
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@ -1199,7 +1192,7 @@ register TARGPCISTAT {
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/*
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* LQ Packet In
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* The last LQ Packet received
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* The last LQ Packet recieved
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*/
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register LQIN {
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address 0x020
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@ -3542,10 +3535,34 @@ scratch_ram {
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COMPLETE_DMA_SCB_HEAD {
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size 2
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}
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/* Counting semaphore to prevent new select-outs */
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/*
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* tail of list of SCBs that have
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* completed but need to be uploaded
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* to the host prior to being completed.
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*/
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COMPLETE_DMA_SCB_TAIL {
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size 2
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}
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/*
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* head of list of SCBs that have
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* been uploaded to the host, but cannot
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* be completed until the QFREEZE is in
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* full effect (i.e. no selections pending).
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*/
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COMPLETE_ON_QFREEZE_HEAD {
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size 2
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}
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/*
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* Counting semaphore to prevent new select-outs
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* The queue is frozen so long as the sequencer
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* and kernel freeze counts differ.
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*/
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QFREEZE_COUNT {
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size 2
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}
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KERNEL_QFREEZE_COUNT {
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size 2
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}
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/*
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* Mode to restore on legacy idle loop exit.
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*/
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@ -3624,6 +3641,17 @@ scratch_ram {
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QOUTFIFO_ENTRY_VALID_TAG {
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size 1
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}
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/*
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* Kernel and sequencer offsets into the queue of
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* incoming target mode command descriptors. The
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* queue is full when the KERNEL_TQINPOS == TQINPOS.
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*/
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KERNEL_TQINPOS {
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size 1
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}
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TQINPOS {
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size 1
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}
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/*
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* Base address of our shared data with the kernel driver in host
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* memory. This includes the qoutfifo and target mode
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@ -3639,17 +3667,6 @@ scratch_ram {
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QOUTFIFO_NEXT_ADDR {
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size 4
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}
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/*
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* Kernel and sequencer offsets into the queue of
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* incoming target mode command descriptors. The
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* queue is full when the KERNEL_TQINPOS == TQINPOS.
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*/
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KERNEL_TQINPOS {
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size 1
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}
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TQINPOS {
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size 1
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}
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ARG_1 {
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size 1
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mask SEND_MSG 0x80
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@ -3951,6 +3968,7 @@ const SG_PREFETCH_ADDR_MASK download
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const SG_SIZEOF download
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const PKT_OVERRUN_BUFOFFSET download
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const SCB_TRANSFER_SIZE download
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const CACHELINE_MASK download
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/*
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* BIOS SCB offsets
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@ -40,7 +40,7 @@
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* $FreeBSD$
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*/
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VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#99 $"
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VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $"
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PATCH_ARG_LIST = "struct ahd_softc *ahd"
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PREFIX = "ahd_"
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@ -68,13 +68,47 @@ no_error_set:
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}
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SET_MODE(M_SCSI, M_SCSI)
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test SCSISEQ0, ENSELO|ENARBO jnz idle_loop_checkbus;
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test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz idle_loop_checkbus;
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test SEQ_FLAGS2, SELECTOUT_QFROZEN jz check_waiting_list;
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/*
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* If the kernel has caught up with us, thaw the queue.
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*/
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mov A, KERNEL_QFREEZE_COUNT;
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cmp QFREEZE_COUNT, A jne check_frozen_completions;
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mov A, KERNEL_QFREEZE_COUNT[1];
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cmp QFREEZE_COUNT[1], A jne check_frozen_completions;
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and SEQ_FLAGS2, ~SELECTOUT_QFROZEN;
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jmp check_waiting_list;
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check_frozen_completions:
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test SSTAT0, SELDO|SELINGO jnz idle_loop_checkbus;
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BEGIN_CRITICAL;
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/*
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* If we have completions stalled waiting for the qfreeze
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* to take effect, move them over to the complete_scb list
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* now that no selections are pending.
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*/
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cmp COMPLETE_ON_QFREEZE_HEAD[1],SCB_LIST_NULL je idle_loop_checkbus;
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/*
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* Find the end of the qfreeze list. The first element has
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* to be treated specially.
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*/
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bmov SCBPTR, COMPLETE_ON_QFREEZE_HEAD, 2;
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cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je join_lists;
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/*
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* Now the normal loop.
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*/
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bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
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cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . - 1;
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join_lists:
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bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
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bmov COMPLETE_SCB_HEAD, COMPLETE_ON_QFREEZE_HEAD, 2;
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mvi COMPLETE_ON_QFREEZE_HEAD[1], SCB_LIST_NULL;
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jmp idle_loop_checkbus;
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check_waiting_list:
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cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je idle_loop_checkbus;
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/*
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* ENSELO is cleared by a SELDO, so we must test for SELDO
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* one last time.
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*/
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BEGIN_CRITICAL;
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test SSTAT0, SELDO jnz select_out;
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END_CRITICAL;
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call start_selection;
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@ -90,6 +124,13 @@ idle_loop_check_nonpackreq:
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test SSTAT2, NONPACKREQ jz . + 2;
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call unexpected_nonpkt_phase_find_ctxt;
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if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
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/*
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* On Rev A. hardware, the busy LED is only
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* turned on automaically during selections
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* and re-selections. Make the LED status
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* more useful by forcing it to be on so
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* long as one of our data FIFOs is active.
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*/
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and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
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cmp A, FIFO0FREE|FIFO1FREE jne . + 3;
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and SBLKCTL, ~DIAGLEDEN|DIAGLEDON;
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@ -101,9 +142,9 @@ idle_loop_check_nonpackreq:
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call idle_loop_cchan;
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jmp idle_loop;
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BEGIN_CRITICAL;
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idle_loop_gsfifo:
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SET_MODE(M_SCSI, M_SCSI)
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BEGIN_CRITICAL;
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idle_loop_gsfifo_in_scsi_mode:
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test LQISTAT2, LQIGSAVAIL jz return;
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/*
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@ -152,11 +193,15 @@ END_CRITICAL;
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idle_loop_service_fifos:
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SET_MODE(M_DFF0, M_DFF0)
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BEGIN_CRITICAL;
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test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_next_fifo;
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call longjmp;
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END_CRITICAL;
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idle_loop_next_fifo:
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SET_MODE(M_DFF1, M_DFF1)
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BEGIN_CRITICAL;
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test LONGJMP_ADDR[1], INVALID_ADDR jz longjmp;
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END_CRITICAL;
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return:
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ret;
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@ -170,7 +215,6 @@ BEGIN_CRITICAL;
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test CCSCBCTL, CCARREN|CCSCBEN jz scbdma_idle;
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test CCSCBCTL, CCSCBDIR jnz fetch_new_scb_inprog;
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test CCSCBCTL, CCSCBDONE jz return;
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END_CRITICAL;
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/* FALLTHROUGH */
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scbdma_tohost_done:
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test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
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@ -180,26 +224,18 @@ scbdma_tohost_done:
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* bad SCSI status (currently only for underruns), we
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* queue the SCB for normal completion. Otherwise, we
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* wait until any select-out activity has halted, and
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* then notify the host so that the transaction can be
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* dealt with.
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* then queue the completion.
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*/
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test SCB_SCSI_STATUS, 0xff jnz scbdma_notify_host;
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and CCSCBCTL, ~(CCARREN|CCSCBEN);
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bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
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cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . + 2;
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mvi COMPLETE_DMA_SCB_TAIL[1], SCB_LIST_NULL;
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test SCB_SCSI_STATUS, 0xff jz scbdma_queue_completion;
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bmov SCB_NEXT_COMPLETE, COMPLETE_ON_QFREEZE_HEAD, 2;
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bmov COMPLETE_ON_QFREEZE_HEAD, SCBPTR, 2 ret;
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scbdma_queue_completion:
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bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
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bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
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scbdma_notify_host:
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SET_MODE(M_SCSI, M_SCSI)
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test SCSISEQ0, ENSELO jnz return;
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test SSTAT0, (SELDO|SELINGO) jnz return;
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SET_MODE(M_CCHAN, M_CCHAN)
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/*
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* Remove SCB and notify host.
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*/
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and CCSCBCTL, ~(CCARREN|CCSCBEN);
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bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
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SET_SEQINTCODE(BAD_SCB_STATUS)
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ret;
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fill_qoutfifo_dmadone:
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and CCSCBCTL, ~(CCARREN|CCSCBEN);
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call qoutfifo_updated;
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@ -208,6 +244,7 @@ fill_qoutfifo_dmadone:
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test QOFF_CTLSTA, SDSCB_ROLLOVR jz return;
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bmov QOUTFIFO_NEXT_ADDR, SHARED_DATA_ADDR, 4;
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xor QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID_TOGGLE ret;
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END_CRITICAL;
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qoutfifo_updated:
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/*
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@ -324,14 +361,15 @@ fill_qoutfifo:
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* Keep track of the SCBs we are dmaing just
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* in case the DMA fails or is aborted.
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*/
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mov A, QOUTFIFO_ENTRY_VALID_TAG;
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bmov COMPLETE_SCB_DMAINPROG_HEAD, COMPLETE_SCB_HEAD, 2;
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mvi CCSCBCTL, CCSCBRESET;
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bmov SCBHADDR, QOUTFIFO_NEXT_ADDR, 4;
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mov A, QOUTFIFO_NEXT_ADDR;
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bmov SCBPTR, COMPLETE_SCB_HEAD, 2;
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fill_qoutfifo_loop:
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mov CCSCBRAM, SCBPTR;
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or CCSCBRAM, A, SCBPTR[1];
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bmov CCSCBRAM, SCBPTR, 2;
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mov CCSCBRAM, SCB_SGPTR[0];
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mov CCSCBRAM, QOUTFIFO_ENTRY_VALID_TAG;
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mov NONE, SDSCB_QOFF;
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inc INT_COALESCING_CMDCOUNT;
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add CMDS_PENDING, -1;
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@ -339,6 +377,18 @@ fill_qoutfifo_loop:
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cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je fill_qoutfifo_done;
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cmp CCSCBADDR, CCSCBADDR_MAX je fill_qoutfifo_done;
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test QOFF_CTLSTA, SDSCB_ROLLOVR jnz fill_qoutfifo_done;
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/*
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* Don't cross an ADB or Cachline boundary when DMA'ing
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* completion entries. In PCI mode, at least in 32/33
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* configurations, the SCB DMA engine may lose its place
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* in the data-stream should the target force a retry on
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* something other than an 8byte aligned boundary. In
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* PCI-X mode, we do this to avoid split transactions since
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* many chipsets seem to be unable to format proper split
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* completions to continue the data transfer.
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*/
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add SINDEX, A, CCSCBADDR;
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test SINDEX, CACHELINE_MASK jz fill_qoutfifo_done;
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bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
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jmp fill_qoutfifo_loop;
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fill_qoutfifo_done:
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@ -354,7 +404,6 @@ dma_complete_scb:
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bmov SCBPTR, COMPLETE_DMA_SCB_HEAD, 2;
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bmov SCBHADDR, SCB_BUSADDR, 4;
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mvi CCARREN|CCSCBEN|CCSCBRESET jmp dma_scb;
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END_CRITICAL;
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/*
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* Either post or fetch an SCB from host memory. The caller
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@ -371,9 +420,19 @@ dma_scb:
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mvi SCBHCNT, SCB_TRANSFER_SIZE;
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mov CCSCBCTL, SINDEX ret;
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BEGIN_CRITICAL;
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setjmp:
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bmov LONGJMP_ADDR, STACK, 2 ret;
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/*
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* At least on the A, a return in the same
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* instruction as the bmov results in a return
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* to the caller, not to the new address at the
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* top of the stack. Since we want the latter
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* (we use setjmp to register a handler from an
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* interrupt context but not invoke that handler
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* until we return to our idle loop), use a
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* separate ret instruction.
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*/
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bmov LONGJMP_ADDR, STACK, 2;
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ret;
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setjmp_inline:
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bmov LONGJMP_ADDR, STACK, 2;
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longjmp:
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@ -392,11 +451,6 @@ set_mode_work_around:
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mvi SEQINTCTL, INTVEC1DSL;
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mov MODE_PTR, SINDEX;
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clr SEQINTCTL ret;
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toggle_dff_mode_work_around:
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mvi SEQINTCTL, INTVEC1DSL;
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xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
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clr SEQINTCTL ret;
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}
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@ -490,6 +544,21 @@ allocate_fifo1:
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SET_SRC_MODE M_SCSI;
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SET_DST_MODE M_SCSI;
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select_in:
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if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
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/*
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* On Rev A. hardware, the busy LED is only
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* turned on automaically during selections
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* and re-selections. Make the LED status
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* more useful by forcing it to be on from
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* the point of selection until our idle
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* loop determines that neither of our FIFOs
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* are busy. This handles the non-packetized
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* case nicely as we will not return to the
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* idle loop until the busfree at the end of
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* each transaction.
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*/
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or SBLKCTL, DIAGLEDEN|DIAGLEDON;
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}
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if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
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/*
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* Test to ensure that the bus has not
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@ -528,6 +597,21 @@ SET_SRC_MODE M_SCSI;
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SET_DST_MODE M_SCSI;
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select_out:
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BEGIN_CRITICAL;
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if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
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/*
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* On Rev A. hardware, the busy LED is only
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* turned on automaically during selections
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* and re-selections. Make the LED status
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* more useful by forcing it to be on from
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* the point of re-selection until our idle
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* loop determines that neither of our FIFOs
|
||||
* are busy. This handles the non-packetized
|
||||
* case nicely as we will not return to the
|
||||
* idle loop until the busfree at the end of
|
||||
* each transaction.
|
||||
*/
|
||||
or SBLKCTL, DIAGLEDEN|DIAGLEDON;
|
||||
}
|
||||
/* Clear out all SCBs that have been successfully sent. */
|
||||
if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
|
||||
/*
|
||||
|
|
@ -1000,15 +1084,9 @@ not_found_ITloop:
|
|||
/*
|
||||
* We received a "command complete" message. Put the SCB on the complete
|
||||
* queue and trigger a completion interrupt via the idle loop. Before doing
|
||||
* so, check to see if there
|
||||
* is a residual or the status byte is something other than STATUS_GOOD (0).
|
||||
* In either of these conditions, we upload the SCB back to the host so it can
|
||||
* process this information. In the case of a non zero status byte, we
|
||||
* additionally interrupt the kernel driver synchronously, allowing it to
|
||||
* decide if sense should be retrieved. If the kernel driver wishes to request
|
||||
* sense, it will fill the kernel SCB with a request sense command, requeue
|
||||
* it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
|
||||
* RETURN_1 to SEND_SENSE.
|
||||
* so, check to see if there is a residual or the status byte is something
|
||||
* other than STATUS_GOOD (0). In either of these conditions, we upload the
|
||||
* SCB back to the host so it can process this information.
|
||||
*/
|
||||
mesgin_complete:
|
||||
|
||||
|
|
@ -1053,6 +1131,7 @@ complete_nomsg:
|
|||
call queue_scb_completion;
|
||||
jmp await_busfree;
|
||||
|
||||
BEGIN_CRITICAL;
|
||||
freeze_queue:
|
||||
/* Cancel any pending select-out. */
|
||||
test SSTAT0, SELDO|SELINGO jnz . + 2;
|
||||
|
|
@ -1063,6 +1142,7 @@ freeze_queue:
|
|||
adc QFREEZE_COUNT[1], A;
|
||||
or SEQ_FLAGS2, SELECTOUT_QFROZEN;
|
||||
mov A, ACCUM_SAVE ret;
|
||||
END_CRITICAL;
|
||||
|
||||
/*
|
||||
* Complete the current FIFO's SCB if data for this same
|
||||
|
|
@ -1085,8 +1165,10 @@ queue_scb_completion:
|
|||
test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
|
||||
test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
|
||||
complete:
|
||||
BEGIN_CRITICAL;
|
||||
bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
|
||||
bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
|
||||
END_CRITICAL;
|
||||
bad_status:
|
||||
cmp SCB_SCSI_STATUS, STATUS_PKT_SENSE je upload_scb;
|
||||
call freeze_queue;
|
||||
|
|
@ -1097,9 +1179,18 @@ upload_scb:
|
|||
* it on the host.
|
||||
*/
|
||||
bmov SCB_TAG, SCBPTR, 2;
|
||||
bmov SCB_NEXT_COMPLETE, COMPLETE_DMA_SCB_HEAD, 2;
|
||||
BEGIN_CRITICAL;
|
||||
or SCB_SGPTR, SG_STATUS_VALID;
|
||||
mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL;
|
||||
cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne add_dma_scb_tail;
|
||||
bmov COMPLETE_DMA_SCB_HEAD, SCBPTR, 2;
|
||||
or SCB_SGPTR, SG_STATUS_VALID ret;
|
||||
bmov COMPLETE_DMA_SCB_TAIL, SCBPTR, 2 ret;
|
||||
add_dma_scb_tail:
|
||||
bmov REG0, SCBPTR, 2;
|
||||
bmov SCBPTR, COMPLETE_DMA_SCB_TAIL, 2;
|
||||
bmov SCB_NEXT_COMPLETE, REG0, 2;
|
||||
bmov COMPLETE_DMA_SCB_TAIL, REG0, 2 ret;
|
||||
END_CRITICAL;
|
||||
|
||||
/*
|
||||
* Is it a disconnect message? Set a flag in the SCB to remind us
|
||||
|
|
@ -1146,8 +1237,18 @@ SET_DST_MODE M_DFF1;
|
|||
await_busfree_clrchn:
|
||||
mvi DFFSXFRCTL, CLRCHN;
|
||||
await_busfree_not_m_dff:
|
||||
call clear_target_state;
|
||||
/* clear target specific flags */
|
||||
mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT;
|
||||
test SSTAT1,REQINIT|BUSFREE jz .;
|
||||
/*
|
||||
* We only set BUSFREE status once either a new
|
||||
* phase has been detected or we are really
|
||||
* BUSFREE. This allows the driver to know
|
||||
* that we are active on the bus even though
|
||||
* no identified transaction exists should a
|
||||
* timeout occur while awaiting busfree.
|
||||
*/
|
||||
mvi LASTPHASE, P_BUSFREE;
|
||||
test SSTAT1, BUSFREE jnz idle_loop;
|
||||
SET_SEQINTCODE(MISSED_BUSFREE)
|
||||
|
||||
|
|
@ -1202,11 +1303,6 @@ msgin_rdptrs_get_fifo:
|
|||
call allocate_fifo;
|
||||
jmp mesgin_done;
|
||||
|
||||
clear_target_state:
|
||||
mvi LASTPHASE, P_BUSFREE;
|
||||
/* clear target specific flags */
|
||||
mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret;
|
||||
|
||||
phase_lock:
|
||||
if ((ahd->bugs & AHD_EARLY_REQ_BUG) != 0) {
|
||||
/*
|
||||
|
|
@ -1297,6 +1393,47 @@ service_fifo:
|
|||
/* Are we actively fetching segments? */
|
||||
test CCSGCTL, CCSGENACK jnz return;
|
||||
|
||||
/*
|
||||
* Should the other FIFO get the S/G cache first? If
|
||||
* both FIFOs have been allocated since we last checked
|
||||
* any FIFO, it is important that we service a FIFO
|
||||
* that is not actively on the bus first. This guarantees
|
||||
* that a FIFO will be freed to handle snapshot requests for
|
||||
* any FIFO that is still on the bus. Chips with RTI do not
|
||||
* perform snapshots, so don't bother with this test there.
|
||||
*/
|
||||
if ((ahd->features & AHD_RTI) == 0) {
|
||||
/*
|
||||
* If we're not still receiving SCSI data,
|
||||
* it is safe to allocate the S/G cache to
|
||||
* this FIFO.
|
||||
*/
|
||||
test DFCNTRL, SCSIEN jz idle_sgfetch_start;
|
||||
|
||||
/*
|
||||
* Switch to the other FIFO. Non-RTI chips
|
||||
* also have the "set mode" bug, so we must
|
||||
* disable interrupts during the switch.
|
||||
*/
|
||||
mvi SEQINTCTL, INTVEC1DSL;
|
||||
xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
|
||||
|
||||
/*
|
||||
* If the other FIFO needs loading, then it
|
||||
* must not have claimed the S/G cache yet
|
||||
* (SG_CACHE_AVAIL would have been cleared in
|
||||
* the orginal FIFO mode and we test this above).
|
||||
* Return to the idle loop so we can process the
|
||||
* FIFO not currently on the bus first.
|
||||
*/
|
||||
test SG_STATE, LOADING_NEEDED jz idle_sgfetch_okay;
|
||||
clr SEQINTCTL ret;
|
||||
idle_sgfetch_okay:
|
||||
xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
|
||||
clr SEQINTCTL;
|
||||
}
|
||||
|
||||
idle_sgfetch_start:
|
||||
/*
|
||||
* We fetch a "cacheline aligned" and sized amount of data
|
||||
* so we don't end up referencing a non-existant page.
|
||||
|
|
@ -1308,7 +1445,7 @@ service_fifo:
|
|||
mvi SGHCNT, SG_PREFETCH_CNT;
|
||||
if ((ahd->bugs & AHD_REG_SLOW_SETTLE_BUG) != 0) {
|
||||
/*
|
||||
* Need two instruction between "touches" of SGHADDR.
|
||||
* Need two instructions between "touches" of SGHADDR.
|
||||
*/
|
||||
nop;
|
||||
}
|
||||
|
|
@ -1658,7 +1795,7 @@ export seq_isr:
|
|||
* savepointer in the current FIFO. We do this so that
|
||||
* a pending CTXTDONE or SAVEPTR is visible in the active
|
||||
* FIFO. This status is the only way we can detect if we
|
||||
* have lost the race (e.g. host paused us) and our attepts
|
||||
* have lost the race (e.g. host paused us) and our attempts
|
||||
* to disable the channel occurred after all REQs were
|
||||
* already seen and acked (REQINIT never comes true).
|
||||
*/
|
||||
|
|
@ -1667,7 +1804,7 @@ export seq_isr:
|
|||
test DFCNTRL, DIRECTION jz interrupt_return;
|
||||
and DFCNTRL, ~SCSIEN;
|
||||
snapshot_wait_data_valid:
|
||||
test SEQINTSRC, (CTXTDONE|SAVEPTRS) jnz snapshot_data_valid;
|
||||
test SEQINTSRC, (CTXTDONE|SAVEPTRS) jnz interrupt_return;
|
||||
test SSTAT1, REQINIT jz snapshot_wait_data_valid;
|
||||
snapshot_data_valid:
|
||||
or DFCNTRL, SCSIEN;
|
||||
|
|
@ -1834,7 +1971,6 @@ pkt_saveptrs_check_status:
|
|||
dec SCB_FIFO_USE_COUNT;
|
||||
test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
|
||||
mvi DFFSXFRCTL, CLRCHN ret;
|
||||
END_CRITICAL;
|
||||
|
||||
/*
|
||||
* LAST_SEG_DONE status has been seen in the current FIFO.
|
||||
|
|
@ -1843,7 +1979,6 @@ END_CRITICAL;
|
|||
* Check for overrun and see if we can complete this command.
|
||||
*/
|
||||
pkt_last_seg_done:
|
||||
BEGIN_CRITICAL;
|
||||
/*
|
||||
* Mark transfer as completed.
|
||||
*/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -839,7 +839,7 @@ ahd_sync_qoutfifo(struct ahd_softc *ahd, int op)
|
|||
{
|
||||
ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
|
||||
/*offset*/0,
|
||||
/*len*/AHD_SCB_MAX * sizeof(uint16_t), op);
|
||||
/*len*/AHD_SCB_MAX * sizeof(struct ahd_completion), op);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
|
|
@ -871,8 +871,8 @@ ahd_check_cmdcmpltqueues(struct ahd_softc *ahd)
|
|||
ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
|
||||
/*offset*/ahd->qoutfifonext * sizeof(*ahd->qoutfifo),
|
||||
/*len*/sizeof(*ahd->qoutfifo), BUS_DMASYNC_POSTREAD);
|
||||
if ((ahd->qoutfifo[ahd->qoutfifonext]
|
||||
& QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag)
|
||||
if (ahd->qoutfifo[ahd->qoutfifonext].valid_tag
|
||||
== ahd->qoutfifonext_valid_tag)
|
||||
retval |= AHD_RUN_QOUTFIFO;
|
||||
#ifdef AHD_TARGET_MODE
|
||||
if ((ahd->flags & AHD_TARGETROLE) != 0
|
||||
|
|
|
|||
|
|
@ -1468,6 +1468,30 @@ ahd_linux_run_command(struct ahd_softc *ahd, struct ahd_linux_device *dev,
|
|||
if ((tstate->auto_negotiate & mask) != 0) {
|
||||
scb->flags |= SCB_AUTO_NEGOTIATE;
|
||||
scb->hscb->control |= MK_MESSAGE;
|
||||
} else if (cmd->cmnd[0] == INQUIRY
|
||||
&& (tinfo->curr.offset != 0
|
||||
|| tinfo->curr.width != MSG_EXT_WDTR_BUS_8_BIT
|
||||
|| tinfo->curr.ppr_options != 0)
|
||||
&& (tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)==0) {
|
||||
/*
|
||||
* The SCSI spec requires inquiry
|
||||
* commands to complete without
|
||||
* reporting unit attention conditions.
|
||||
* Because of this, an inquiry command
|
||||
* that occurs just after a device is
|
||||
* reset will result in a data phase
|
||||
* with mismatched negotiated rates.
|
||||
* The core already forces a renegotiation
|
||||
* for reset events that are visible to
|
||||
* our controller or that we initiate,
|
||||
* but a third party device reset or a
|
||||
* hot-plug insertion can still cause this
|
||||
* issue. Therefore, we force a re-negotiation
|
||||
* for every inquiry command unless we
|
||||
* are async.
|
||||
*/
|
||||
scb->flags |= SCB_NEGOTIATE;
|
||||
scb->hscb->control |= MK_MESSAGE;
|
||||
}
|
||||
|
||||
if ((dev->flags & (AHD_DEV_Q_TAGGED|AHD_DEV_Q_BASIC)) != 0) {
|
||||
|
|
@ -2058,6 +2082,7 @@ ahd_linux_queue_recovery_cmd(struct scsi_cmnd *cmd, scb_flag flag)
|
|||
int paused;
|
||||
int wait;
|
||||
int disconnected;
|
||||
int found;
|
||||
ahd_mode_state saved_modes;
|
||||
unsigned long flags;
|
||||
|
||||
|
|
@ -2176,7 +2201,8 @@ ahd_linux_queue_recovery_cmd(struct scsi_cmnd *cmd, scb_flag flag)
|
|||
last_phase = ahd_inb(ahd, LASTPHASE);
|
||||
saved_scbptr = ahd_get_scbptr(ahd);
|
||||
active_scbptr = saved_scbptr;
|
||||
if (disconnected && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0) {
|
||||
if (disconnected && ((last_phase != P_BUSFREE) ||
|
||||
(ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0)) {
|
||||
struct scb *bus_scb;
|
||||
|
||||
bus_scb = ahd_lookup_scb(ahd, active_scbptr);
|
||||
|
|
@ -2194,28 +2220,41 @@ ahd_linux_queue_recovery_cmd(struct scsi_cmnd *cmd, scb_flag flag)
|
|||
* bus or is in the disconnected state.
|
||||
*/
|
||||
saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
|
||||
if (last_phase != P_BUSFREE
|
||||
&& (SCB_GET_TAG(pending_scb) == active_scbptr
|
||||
if (SCB_GET_TAG(pending_scb) == active_scbptr
|
||||
|| (flag == SCB_DEVICE_RESET
|
||||
&& SCSIID_TARGET(ahd, saved_scsiid) == scmd_id(cmd)))) {
|
||||
&& SCSIID_TARGET(ahd, saved_scsiid) == scmd_id(cmd))) {
|
||||
|
||||
/*
|
||||
* We're active on the bus, so assert ATN
|
||||
* and hope that the target responds.
|
||||
*/
|
||||
pending_scb = ahd_lookup_scb(ahd, active_scbptr);
|
||||
pending_scb->flags |= SCB_RECOVERY_SCB|flag;
|
||||
pending_scb->flags |= SCB_RECOVERY_SCB|SCB_DEVICE_RESET;
|
||||
ahd_outb(ahd, MSG_OUT, HOST_MSG);
|
||||
ahd_outb(ahd, SCSISIGO, last_phase|ATNO);
|
||||
scmd_printk(KERN_INFO, cmd, "Device is active, asserting ATN\n");
|
||||
scmd_printk(KERN_INFO, cmd, "BDR message in message buffer\n");
|
||||
wait = TRUE;
|
||||
} else if (last_phase != P_BUSFREE
|
||||
&& ahd_inb(ahd, SCSIPHASE) == 0) {
|
||||
/*
|
||||
* SCB is not identified, there
|
||||
* is no pending REQ, and the sequencer
|
||||
* has not seen a busfree. Looks like
|
||||
* a stuck connection waiting to
|
||||
* go busfree. Reset the bus.
|
||||
*/
|
||||
found = ahd_reset_channel(ahd, cmd->device->channel + 'A',
|
||||
/*Initiate Reset*/TRUE);
|
||||
printf("%s: Issued Channel %c Bus Reset. "
|
||||
"%d SCBs aborted\n", ahd_name(ahd),
|
||||
cmd->device->channel + 'A', found);
|
||||
} else if (disconnected) {
|
||||
|
||||
/*
|
||||
* Actually re-queue this SCB in an attempt
|
||||
* to select the device before it reconnects.
|
||||
*/
|
||||
pending_scb->flags |= SCB_RECOVERY_SCB|SCB_ABORT;
|
||||
pending_scb->flags |= SCB_RECOVERY_SCB|flag;
|
||||
ahd_set_scbptr(ahd, SCB_GET_TAG(pending_scb));
|
||||
pending_scb->hscb->cdb_len = 0;
|
||||
pending_scb->hscb->task_attribute = 0;
|
||||
|
|
@ -2296,16 +2335,17 @@ done:
|
|||
timer.expires = jiffies + (5 * HZ);
|
||||
timer.function = ahd_linux_sem_timeout;
|
||||
add_timer(&timer);
|
||||
printf("Recovery code sleeping\n");
|
||||
printf("%s: Recovery code sleeping\n", ahd_name(ahd));
|
||||
down(&ahd->platform_data->eh_sem);
|
||||
printf("Recovery code awake\n");
|
||||
printf("%s: Recovery code awake\n", ahd_name(ahd));
|
||||
ret = del_timer_sync(&timer);
|
||||
if (ret == 0) {
|
||||
printf("Timer Expired\n");
|
||||
printf("%s: Timer Expired (active %d)\n",
|
||||
ahd_name(ahd), dev->active);
|
||||
retval = FAILED;
|
||||
}
|
||||
}
|
||||
ahd_unlock(ahd, &flags);
|
||||
ahd_unlock(ahd, &flags);
|
||||
return (retval);
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -2,8 +2,8 @@
|
|||
* DO NOT EDIT - This file is automatically generated
|
||||
* from the following source files:
|
||||
*
|
||||
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#94 $
|
||||
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $
|
||||
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#118 $
|
||||
* $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#75 $
|
||||
*/
|
||||
|
||||
#include "aic79xx_osm.h"
|
||||
|
|
@ -172,21 +172,6 @@ ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x0b, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = {
|
||||
{ "CLRSEQ_SPLTINT", 0x01, 0x01 },
|
||||
{ "CLRSEQ_PCIINT", 0x02, 0x02 },
|
||||
{ "CLRSEQ_SCSIINT", 0x04, 0x04 },
|
||||
{ "CLRSEQ_SEQINT", 0x08, 0x08 },
|
||||
{ "CLRSEQ_SWTMRTO", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_clrseqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(CLRSEQINTSTAT_parse_table, 5, "CLRSEQINTSTAT",
|
||||
0x0c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = {
|
||||
{ "SEQ_SPLTINT", 0x01, 0x01 },
|
||||
{ "SEQ_PCIINT", 0x02, 0x02 },
|
||||
|
|
@ -202,6 +187,21 @@ ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x0c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = {
|
||||
{ "CLRSEQ_SPLTINT", 0x01, 0x01 },
|
||||
{ "CLRSEQ_PCIINT", 0x02, 0x02 },
|
||||
{ "CLRSEQ_SCSIINT", 0x04, 0x04 },
|
||||
{ "CLRSEQ_SEQINT", 0x08, 0x08 },
|
||||
{ "CLRSEQ_SWTMRTO", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_clrseqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(CLRSEQINTSTAT_parse_table, 5, "CLRSEQINTSTAT",
|
||||
0x0c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_swtimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
|
@ -670,16 +670,16 @@ ahd_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_businitid_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_dlcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "BUSINITID",
|
||||
return (ahd_print_register(NULL, 0, "DLCOUNT",
|
||||
0x3c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_dlcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_businitid_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "DLCOUNT",
|
||||
return (ahd_print_register(NULL, 0, "BUSINITID",
|
||||
0x3c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
|
|
@ -859,21 +859,6 @@ ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x49, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SBLKCTL_parse_table[] = {
|
||||
{ "SELWIDE", 0x02, 0x02 },
|
||||
{ "ENAB20", 0x04, 0x04 },
|
||||
{ "ENAB40", 0x08, 0x08 },
|
||||
{ "DIAGLEDON", 0x40, 0x40 },
|
||||
{ "DIAGLEDEN", 0x80, 0x80 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SBLKCTL_parse_table, 5, "SBLKCTL",
|
||||
0x4a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = {
|
||||
{ "AUTO_MSGOUT_DE", 0x02, 0x02 },
|
||||
{ "ENDGFORMCHK", 0x04, 0x04 },
|
||||
|
|
@ -891,22 +876,19 @@ ahd_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x4a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
|
||||
{ "ARBDO", 0x01, 0x01 },
|
||||
{ "SPIORDY", 0x02, 0x02 },
|
||||
{ "OVERRUN", 0x04, 0x04 },
|
||||
{ "IOERR", 0x08, 0x08 },
|
||||
{ "SELINGO", 0x10, 0x10 },
|
||||
{ "SELDI", 0x20, 0x20 },
|
||||
{ "SELDO", 0x40, 0x40 },
|
||||
{ "TARGET", 0x80, 0x80 }
|
||||
static ahd_reg_parse_entry_t SBLKCTL_parse_table[] = {
|
||||
{ "SELWIDE", 0x02, 0x02 },
|
||||
{ "ENAB20", 0x04, 0x04 },
|
||||
{ "ENAB40", 0x08, 0x08 },
|
||||
{ "DIAGLEDON", 0x40, 0x40 },
|
||||
{ "DIAGLEDEN", 0x80, 0x80 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0",
|
||||
0x4b, regvalue, cur_col, wrap));
|
||||
return (ahd_print_register(SBLKCTL_parse_table, 5, "SBLKCTL",
|
||||
0x4a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CLRSINT0_parse_table[] = {
|
||||
|
|
@ -926,6 +908,24 @@ ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x4b, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
|
||||
{ "ARBDO", 0x01, 0x01 },
|
||||
{ "SPIORDY", 0x02, 0x02 },
|
||||
{ "OVERRUN", 0x04, 0x04 },
|
||||
{ "IOERR", 0x08, 0x08 },
|
||||
{ "SELINGO", 0x10, 0x10 },
|
||||
{ "SELDI", 0x20, 0x20 },
|
||||
{ "SELDO", 0x40, 0x40 },
|
||||
{ "TARGET", 0x80, 0x80 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0",
|
||||
0x4b, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SIMODE0_parse_table[] = {
|
||||
{ "ENARBDO", 0x01, 0x01 },
|
||||
{ "ENSPIORDY", 0x02, 0x02 },
|
||||
|
|
@ -998,6 +998,19 @@ ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x4d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SIMODE2_parse_table[] = {
|
||||
{ "ENDMADONE", 0x01, 0x01 },
|
||||
{ "ENSDONE", 0x02, 0x02 },
|
||||
{ "ENWIDE_RES", 0x04, 0x04 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_simode2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SIMODE2_parse_table, 3, "SIMODE2",
|
||||
0x4d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CLRSINT2_parse_table[] = {
|
||||
{ "CLRDMADONE", 0x01, 0x01 },
|
||||
{ "CLRSDONE", 0x02, 0x02 },
|
||||
|
|
@ -1012,19 +1025,6 @@ ahd_clrsint2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x4d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SIMODE2_parse_table[] = {
|
||||
{ "ENDMADONE", 0x01, 0x01 },
|
||||
{ "ENSDONE", 0x02, 0x02 },
|
||||
{ "ENWIDE_RES", 0x04, 0x04 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_simode2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SIMODE2_parse_table, 3, "SIMODE2",
|
||||
0x4d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t PERRDIAG_parse_table[] = {
|
||||
{ "DTERR", 0x01, 0x01 },
|
||||
{ "DGFORMERR", 0x02, 0x02 },
|
||||
|
|
@ -1220,21 +1220,6 @@ ahd_clrsint3_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x53, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOMODE0_parse_table[] = {
|
||||
{ "ENLQOTCRC", 0x01, 0x01 },
|
||||
{ "ENLQOATNPKT", 0x02, 0x02 },
|
||||
{ "ENLQOATNLQ", 0x04, 0x04 },
|
||||
{ "ENLQOSTOPT2", 0x08, 0x08 },
|
||||
{ "ENLQOTARGSCBPERR", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(LQOMODE0_parse_table, 5, "LQOMODE0",
|
||||
0x54, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = {
|
||||
{ "LQOTCRC", 0x01, 0x01 },
|
||||
{ "LQOATNPKT", 0x02, 0x02 },
|
||||
|
|
@ -1265,6 +1250,36 @@ ahd_clrlqoint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x54, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOMODE0_parse_table[] = {
|
||||
{ "ENLQOTCRC", 0x01, 0x01 },
|
||||
{ "ENLQOATNPKT", 0x02, 0x02 },
|
||||
{ "ENLQOATNLQ", 0x04, 0x04 },
|
||||
{ "ENLQOSTOPT2", 0x08, 0x08 },
|
||||
{ "ENLQOTARGSCBPERR", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(LQOMODE0_parse_table, 5, "LQOMODE0",
|
||||
0x54, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOMODE1_parse_table[] = {
|
||||
{ "ENLQOPHACHGINPKT", 0x01, 0x01 },
|
||||
{ "ENLQOBUSFREE", 0x02, 0x02 },
|
||||
{ "ENLQOBADQAS", 0x04, 0x04 },
|
||||
{ "ENLQOSTOPI2", 0x08, 0x08 },
|
||||
{ "ENLQOINITSCBPERR", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(LQOMODE1_parse_table, 5, "LQOMODE1",
|
||||
0x55, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = {
|
||||
{ "LQOPHACHGINPKT", 0x01, 0x01 },
|
||||
{ "LQOBUSFREE", 0x02, 0x02 },
|
||||
|
|
@ -1295,21 +1310,6 @@ ahd_clrlqoint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x55, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOMODE1_parse_table[] = {
|
||||
{ "ENLQOPHACHGINPKT", 0x01, 0x01 },
|
||||
{ "ENLQOBUSFREE", 0x02, 0x02 },
|
||||
{ "ENLQOBADQAS", 0x04, 0x04 },
|
||||
{ "ENLQOSTOPI2", 0x08, 0x08 },
|
||||
{ "ENLQOINITSCBPERR", 0x10, 0x10 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(LQOMODE1_parse_table, 5, "LQOMODE1",
|
||||
0x55, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = {
|
||||
{ "LQOSTOP0", 0x01, 0x01 },
|
||||
{ "LQOPHACHGOUTPKT", 0x02, 0x02 },
|
||||
|
|
@ -1594,6 +1594,13 @@ ahd_annexcol_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x65, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "ANNEXDAT",
|
||||
0x66, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SCSCHKN_parse_table[] = {
|
||||
{ "LSTSGCLRDIS", 0x01, 0x01 },
|
||||
{ "SHVALIDSTDIS", 0x02, 0x02 },
|
||||
|
|
@ -1611,13 +1618,6 @@ ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x66, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "ANNEXDAT",
|
||||
0x66, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_iownid_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
|
@ -1728,16 +1728,16 @@ ahd_pll400ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_pll400cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_unfairness_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "PLL400CNT0",
|
||||
return (ahd_print_register(NULL, 0, "UNFAIRNESS",
|
||||
0x6e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_unfairness_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_pll400cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "UNFAIRNESS",
|
||||
return (ahd_print_register(NULL, 0, "PLL400CNT0",
|
||||
0x6e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
|
|
@ -1787,13 +1787,6 @@ ahd_hodmaen_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x7a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SGHADDR",
|
||||
0x7c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
|
@ -1802,10 +1795,10 @@ ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SGHCNT",
|
||||
0x84, regvalue, cur_col, wrap));
|
||||
return (ahd_print_register(NULL, 0, "SGHADDR",
|
||||
0x7c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
|
|
@ -1815,6 +1808,13 @@ ahd_scbhcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x84, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SGHCNT",
|
||||
0x84, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = {
|
||||
{ "WR_DFTHRSH_MIN", 0x00, 0x70 },
|
||||
{ "RD_DFTHRSH_MIN", 0x00, 0x07 },
|
||||
|
|
@ -1950,17 +1950,6 @@ ahd_nsenable_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x91, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHRXMSG1_parse_table[] = {
|
||||
{ "CBNUM", 0xff, 0xff }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_dchrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(DCHRXMSG1_parse_table, 1, "DCHRXMSG1",
|
||||
0x91, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CMCRXMSG1_parse_table[] = {
|
||||
{ "CBNUM", 0xff, 0xff }
|
||||
};
|
||||
|
|
@ -1972,6 +1961,17 @@ ahd_cmcrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x91, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHRXMSG1_parse_table[] = {
|
||||
{ "CBNUM", 0xff, 0xff }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_dchrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(DCHRXMSG1_parse_table, 1, "DCHRXMSG1",
|
||||
0x91, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHRXMSG2_parse_table[] = {
|
||||
{ "MINDEX", 0xff, 0xff }
|
||||
};
|
||||
|
|
@ -1983,17 +1983,6 @@ ahd_dchrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x92, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OVLYRXMSG2_parse_table[] = {
|
||||
{ "MINDEX", 0xff, 0xff }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ovlyrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(OVLYRXMSG2_parse_table, 1, "OVLYRXMSG2",
|
||||
0x92, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CMCRXMSG2_parse_table[] = {
|
||||
{ "MINDEX", 0xff, 0xff }
|
||||
};
|
||||
|
|
@ -2012,6 +2001,17 @@ ahd_ost_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x92, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OVLYRXMSG2_parse_table[] = {
|
||||
{ "MINDEX", 0xff, 0xff }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ovlyrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(OVLYRXMSG2_parse_table, 1, "OVLYRXMSG2",
|
||||
0x92, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHRXMSG3_parse_table[] = {
|
||||
{ "MCLASS", 0x0f, 0x0f }
|
||||
};
|
||||
|
|
@ -2023,6 +2023,17 @@ ahd_dchrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x93, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OVLYRXMSG3_parse_table[] = {
|
||||
{ "MCLASS", 0x0f, 0x0f }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ovlyrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(OVLYRXMSG3_parse_table, 1, "OVLYRXMSG3",
|
||||
0x93, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CMCRXMSG3_parse_table[] = {
|
||||
{ "MCLASS", 0x0f, 0x0f }
|
||||
};
|
||||
|
|
@ -2051,17 +2062,6 @@ ahd_pcixctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x93, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OVLYRXMSG3_parse_table[] = {
|
||||
{ "MCLASS", 0x0f, 0x0f }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ovlyrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(OVLYRXMSG3_parse_table, 1, "OVLYRXMSG3",
|
||||
0x93, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_ovlyseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
|
@ -2070,16 +2070,16 @@ ahd_ovlyseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_cmcseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_dchseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CMCSEQBCNT",
|
||||
return (ahd_print_register(NULL, 0, "DCHSEQBCNT",
|
||||
0x94, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_dchseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_cmcseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "DCHSEQBCNT",
|
||||
return (ahd_print_register(NULL, 0, "CMCSEQBCNT",
|
||||
0x94, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
|
|
@ -2101,24 +2101,6 @@ ahd_cmcspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x96, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t OVLYSPLTSTAT0_parse_table[] = {
|
||||
{ "RXSPLTRSP", 0x01, 0x01 },
|
||||
{ "RXSCEMSG", 0x02, 0x02 },
|
||||
{ "RXOVRUN", 0x04, 0x04 },
|
||||
{ "CNTNOTCMPLT", 0x08, 0x08 },
|
||||
{ "SCDATBUCKET", 0x10, 0x10 },
|
||||
{ "SCADERR", 0x20, 0x20 },
|
||||
{ "SCBCERR", 0x40, 0x40 },
|
||||
{ "STAETERM", 0x80, 0x80 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ovlyspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(OVLYSPLTSTAT0_parse_table, 8, "OVLYSPLTSTAT0",
|
||||
0x96, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = {
|
||||
{ "RXSPLTRSP", 0x01, 0x01 },
|
||||
{ "RXSCEMSG", 0x02, 0x02 },
|
||||
|
|
@ -2137,15 +2119,22 @@ ahd_dchspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x96, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
|
||||
{ "RXDATABUCKET", 0x01, 0x01 }
|
||||
static ahd_reg_parse_entry_t OVLYSPLTSTAT0_parse_table[] = {
|
||||
{ "RXSPLTRSP", 0x01, 0x01 },
|
||||
{ "RXSCEMSG", 0x02, 0x02 },
|
||||
{ "RXOVRUN", 0x04, 0x04 },
|
||||
{ "CNTNOTCMPLT", 0x08, 0x08 },
|
||||
{ "SCDATBUCKET", 0x10, 0x10 },
|
||||
{ "SCADERR", 0x20, 0x20 },
|
||||
{ "SCBCERR", 0x40, 0x40 },
|
||||
{ "STAETERM", 0x80, 0x80 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_ovlyspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(DCHSPLTSTAT1_parse_table, 1, "DCHSPLTSTAT1",
|
||||
0x97, regvalue, cur_col, wrap));
|
||||
return (ahd_print_register(OVLYSPLTSTAT0_parse_table, 8, "OVLYSPLTSTAT0",
|
||||
0x96, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CMCSPLTSTAT1_parse_table[] = {
|
||||
|
|
@ -2170,6 +2159,17 @@ ahd_ovlyspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x97, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
|
||||
{ "RXDATABUCKET", 0x01, 0x01 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(DCHSPLTSTAT1_parse_table, 1, "DCHSPLTSTAT1",
|
||||
0x97, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SGRXMSG0_parse_table[] = {
|
||||
{ "CFNUM", 0x07, 0x07 },
|
||||
{ "CDNUM", 0xf8, 0xf8 }
|
||||
|
|
@ -2320,6 +2320,17 @@ ahd_sgspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x9e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = {
|
||||
{ "RXDATABUCKET", 0x01, 0x01 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SGSPLTSTAT1_parse_table, 1, "SGSPLTSTAT1",
|
||||
0x9f, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SFUNCT_parse_table[] = {
|
||||
{ "TEST_NUM", 0x0f, 0x0f },
|
||||
{ "TEST_GROUP", 0xf0, 0xf0 }
|
||||
|
|
@ -2332,17 +2343,6 @@ ahd_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x9f, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = {
|
||||
{ "RXDATABUCKET", 0x01, 0x01 }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SGSPLTSTAT1_parse_table, 1, "SGSPLTSTAT1",
|
||||
0x9f, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = {
|
||||
{ "DPR", 0x01, 0x01 },
|
||||
{ "TWATERR", 0x02, 0x02 },
|
||||
|
|
@ -2537,16 +2537,16 @@ ahd_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_ccscbadr_bk_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CCSCBADDR",
|
||||
return (ahd_print_register(NULL, 0, "CCSCBADR_BK",
|
||||
0xac, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_ccscbadr_bk_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CCSCBADR_BK",
|
||||
return (ahd_print_register(NULL, 0, "CCSCBADDR",
|
||||
0xac, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
|
|
@ -2566,22 +2566,6 @@ ahd_cmc_rambist_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xad, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
|
||||
{ "CCSGRESET", 0x01, 0x01 },
|
||||
{ "SG_FETCH_REQ", 0x02, 0x02 },
|
||||
{ "CCSGENACK", 0x08, 0x08 },
|
||||
{ "SG_CACHE_AVAIL", 0x10, 0x10 },
|
||||
{ "CCSGDONE", 0x80, 0x80 },
|
||||
{ "CCSGEN", 0x0c, 0x0c }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL",
|
||||
0xad, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
|
||||
{ "CCSCBRESET", 0x01, 0x01 },
|
||||
{ "CCSCBDIR", 0x04, 0x04 },
|
||||
|
|
@ -2598,6 +2582,22 @@ ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xad, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
|
||||
{ "CCSGRESET", 0x01, 0x01 },
|
||||
{ "SG_FETCH_REQ", 0x02, 0x02 },
|
||||
{ "CCSGENACK", 0x08, 0x08 },
|
||||
{ "SG_CACHE_AVAIL", 0x10, 0x10 },
|
||||
{ "CCSGDONE", 0x80, 0x80 },
|
||||
{ "CCSGEN", 0x0c, 0x0c }
|
||||
};
|
||||
|
||||
int
|
||||
ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL",
|
||||
0xad, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
|
@ -2840,13 +2840,6 @@ ahd_wrtbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xc7, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_dfptrs_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "DFPTRS",
|
||||
0xc8, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_rcvrbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
|
@ -2855,10 +2848,10 @@ ahd_rcvrbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_dfbkptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_dfptrs_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "DFBKPTR",
|
||||
0xc9, regvalue, cur_col, wrap));
|
||||
return (ahd_print_register(NULL, 0, "DFPTRS",
|
||||
0xc8, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
|
|
@ -2868,6 +2861,13 @@ ahd_skewcalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xc9, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_dfbkptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "DFBKPTR",
|
||||
0xc9, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DFDBCTL_parse_table[] = {
|
||||
{ "DFF_RAMBIST_EN", 0x01, 0x01 },
|
||||
{ "DFF_RAMBIST_DONE", 0x02, 0x02 },
|
||||
|
|
@ -3001,6 +3001,13 @@ ahd_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xe4, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_brkaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "BRKADDR0",
|
||||
0xe6, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t BRKADDR1_parse_table[] = {
|
||||
{ "BRKDIS", 0x80, 0x80 }
|
||||
};
|
||||
|
|
@ -3012,13 +3019,6 @@ ahd_brkaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xe6, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_brkaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "BRKADDR0",
|
||||
0xe6, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
|
@ -3068,13 +3068,6 @@ ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xf2, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CURADDR",
|
||||
0xf4, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_intvec1_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
|
@ -3083,10 +3076,10 @@ ahd_intvec1_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
}
|
||||
|
||||
int
|
||||
ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INTVEC2_ADDR",
|
||||
0xf6, regvalue, cur_col, wrap));
|
||||
return (ahd_print_register(NULL, 0, "CURADDR",
|
||||
0xf4, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
|
|
@ -3096,6 +3089,13 @@ ahd_lastaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0xf6, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INTVEC2_ADDR",
|
||||
0xf6, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_longjmp_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
|
|
@ -3173,25 +3173,46 @@ ahd_complete_dma_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
|||
0x12c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_complete_dma_scb_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL",
|
||||
0x12e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_complete_on_qfreeze_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD",
|
||||
0x130, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "QFREEZE_COUNT",
|
||||
0x12e, regvalue, cur_col, wrap));
|
||||
0x132, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_kernel_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT",
|
||||
0x134, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SAVED_MODE",
|
||||
0x130, regvalue, cur_col, wrap));
|
||||
0x136, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "MSG_OUT",
|
||||
0x131, regvalue, cur_col, wrap));
|
||||
0x137, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = {
|
||||
|
|
@ -3211,7 +3232,7 @@ int
|
|||
ahd_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS",
|
||||
0x132, regvalue, cur_col, wrap));
|
||||
0x138, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
|
||||
|
|
@ -3230,21 +3251,21 @@ int
|
|||
ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
|
||||
0x133, regvalue, cur_col, wrap));
|
||||
0x139, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SAVED_SCSIID",
|
||||
0x134, regvalue, cur_col, wrap));
|
||||
0x13a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SAVED_LUN",
|
||||
0x135, regvalue, cur_col, wrap));
|
||||
0x13b, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t LASTPHASE_parse_table[] = {
|
||||
|
|
@ -3267,42 +3288,42 @@ int
|
|||
ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(LASTPHASE_parse_table, 13, "LASTPHASE",
|
||||
0x136, regvalue, cur_col, wrap));
|
||||
0x13c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_qoutfifo_entry_valid_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG",
|
||||
0x137, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SHARED_DATA_ADDR",
|
||||
0x138, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR",
|
||||
0x13c, regvalue, cur_col, wrap));
|
||||
0x13d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "KERNEL_TQINPOS",
|
||||
0x140, regvalue, cur_col, wrap));
|
||||
0x13e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "TQINPOS",
|
||||
0x141, regvalue, cur_col, wrap));
|
||||
0x13f, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "SHARED_DATA_ADDR",
|
||||
0x140, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR",
|
||||
0x144, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t ARG_1_parse_table[] = {
|
||||
|
|
@ -3320,21 +3341,21 @@ int
|
|||
ahd_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(ARG_1_parse_table, 8, "ARG_1",
|
||||
0x142, regvalue, cur_col, wrap));
|
||||
0x148, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "ARG_2",
|
||||
0x143, regvalue, cur_col, wrap));
|
||||
0x149, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "LAST_MSG",
|
||||
0x144, regvalue, cur_col, wrap));
|
||||
0x14a, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
|
||||
|
|
@ -3350,14 +3371,14 @@ int
|
|||
ahd_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE",
|
||||
0x145, regvalue, cur_col, wrap));
|
||||
0x14b, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_initiator_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INITIATOR_TAG",
|
||||
0x146, regvalue, cur_col, wrap));
|
||||
0x14c, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
static ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
|
||||
|
|
@ -3369,63 +3390,63 @@ int
|
|||
ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(SEQ_FLAGS2_parse_table, 2, "SEQ_FLAGS2",
|
||||
0x147, regvalue, cur_col, wrap));
|
||||
0x14d, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_allocfifo_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR",
|
||||
0x148, regvalue, cur_col, wrap));
|
||||
0x14e, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_int_coalescing_timer_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INT_COALESCING_TIMER",
|
||||
0x14a, regvalue, cur_col, wrap));
|
||||
0x150, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_int_coalescing_maxcmds_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS",
|
||||
0x14c, regvalue, cur_col, wrap));
|
||||
0x152, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_int_coalescing_mincmds_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS",
|
||||
0x14d, regvalue, cur_col, wrap));
|
||||
0x153, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_cmds_pending_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CMDS_PENDING",
|
||||
0x14e, regvalue, cur_col, wrap));
|
||||
0x154, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_int_coalescing_cmdcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT",
|
||||
0x150, regvalue, cur_col, wrap));
|
||||
0x156, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_local_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX",
|
||||
0x151, regvalue, cur_col, wrap));
|
||||
0x157, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
ahd_cmdsize_table_print(u_int regvalue, u_int *cur_col, u_int wrap)
|
||||
{
|
||||
return (ahd_print_register(NULL, 0, "CMDSIZE_TABLE",
|
||||
0x152, regvalue, cur_col, wrap));
|
||||
0x158, regvalue, cur_col, wrap));
|
||||
}
|
||||
|
||||
int
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Reference in New Issue