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[ARM] Remove compatibility layer for ARM irqs 

set_irq_chipdata -> set_irq_chip_data
get_irq_chipdata -> get_irq_chip_data
do_level_IRQ -> handle_level_irq
do_edge_IRQ -> handle_edge_irq
do_simple_IRQ -> handle_simple_irq
irqdesc -> irq_desc
irqchip -> irq_chip

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2006-11-23 11:41:32 +00:00 committed by Russell King
parent 127e477e0c
commit 10dd5ce28d
58 changed files with 277 additions and 289 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/common/gic.c
View File

@ -160,7 +160,7 @@ void __init gic_dist_init(void __iomem *base)
*/
for (i = 29; i < max_irq; i++) {
set_irq_chip(i, &gic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}

84
arch/arm/common/locomo.c
View File

@ -163,11 +163,11 @@ static struct locomo_dev_info locomo_devices[] = {
#define LOCOMO_IRQ_LT_START (IRQ_LOCOMO_LT)
#define LOCOMO_IRQ_SPI_START (IRQ_LOCOMO_SPI_RFR)
static void locomo_handler(unsigned int irq, struct irqdesc *desc)
static void locomo_handler(unsigned int irq, struct irq_desc *desc)
{
int req, i;
struct irqdesc *d;
void __iomem *mapbase = get_irq_chipdata(irq);
struct irq_desc *d;
void __iomem *mapbase = get_irq_chip_data(irq);
/* Acknowledge the parent IRQ */
desc->chip->ack(irq);
@ -194,7 +194,7 @@ static void locomo_ack_irq(unsigned int irq)
static void locomo_mask_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_ICR);
r &= ~(0x0010 << (irq - LOCOMO_IRQ_START));
@ -203,7 +203,7 @@ static void locomo_mask_irq(unsigned int irq)
static void locomo_unmask_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_ICR);
r |= (0x0010 << (irq - LOCOMO_IRQ_START));
@ -217,10 +217,10 @@ static struct irq_chip locomo_chip = {
.unmask = locomo_unmask_irq,
};
static void locomo_key_handler(unsigned int irq, struct irqdesc *desc)
static void locomo_key_handler(unsigned int irq, struct irq_desc *desc)
{
struct irqdesc *d;
void __iomem *mapbase = get_irq_chipdata(irq);
struct irq_desc *d;
void __iomem *mapbase = get_irq_chip_data(irq);
if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) {
d = irq_desc + LOCOMO_IRQ_KEY_START;
@ -230,7 +230,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc)
static void locomo_key_ack_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START));
@ -239,7 +239,7 @@ static void locomo_key_ack_irq(unsigned int irq)
static void locomo_key_mask_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@ -248,7 +248,7 @@ static void locomo_key_mask_irq(unsigned int irq)
static void locomo_key_unmask_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@ -262,11 +262,11 @@ static struct irq_chip locomo_key_chip = {
.unmask = locomo_key_unmask_irq,
};
static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc)
static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc)
{
int req, i;
struct irqdesc *d;
void __iomem *mapbase = get_irq_chipdata(irq);
struct irq_desc *d;
void __iomem *mapbase = get_irq_chip_data(irq);
req = locomo_readl(mapbase + LOCOMO_GIR) &
locomo_readl(mapbase + LOCOMO_GPD) &
@ -285,7 +285,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc)
static void locomo_gpio_ack_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_GWE);
r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@ -302,7 +302,7 @@ static void locomo_gpio_ack_irq(unsigned int irq)
static void locomo_gpio_mask_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_GIE);
r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@ -311,7 +311,7 @@ static void locomo_gpio_mask_irq(unsigned int irq)
static void locomo_gpio_unmask_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_GIE);
r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@ -325,10 +325,10 @@ static struct irq_chip locomo_gpio_chip = {
.unmask = locomo_gpio_unmask_irq,
};
static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc)
static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc)
{
struct irqdesc *d;
void __iomem *mapbase = get_irq_chipdata(irq);
struct irq_desc *d;
void __iomem *mapbase = get_irq_chip_data(irq);
if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) {
d = irq_desc + LOCOMO_IRQ_LT_START;
@ -338,7 +338,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc)
static void locomo_lt_ack_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_LTINT);
r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START));
@ -347,7 +347,7 @@ static void locomo_lt_ack_irq(unsigned int irq)
static void locomo_lt_mask_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_LTINT);
r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START));
@ -356,7 +356,7 @@ static void locomo_lt_mask_irq(unsigned int irq)
static void locomo_lt_unmask_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_LTINT);
r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START));
@ -370,11 +370,11 @@ static struct irq_chip locomo_lt_chip = {
.unmask = locomo_lt_unmask_irq,
};
static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc)
static void locomo_spi_handler(unsigned int irq, struct irq_desc *desc)
{
int req, i;
struct irqdesc *d;
void __iomem *mapbase = get_irq_chipdata(irq);
struct irq_desc *d;
void __iomem *mapbase = get_irq_chip_data(irq);
req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F;
if (req) {
@ -391,7 +391,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc)
static void locomo_spi_ack_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE);
r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@ -408,7 +408,7 @@ static void locomo_spi_ack_irq(unsigned int irq)
static void locomo_spi_mask_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@ -417,7 +417,7 @@ static void locomo_spi_mask_irq(unsigned int irq)
static void locomo_spi_unmask_irq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned int r;
r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@ -440,55 +440,55 @@ static void locomo_setup_irq(struct locomo *lchip)
* Install handler for IRQ_LOCOMO_HW.
*/
set_irq_type(lchip->irq, IRQT_FALLING);
set_irq_chipdata(lchip->irq, irqbase);
set_irq_chip_data(lchip->irq, irqbase);
set_irq_chained_handler(lchip->irq, locomo_handler);
/* Install handlers for IRQ_LOCOMO_*_BASE */
set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip);
set_irq_chipdata(IRQ_LOCOMO_KEY_BASE, irqbase);
set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase);
set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler);
set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE);
set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip);
set_irq_chipdata(IRQ_LOCOMO_GPIO_BASE, irqbase);
set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase);
set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler);
set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE);
set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip);
set_irq_chipdata(IRQ_LOCOMO_LT_BASE, irqbase);
set_irq_chip_data(IRQ_LOCOMO_LT_BASE, irqbase);
set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler);
set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE);
set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip);
set_irq_chipdata(IRQ_LOCOMO_SPI_BASE, irqbase);
set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase);
set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler);
set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE);
/* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */
set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip);
set_irq_chipdata(LOCOMO_IRQ_KEY_START, irqbase);
set_irq_handler(LOCOMO_IRQ_KEY_START, do_edge_IRQ);
set_irq_chip_data(LOCOMO_IRQ_KEY_START, irqbase);
set_irq_handler(LOCOMO_IRQ_KEY_START, handle_edge_irq);
set_irq_flags(LOCOMO_IRQ_KEY_START, IRQF_VALID | IRQF_PROBE);
/* install handlers for IRQ_LOCOMO_GPIO_BASE generated interrupts */
for (irq = LOCOMO_IRQ_GPIO_START; irq < LOCOMO_IRQ_GPIO_START + 16; irq++) {
set_irq_chip(irq, &locomo_gpio_chip);
set_irq_chipdata(irq, irqbase);
set_irq_handler(irq, do_edge_IRQ);
set_irq_chip_data(irq, irqbase);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/* install handlers for IRQ_LOCOMO_LT_BASE generated interrupts */
set_irq_chip(LOCOMO_IRQ_LT_START, &locomo_lt_chip);
set_irq_chipdata(LOCOMO_IRQ_LT_START, irqbase);
set_irq_handler(LOCOMO_IRQ_LT_START, do_edge_IRQ);
set_irq_chip_data(LOCOMO_IRQ_LT_START, irqbase);
set_irq_handler(LOCOMO_IRQ_LT_START, handle_edge_irq);
set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE);
/* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */
for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) {
set_irq_chip(irq, &locomo_spi_chip);
set_irq_chipdata(irq, irqbase);
set_irq_handler(irq, do_edge_IRQ);
set_irq_chip_data(irq, irqbase);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}

30
arch/arm/common/sa1111.c
View File

@ -147,7 +147,7 @@ void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *ho
* will call us again if there are more interrupts to process.
*/
static void
sa1111_irq_handler(unsigned int irq, struct irqdesc *desc)
sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int stat0, stat1, i;
void __iomem *base = get_irq_data(irq);
@ -187,7 +187,7 @@ static void sa1111_ack_irq(unsigned int irq)
static void sa1111_mask_lowirq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ie0;
ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
@ -197,7 +197,7 @@ static void sa1111_mask_lowirq(unsigned int irq)
static void sa1111_unmask_lowirq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ie0;
ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
@ -215,7 +215,7 @@ static void sa1111_unmask_lowirq(unsigned int irq)
static int sa1111_retrigger_lowirq(unsigned int irq)
{
unsigned int mask = SA1111_IRQMASK_LO(irq);
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ip0;
int i;
@ -236,7 +236,7 @@ static int sa1111_retrigger_lowirq(unsigned int irq)
static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
{
unsigned int mask = SA1111_IRQMASK_LO(irq);
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ip0;
if (flags == IRQT_PROBE)
@ -259,7 +259,7 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
static int sa1111_wake_lowirq(unsigned int irq, unsigned int on)
{
unsigned int mask = SA1111_IRQMASK_LO(irq);
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long we0;
we0 = sa1111_readl(mapbase + SA1111_WAKEEN0);
@ -284,7 +284,7 @@ static struct irq_chip sa1111_low_chip = {
static void sa1111_mask_highirq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ie1;
ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
@ -294,7 +294,7 @@ static void sa1111_mask_highirq(unsigned int irq)
static void sa1111_unmask_highirq(unsigned int irq)
{
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ie1;
ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
@ -312,7 +312,7 @@ static void sa1111_unmask_highirq(unsigned int irq)
static int sa1111_retrigger_highirq(unsigned int irq)
{
unsigned int mask = SA1111_IRQMASK_HI(irq);
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ip1;
int i;
@ -333,7 +333,7 @@ static int sa1111_retrigger_highirq(unsigned int irq)
static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
{
unsigned int mask = SA1111_IRQMASK_HI(irq);
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ip1;
if (flags == IRQT_PROBE)
@ -356,7 +356,7 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
static int sa1111_wake_highirq(unsigned int irq, unsigned int on)
{
unsigned int mask = SA1111_IRQMASK_HI(irq);
void __iomem *mapbase = get_irq_chipdata(irq);
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long we1;
we1 = sa1111_readl(mapbase + SA1111_WAKEEN1);
@ -410,15 +410,15 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
set_irq_chip(irq, &sa1111_low_chip);
set_irq_chipdata(irq, irqbase);
set_irq_handler(irq, do_edge_IRQ);
set_irq_chip_data(irq, irqbase);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
set_irq_chip(irq, &sa1111_high_chip);
set_irq_chipdata(irq, irqbase);
set_irq_handler(irq, do_edge_IRQ);
set_irq_chip_data(irq, irqbase);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}

8
arch/arm/common/vic.c
View File

@ -27,14 +27,14 @@
static void vic_mask_irq(unsigned int irq)
{
void __iomem *base = get_irq_chipdata(irq);
void __iomem *base = get_irq_chip_data(irq);
irq &= 31;
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
}
static void vic_unmask_irq(unsigned int irq)
{
void __iomem *base = get_irq_chipdata(irq);
void __iomem *base = get_irq_chip_data(irq);
irq &= 31;
writel(1 << irq, base + VIC_INT_ENABLE);
}
@ -88,10 +88,10 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
unsigned int irq = irq_start + i;
set_irq_chip(irq, &vic_chip);
set_irq_chipdata(irq, base);
set_irq_chip_data(irq, base);
if (vic_sources & (1 << i)) {
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}

10
arch/arm/kernel/ecard.c
View File

@ -529,7 +529,7 @@ static void ecard_dump_irq_state(void)
}
}
static void ecard_check_lockup(struct irqdesc *desc)
static void ecard_check_lockup(struct irq_desc *desc)
{
static unsigned long last;
static int lockup;
@ -567,7 +567,7 @@ static void ecard_check_lockup(struct irqdesc *desc)
}
static void
ecard_irq_handler(unsigned int irq, struct irqdesc *desc)
ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
{
ecard_t *ec;
int called = 0;
@ -585,7 +585,7 @@ ecard_irq_handler(unsigned int irq, struct irqdesc *desc)
pending = ecard_default_ops.irqpending(ec);
if (pending) {
struct irqdesc *d = irq_desc + ec->irq;
struct irq_desc *d = irq_desc + ec->irq;
desc_handle_irq(ec->irq, d);
called ++;
}
@ -609,7 +609,7 @@ static unsigned char first_set[] =
};
static void
ecard_irqexp_handler(unsigned int irq, struct irqdesc *desc)
ecard_irqexp_handler(unsigned int irq, struct irq_desc *desc)
{
const unsigned int statusmask = 15;
unsigned int status;
@ -1022,7 +1022,7 @@ ecard_probe(int slot, card_type_t type)
if (slot < 8) {
ec->irq = 32 + slot;
set_irq_chip(ec->irq, &ecard_chip);
set_irq_handler(ec->irq, do_level_IRQ);
set_irq_handler(ec->irq, handle_level_irq);
set_irq_flags(ec->irq, IRQF_VALID);
}

8
arch/arm/kernel/irq.c
View File

@ -112,7 +112,7 @@ static struct irq_desc bad_irq_desc = {
asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
struct irqdesc *desc = irq_desc + irq;
struct irq_desc *desc = irq_desc + irq;
/*
* Some hardware gives randomly wrong interrupts. Rather
@ -134,7 +134,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
void set_irq_flags(unsigned int irq, unsigned int iflags)
{
struct irqdesc *desc;
struct irq_desc *desc;
unsigned long flags;
if (irq >= NR_IRQS) {
@ -171,7 +171,7 @@ void __init init_IRQ(void)
#ifdef CONFIG_HOTPLUG_CPU
static void route_irq(struct irqdesc *desc, unsigned int irq, unsigned int cpu)
static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
{
pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu);
@ -190,7 +190,7 @@ void migrate_irqs(void)
unsigned int i, cpu = smp_processor_id();
for (i = 0; i < NR_IRQS; i++) {
struct irqdesc *desc = irq_desc + i;
struct irq_desc *desc = irq_desc + i;
if (desc->cpu == cpu) {
unsigned int newcpu = any_online_cpu(desc->affinity);

4
arch/arm/mach-aaec2000/core.c
View File

@ -82,7 +82,7 @@ static void aaec2000_int_unmask(unsigned int irq)
IRQ_INTENS |= (1 << irq);
}
static struct irqchip aaec2000_irq_chip = {
static struct irq_chip aaec2000_irq_chip = {
.ack = aaec2000_int_ack,
.mask = aaec2000_int_mask,
.unmask = aaec2000_int_unmask,
@ -93,7 +93,7 @@ void __init aaec2000_init_irq(void)
unsigned int i;
for (i = 0; i < NR_IRQS; i++) {
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_chip(i, &aaec2000_irq_chip);
set_irq_flags(i, IRQF_VALID);
}

8
arch/arm/mach-at91rm9200/gpio.c
View File

@ -332,10 +332,10 @@ static struct irq_chip gpio_irqchip = {
.set_wake = gpio_irq_set_wake,
};
static void gpio_irq_handler(unsigned irq, struct irqdesc *desc)
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
unsigned pin;
struct irqdesc *gpio;
struct irq_desc *gpio;
void __iomem *pio;
u32 isr;
@ -396,7 +396,7 @@ void __init at91_gpio_irq_setup(void)
__raw_writel(~0, controller + PIO_IDR);
set_irq_data(id, (void *) pin);
set_irq_chipdata(id, controller);
set_irq_chip_data(id, controller);
for (i = 0; i < 32; i++, pin++) {
/*
@ -404,7 +404,7 @@ void __init at91_gpio_irq_setup(void)
* shorter, and the AIC handles interupts sanely.
*/
set_irq_chip(pin, &gpio_irqchip);
set_irq_handler(pin, do_simple_IRQ);
set_irq_handler(pin, handle_simple_irq);
set_irq_flags(pin, IRQF_VALID);
}

2
arch/arm/mach-at91rm9200/irq.c
View File

@ -139,7 +139,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
set_irq_chip(i, &at91_aic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */

8
arch/arm/mach-clps711x/irq.c
View File

@ -63,7 +63,7 @@ static void int1_unmask(unsigned int irq)
clps_writel(intmr1, INTMR1);
}
static struct irqchip int1_chip = {
static struct irq_chip int1_chip = {
.ack = int1_ack,
.mask = int1_mask,
.unmask = int1_unmask,
@ -100,7 +100,7 @@ static void int2_unmask(unsigned int irq)
clps_writel(intmr2, INTMR2);
}
static struct irqchip int2_chip = {
static struct irq_chip int2_chip = {
.ack = int2_ack,
.mask = int2_mask,
.unmask = int2_unmask,
@ -112,12 +112,12 @@ void __init clps711x_init_irq(void)
for (i = 0; i < NR_IRQS; i++) {
if (INT1_IRQS & (1 << i)) {
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_chip(i, &int1_chip);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
if (INT2_IRQS & (1 << i)) {
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_chip(i, &int2_chip);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}

28
arch/arm/mach-clps7500/core.c
View File

@ -57,7 +57,7 @@ static void cl7500_unmask_irq_a(unsigned int irq)
iomd_writeb(val | mask, IOMD_IRQMASKA);
}
static struct irqchip clps7500_a_chip = {
static struct irq_chip clps7500_a_chip = {
.ack = cl7500_ack_irq_a,
.mask = cl7500_mask_irq_a,
.unmask = cl7500_unmask_irq_a,
@ -81,7 +81,7 @@ static void cl7500_unmask_irq_b(unsigned int irq)
iomd_writeb(val | mask, IOMD_IRQMASKB);
}
static struct irqchip clps7500_b_chip = {
static struct irq_chip clps7500_b_chip = {
.ack = cl7500_mask_irq_b,
.mask = cl7500_mask_irq_b,
.unmask = cl7500_unmask_irq_b,
@ -105,7 +105,7 @@ static void cl7500_unmask_irq_c(unsigned int irq)
iomd_writeb(val | mask, IOMD_IRQMASKC);
}
static struct irqchip clps7500_c_chip = {
static struct irq_chip clps7500_c_chip = {
.ack = cl7500_mask_irq_c,
.mask = cl7500_mask_irq_c,
.unmask = cl7500_unmask_irq_c,
@ -129,7 +129,7 @@ static void cl7500_unmask_irq_d(unsigned int irq)
iomd_writeb(val | mask, IOMD_IRQMASKD);
}
static struct irqchip clps7500_d_chip = {
static struct irq_chip clps7500_d_chip = {
.ack = cl7500_mask_irq_d,
.mask = cl7500_mask_irq_d,
.unmask = cl7500_unmask_irq_d,
@ -153,7 +153,7 @@ static void cl7500_unmask_irq_dma(unsigned int irq)
iomd_writeb(val | mask, IOMD_DMAMASK);
}
static struct irqchip clps7500_dma_chip = {
static struct irq_chip clps7500_dma_chip = {
.ack = cl7500_mask_irq_dma,
.mask = cl7500_mask_irq_dma,
.unmask = cl7500_unmask_irq_dma,
@ -177,7 +177,7 @@ static void cl7500_unmask_irq_fiq(unsigned int irq)
iomd_writeb(val | mask, IOMD_FIQMASK);
}
static struct irqchip clps7500_fiq_chip = {
static struct irq_chip clps7500_fiq_chip = {
.ack = cl7500_mask_irq_fiq,
.mask = cl7500_mask_irq_fiq,
.unmask = cl7500_unmask_irq_fiq,
@ -187,7 +187,7 @@ static void cl7500_no_action(unsigned int irq)
{
}
static struct irqchip clps7500_no_chip = {
static struct irq_chip clps7500_no_chip = {
.ack = cl7500_no_action,
.mask = cl7500_no_action,
.unmask = cl7500_no_action,
@ -214,43 +214,43 @@ static void __init clps7500_init_irq(void)
switch (irq) {
case 0 ... 7:
set_irq_chip(irq, &clps7500_a_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 8 ... 15:
set_irq_chip(irq, &clps7500_b_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 16 ... 22:
set_irq_chip(irq, &clps7500_dma_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 24 ... 31:
set_irq_chip(irq, &clps7500_c_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 40 ... 47:
set_irq_chip(irq, &clps7500_d_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 48 ... 55:
set_irq_chip(irq, &clps7500_no_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 64 ... 72:
set_irq_chip(irq, &clps7500_fiq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
}

4
arch/arm/mach-ebsa110/core.c
View File

@ -45,7 +45,7 @@ static void ebsa110_unmask_irq(unsigned int irq)
__raw_writeb(1 << irq, IRQ_MSET);
}
static struct irqchip ebsa110_irq_chip = {
static struct irq_chip ebsa110_irq_chip = {
.ack = ebsa110_mask_irq,
.mask = ebsa110_mask_irq,
.unmask = ebsa110_unmask_irq,
@ -67,7 +67,7 @@ static void __init ebsa110_init_irq(void)
for (irq = 0; irq < NR_IRQS; irq++) {
set_irq_chip(irq, &ebsa110_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}

6
arch/arm/mach-ep93xx/core.c
View File

@ -245,7 +245,7 @@ EXPORT_SYMBOL(gpio_line_set);
* EP93xx IRQ handling
*************************************************************************/
static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
unsigned char status;
int i;
@ -335,7 +335,7 @@ static int ep93xx_gpio_ab_irq_type(unsigned int irq, unsigned int type)
return 0;
}
static struct irqchip ep93xx_gpio_ab_irq_chip = {
static struct irq_chip ep93xx_gpio_ab_irq_chip = {
.ack = ep93xx_gpio_ab_irq_mask_ack,
.mask = ep93xx_gpio_ab_irq_mask,
.unmask = ep93xx_gpio_ab_irq_unmask,
@ -352,7 +352,7 @@ void __init ep93xx_init_irq(void)
for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) {
set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);

4
arch/arm/mach-footbridge/common.c
View File

@ -78,7 +78,7 @@ static void fb_unmask_irq(unsigned int irq)
*CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)];
}
static struct irqchip fb_chip = {
static struct irq_chip fb_chip = {
.ack = fb_mask_irq,
.mask = fb_mask_irq,
.unmask = fb_unmask_irq,
@ -96,7 +96,7 @@ static void __init __fb_init_irq(void)
for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
set_irq_chip(irq, &fb_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}

10
arch/arm/mach-footbridge/isa-irq.c
View File

@ -49,7 +49,7 @@ static void isa_unmask_pic_lo_irq(unsigned int irq)
outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO);
}
static struct irqchip isa_lo_chip = {
static struct irq_chip isa_lo_chip = {
.ack = isa_ack_pic_lo_irq,
.mask = isa_mask_pic_lo_irq,
.unmask = isa_unmask_pic_lo_irq,
@ -78,14 +78,14 @@ static void isa_unmask_pic_hi_irq(unsigned int irq)
outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI);
}
static struct irqchip isa_hi_chip = {
static struct irq_chip isa_hi_chip = {
.ack = isa_ack_pic_hi_irq,
.mask = isa_mask_pic_hi_irq,
.unmask = isa_unmask_pic_hi_irq,
};
static void
isa_irq_handler(unsigned int irq, struct irqdesc *desc)
isa_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
@ -150,13 +150,13 @@ void __init isa_init_irq(unsigned int host_irq)
if (host_irq != (unsigned int)-1) {
for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
set_irq_chip(irq, &isa_lo_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
set_irq_chip(irq, &isa_hi_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}

22
arch/arm/mach-h720x/common.c
View File

@ -101,7 +101,7 @@ static void inline unmask_gpio_irq(u32 irq)
static void
h720x_gpio_handler(unsigned int mask, unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
desc = irq_desc + irq;
@ -117,7 +117,7 @@ h720x_gpio_handler(unsigned int mask, unsigned int irq,
}
static void
h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@ -128,7 +128,7 @@ h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
}
static void
h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
@ -138,7 +138,7 @@ h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
}
static void
h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@ -149,7 +149,7 @@ h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
}
static void
h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@ -161,7 +161,7 @@ h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
#ifdef CONFIG_CPU_H7202
static void
h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@ -172,13 +172,13 @@ h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
}
#endif
static struct irqchip h720x_global_chip = {
static struct irq_chip h720x_global_chip = {
.ack = mask_global_irq,
.mask = mask_global_irq,
.unmask = unmask_global_irq,
};
static struct irqchip h720x_gpio_chip = {
static struct irq_chip h720x_gpio_chip = {
.ack = ack_gpio_irq,
.mask = mask_gpio_irq,
.unmask = unmask_gpio_irq,
@ -203,14 +203,14 @@ void __init h720x_init_irq (void)
/* Initialize global IRQ's, fast path */
for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
set_irq_chip(irq, &h720x_global_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/* Initialize multiplexed IRQ's, slow path */
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
set_irq_chip(irq, &h720x_gpio_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
@ -221,7 +221,7 @@ void __init h720x_init_irq (void)
#ifdef CONFIG_CPU_H7202
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
set_irq_chip(irq, &h720x_gpio_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);

6
arch/arm/mach-h720x/cpu-h7202.c
View File

@ -106,7 +106,7 @@ static struct platform_device *devices[] __initdata = {
* we have to handle all timer interrupts in one place.
*/
static void
h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@ -162,7 +162,7 @@ static void inline unmask_timerx_irq (u32 irq)
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
}
static struct irqchip h7202_timerx_chip = {
static struct irq_chip h7202_timerx_chip = {
.ack = mask_timerx_irq,
.mask = mask_timerx_irq,
.unmask = unmask_timerx_irq,
@ -202,7 +202,7 @@ void __init h7202_init_irq (void)
irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
mask_timerx_irq(irq);
set_irq_chip(irq, &h7202_timerx_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);

14
arch/arm/mach-imx/irq.c
View File

@ -146,7 +146,7 @@ imx_gpio_unmask_irq(unsigned int irq)
static void
imx_gpio_handler(unsigned int mask, unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
desc = irq_desc + irq;
while (mask) {
@ -161,7 +161,7 @@ imx_gpio_handler(unsigned int mask, unsigned int irq,
}
static void
imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@ -171,7 +171,7 @@ imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
}
static void
imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@ -181,7 +181,7 @@ imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
}
static void
imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@ -191,7 +191,7 @@ imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
}
static void
imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@ -230,13 +230,13 @@ imx_init_irq(void)
for (irq = 0; irq < IMX_IRQS; irq++) {
set_irq_chip(irq, &imx_internal_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
set_irq_chip(irq, &imx_gpio_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID);
}

2
arch/arm/mach-integrator/integrator_ap.c
View File

@ -183,7 +183,7 @@ static void __init ap_init_irq(void)
for (i = 0; i < NR_IRQS; i++) {
if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) {
set_irq_chip(i, &sc_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}

8
arch/arm/mach-integrator/integrator_cp.c
View File

@ -202,7 +202,7 @@ static struct irq_chip sic_chip = {
};
static void
sic_handle_irq(unsigned int irq, struct irqdesc *desc)
sic_handle_irq(unsigned int irq, struct irq_desc *desc)
{
unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
@ -238,7 +238,7 @@ static void __init intcp_init_irq(void)
if (i == 29)
break;
set_irq_chip(i, &pic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
@ -247,7 +247,7 @@ static void __init intcp_init_irq(void)
for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
set_irq_chip(i, &cic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
@ -256,7 +256,7 @@ static void __init intcp_init_irq(void)
for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
set_irq_chip(i, &sic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}

2
arch/arm/mach-iop32x/irq.c
View File

@ -70,7 +70,7 @@ void __init iop32x_init_irq(void)
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &ext_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}

2
arch/arm/mach-iop33x/irq.c
View File

@ -121,7 +121,7 @@ void __init iop33x_init_irq(void)
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}

20
arch/arm/mach-ixp2000/core.c
View File

@ -308,7 +308,7 @@ EXPORT_SYMBOL(gpio_line_config);
/*************************************************************************
* IRQ handling IXP2000
*************************************************************************/
static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc)
static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
{
int i;
unsigned long status = *IXP2000_GPIO_INST;
@ -373,7 +373,7 @@ static void ixp2000_GPIO_irq_unmask(unsigned int irq)
ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}
static struct irqchip ixp2000_GPIO_irq_chip = {
static struct irq_chip ixp2000_GPIO_irq_chip = {
.ack = ixp2000_GPIO_irq_mask_ack,
.mask = ixp2000_GPIO_irq_mask,
.unmask = ixp2000_GPIO_irq_unmask,
@ -401,7 +401,7 @@ static void ixp2000_pci_irq_unmask(unsigned int irq)
/*
* Error interrupts. These are used extensively by the microengine drivers
*/
static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc)
static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
{
int i;
unsigned long status = *IXP2000_IRQ_ERR_STATUS;
@ -426,13 +426,13 @@ static void ixp2000_err_irq_unmask(unsigned int irq)
(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
}
static struct irqchip ixp2000_err_irq_chip = {
static struct irq_chip ixp2000_err_irq_chip = {
.ack = ixp2000_err_irq_mask,
.mask = ixp2000_err_irq_mask,
.unmask = ixp2000_err_irq_unmask
};
static struct irqchip ixp2000_pci_irq_chip = {
static struct irq_chip ixp2000_pci_irq_chip = {
.ack = ixp2000_pci_irq_mask,
.mask = ixp2000_pci_irq_mask,
.unmask = ixp2000_pci_irq_unmask
@ -448,7 +448,7 @@ static void ixp2000_irq_unmask(unsigned int irq)
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
}
static struct irqchip ixp2000_irq_chip = {
static struct irq_chip ixp2000_irq_chip = {
.ack = ixp2000_irq_mask,
.mask = ixp2000_irq_mask,
.unmask = ixp2000_irq_unmask
@ -484,7 +484,7 @@ void __init ixp2000_init_irq(void)
for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
set_irq_chip(irq, &ixp2000_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
} else set_irq_flags(irq, 0);
}
@ -493,7 +493,7 @@ void __init ixp2000_init_irq(void)
if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
IXP2000_VALID_ERR_IRQ_MASK) {
set_irq_chip(irq, &ixp2000_err_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
else
@ -503,7 +503,7 @@ void __init ixp2000_init_irq(void)
for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
@ -516,7 +516,7 @@ void __init ixp2000_init_irq(void)
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
set_irq_chip(irq, &ixp2000_pci_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}

8
arch/arm/mach-ixp2000/ixdp2x00.c
View File

@ -106,7 +106,7 @@ static void ixdp2x00_irq_unmask(unsigned int irq)
ixp2000_release_slowport(&old_cfg);
}
static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
{
volatile u32 ex_interrupt = 0;
static struct slowport_cfg old_cfg;
@ -129,7 +129,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
for(i = 0; i < board_irq_count; i++) {
if(ex_interrupt & (1 << i)) {
struct irqdesc *cpld_desc;
struct irq_desc *cpld_desc;
int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
cpld_desc = irq_desc + cpld_irq;
desc_handle_irq(cpld_irq, cpld_desc);
@ -139,7 +139,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
desc->chip->unmask(irq);
}
static struct irqchip ixdp2x00_cpld_irq_chip = {
static struct irq_chip ixdp2x00_cpld_irq_chip = {
.ack = ixdp2x00_irq_mask,
.mask = ixdp2x00_irq_mask,
.unmask = ixdp2x00_irq_unmask
@ -162,7 +162,7 @@ void ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long
for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}

8
arch/arm/mach-ixp2000/ixdp2x01.c
View File

@ -63,7 +63,7 @@ static void ixdp2x01_irq_unmask(unsigned int irq)
static u32 valid_irq_mask;
static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
{
u32 ex_interrupt;
int i;
@ -79,7 +79,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
if (ex_interrupt & (1 << i)) {
struct irqdesc *cpld_desc;
struct irq_desc *cpld_desc;
int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
cpld_desc = irq_desc + cpld_irq;
desc_handle_irq(cpld_irq, cpld_desc);
@ -89,7 +89,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
desc->chip->unmask(irq);
}
static struct irqchip ixdp2x01_irq_chip = {
static struct irq_chip ixdp2x01_irq_chip = {
.mask = ixdp2x01_irq_mask,
.ack = ixdp2x01_irq_mask,
.unmask = ixdp2x01_irq_unmask
@ -119,7 +119,7 @@ void __init ixdp2x01_init_irq(void)
for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
if (irq & valid_irq_mask) {
set_irq_chip(irq, &ixdp2x01_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
} else {
set_irq_flags(irq, 0);

16
arch/arm/mach-ixp23xx/core.c
View File

@ -224,14 +224,14 @@ static void ixp23xx_irq_edge_unmask(unsigned int irq)
*intr_reg |= (1 << (irq % 32));
}
static struct irqchip ixp23xx_irq_level_chip = {
static struct irq_chip ixp23xx_irq_level_chip = {
.ack = ixp23xx_irq_mask,
.mask = ixp23xx_irq_mask,
.unmask = ixp23xx_irq_level_unmask,
.set_type = ixp23xx_irq_set_type
};
static struct irqchip ixp23xx_irq_edge_chip = {
static struct irq_chip ixp23xx_irq_edge_chip = {
.ack = ixp23xx_irq_ack,
.mask = ixp23xx_irq_mask,
.unmask = ixp23xx_irq_edge_unmask,
@ -251,11 +251,11 @@ static void ixp23xx_pci_irq_unmask(unsigned int irq)
/*
* TODO: Should this just be done at ASM level?
*/
static void pci_handler(unsigned int irq, struct irqdesc *desc)
static void pci_handler(unsigned int irq, struct irq_desc *desc)
{
u32 pci_interrupt;
unsigned int irqno;
struct irqdesc *int_desc;
struct irq_desc *int_desc;
pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
@ -276,7 +276,7 @@ static void pci_handler(unsigned int irq, struct irqdesc *desc)
desc->chip->unmask(irq);
}
static struct irqchip ixp23xx_pci_irq_chip = {
static struct irq_chip ixp23xx_pci_irq_chip = {
.ack = ixp23xx_pci_irq_mask,
.mask = ixp23xx_pci_irq_mask,
.unmask = ixp23xx_pci_irq_unmask
@ -287,11 +287,11 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
switch (type) {
case IXP23XX_IRQ_LEVEL:
set_irq_chip(irq, &ixp23xx_irq_level_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
break;
case IXP23XX_IRQ_EDGE:
set_irq_chip(irq, &ixp23xx_irq_edge_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
break;
}
set_irq_flags(irq, IRQF_VALID);
@ -322,7 +322,7 @@ void __init ixp23xx_init_irq(void)
for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
set_irq_chip(irq, &ixp23xx_pci_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}

16
arch/arm/mach-ixp23xx/ixdp2351.c
View File

@ -60,7 +60,7 @@ static void ixdp2351_inta_unmask(unsigned int irq)
*IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
}
static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
{
u16 ex_interrupt =
*IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
@ -70,7 +70,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
if (ex_interrupt & (1 << i)) {
struct irqdesc *cpld_desc;
struct irq_desc *cpld_desc;
int cpld_irq =
IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
cpld_desc = irq_desc + cpld_irq;
@ -81,7 +81,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
desc->chip->unmask(irq);
}
static struct irqchip ixdp2351_inta_chip = {
static struct irq_chip ixdp2351_inta_chip = {
.ack = ixdp2351_inta_mask,
.mask = ixdp2351_inta_mask,
.unmask = ixdp2351_inta_unmask
@ -97,7 +97,7 @@ static void ixdp2351_intb_unmask(unsigned int irq)
*IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
}
static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
{
u16 ex_interrupt =
*IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
@ -107,7 +107,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
if (ex_interrupt & (1 << i)) {
struct irqdesc *cpld_desc;
struct irq_desc *cpld_desc;
int cpld_irq =
IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
cpld_desc = irq_desc + cpld_irq;
@ -118,7 +118,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
desc->chip->unmask(irq);
}
static struct irqchip ixdp2351_intb_chip = {
static struct irq_chip ixdp2351_intb_chip = {
.ack = ixdp2351_intb_mask,
.mask = ixdp2351_intb_mask,
.unmask = ixdp2351_intb_unmask
@ -142,7 +142,7 @@ void ixdp2351_init_irq(void)
irq++) {
if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_chip(irq, &ixdp2351_inta_chip);
}
}
@ -153,7 +153,7 @@ void ixdp2351_init_irq(void)
irq++) {
if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_chip(irq, &ixdp2351_intb_chip);
}
}

4
arch/arm/mach-ixp4xx/common.c
View File

@ -195,7 +195,7 @@ static void ixp4xx_irq_unmask(unsigned int irq)
*IXP4XX_ICMR |= (1 << irq);
}
static struct irqchip ixp4xx_irq_chip = {
static struct irq_chip ixp4xx_irq_chip = {
.name = "IXP4xx",
.ack = ixp4xx_irq_ack,
.mask = ixp4xx_irq_mask,
@ -224,7 +224,7 @@ void __init ixp4xx_init_irq(void)
/* Default to all level triggered */
for(i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &ixp4xx_irq_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}

4
arch/arm/mach-l7200/core.c
View File

@ -55,7 +55,7 @@ static void l7200_unmask_irq(unsigned int irq)
IRQ_ENABLE = 1 << irq;
}
static struct irqchip l7200_irq_chip = {
static struct irq_chip l7200_irq_chip = {
.ack = l7200_mask_irq,
.mask = l7200_mask_irq,
.unmask = l7200_unmask_irq
@ -71,7 +71,7 @@ static void __init l7200_init_irq(void)
for (irq = 0; irq < NR_IRQS; irq++) {
set_irq_chip(irq, &l7200_irq_chip);
set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
}
init_FIQ();

4
arch/arm/mach-lh7a40x/arch-kev7a400.c
View File

@ -71,7 +71,7 @@ static struct irq_chip kev7a400_cpld_chip = {
};
static void kev7a400_cpld_handler (unsigned int irq, struct irqdesc *desc)
static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
{
u32 mask = CPLD_LATCHED_INTS;
irq = IRQ_KEV7A400_CPLD;
@ -88,7 +88,7 @@ void __init lh7a40x_init_board_irq (void)
for (irq = IRQ_KEV7A400_CPLD;
irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) {
set_irq_chip (irq, &kev7a400_cpld_chip);
set_irq_handler (irq, do_edge_IRQ);
set_irq_handler (irq, handle_edge_irq);
set_irq_flags (irq, IRQF_VALID);
}
set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);

4
arch/arm/mach-lh7a40x/arch-lpd7a40x.c
View File

@ -207,7 +207,7 @@ static struct irq_chip lpd7a40x_cpld_chip = {
.unmask = lh7a40x_unmask_cpld_irq,
};
static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc)
static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
{
unsigned int mask = CPLD_INTERRUPTS;
@ -279,7 +279,7 @@ void __init lh7a40x_init_board_irq (void)
for (irq = IRQ_BOARD_START;
irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
set_irq_chip (irq, &lpd7a40x_cpld_chip);
set_irq_handler (irq, do_level_IRQ);
set_irq_handler (irq, handle_level_irq);
set_irq_flags (irq, IRQF_VALID);
}

4
arch/arm/mach-lh7a40x/irq-kev7a400.c
View File

@ -51,7 +51,7 @@ irq_chip lh7a400_cpld_chip = {
};
static void
lh7a400_cpld_handler (unsigned int irq, struct irqdesc *desc)
lh7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
{
u32 mask = CPLD_LATCHED_INTS;
irq = IRQ_KEV_7A400_CPLD;
@ -71,7 +71,7 @@ lh7a400_init_board_irq (void)
for (irq = IRQ_KEV7A400_CPLD;
irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) {
set_irq_chip (irq, &lh7a400_cpld_chip);
set_irq_handler (irq, do_edge_IRQ);
set_irq_handler (irq, handle_edge_irq);
set_irq_flags (irq, IRQF_VALID);
}
set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);

4
arch/arm/mach-lh7a40x/irq-lh7a400.c
View File

@ -74,11 +74,11 @@ void __init lh7a400_init_irq (void)
case IRQ_GPIO6INTR:
case IRQ_GPIO7INTR:
set_irq_chip (irq, &lh7a400_gpio_chip);
set_irq_handler (irq, do_level_IRQ); /* OK default */
set_irq_handler (irq, handle_level_irq); /* OK default */
break;
default:
set_irq_chip (irq, &lh7a400_internal_chip);
set_irq_handler (irq, do_level_IRQ);
set_irq_handler (irq, handle_level_irq);
}
set_irq_flags (irq, IRQF_VALID);
}

4
arch/arm/mach-lh7a40x/irq-lh7a404.c
View File

@ -161,13 +161,13 @@ void __init lh7a404_init_irq (void)
set_irq_chip (irq, irq < 32
? &lh7a404_gpio_vic1_chip
: &lh7a404_gpio_vic2_chip);
set_irq_handler (irq, do_level_IRQ); /* OK default */
set_irq_handler (irq, handle_level_irq); /* OK default */
break;
default:
set_irq_chip (irq, irq < 32
? &lh7a404_vic1_chip
: &lh7a404_vic2_chip);
set_irq_handler (irq, do_level_IRQ);
set_irq_handler (irq, handle_level_irq);
}
set_irq_flags (irq, IRQF_VALID);
}

4
arch/arm/mach-lh7a40x/irq-lpd7a40x.c
View File

@ -57,7 +57,7 @@ static struct irq_chip lh7a40x_cpld_chip = {
.unmask = lh7a40x_unmask_cpld_irq,
};
static void lh7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc)
static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
{
unsigned int mask = CPLD_INTERRUPTS;
@ -118,7 +118,7 @@ void __init lh7a40x_init_board_irq (void)
for (irq = IRQ_BOARD_START;
irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
set_irq_chip (irq, &lh7a40x_cpld_chip);
set_irq_handler (irq, do_edge_IRQ);
set_irq_handler (irq, handle_edge_irq);
set_irq_flags (irq, IRQF_VALID);
}

6
arch/arm/mach-netx/generic.c
View File

@ -69,7 +69,7 @@ static struct platform_device *devices[] __initdata = {
#endif
static void
netx_hif_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
unsigned int stat;
@ -160,7 +160,7 @@ netx_hif_unmask_irq(unsigned int _irq)
DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq);
}
static struct irqchip netx_hif_chip = {
static struct irq_chip netx_hif_chip = {
.ack = netx_hif_ack_irq,
.mask = netx_hif_mask_irq,
.unmask = netx_hif_unmask_irq,
@ -175,7 +175,7 @@ void __init netx_init_irq(void)
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
set_irq_chip(irq, &netx_hif_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}

6
arch/arm/mach-omap1/fpga.c
View File

@ -84,9 +84,9 @@ static void fpga_mask_ack_irq(unsigned int irq)
fpga_ack_irq(irq);
}
void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc)
void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
{
struct irqdesc *d;
struct irq_desc *d;
u32 stat;
int fpga_irq;
@ -168,7 +168,7 @@ void omap1510_fpga_init_irq(void)
set_irq_chip(i, &omap_fpga_irq);
}
set_irq_handler(i, do_edge_IRQ);
set_irq_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}

2
arch/arm/mach-omap1/irq.c
View File

@ -229,7 +229,7 @@ void __init omap_init_irq(void)
omap_irq_set_cfg(j, 0, 0, irq_trigger);
set_irq_chip(j, &omap_irq_chip);
set_irq_handler(j, do_level_IRQ);
set_irq_handler(j, handle_level_irq);
set_irq_flags(j, IRQF_VALID);
}
}

2
arch/arm/mach-omap2/irq.c
View File

@ -130,7 +130,7 @@ void __init omap_init_irq(void)
for (i = 0; i < nr_irqs; i++) {
set_irq_chip(i, &omap_irq_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}

10
arch/arm/mach-pnx4008/irq.c
View File

@ -59,22 +59,22 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
case IRQT_RISING:
__raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
break;
case IRQT_FALLING:
__raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
break;
case IRQT_LOW:
__raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
break;
case IRQT_HIGH:
__raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
break;
/* IRQT_BOTHEDGE is not supported */
@ -85,7 +85,7 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
return 0;
}
static struct irqchip pnx4008_irq_chip = {
static struct irq_chip pnx4008_irq_chip = {
.ack = pnx4008_mask_ack_irq,
.mask = pnx4008_mask_irq,
.unmask = pnx4008_unmask_irq,

10
arch/arm/mach-pxa/irq.c
View File

@ -143,7 +143,7 @@ static struct irq_chip pxa_low_gpio_chip = {
* Demux handler for GPIO>=2 edge detect interrupts
*/
static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc)
static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int mask;
int loop;
@ -286,27 +286,27 @@ void __init pxa_init_irq(void)
for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
set_irq_chip(irq, &pxa_internal_chip_low);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
#if PXA_INTERNAL_IRQS > 32
for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
set_irq_chip(irq, &pxa_internal_chip_high);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
#endif
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
set_irq_chip(irq, &pxa_low_gpio_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
set_irq_chip(irq, &pxa_muxed_gpio_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}

4
arch/arm/mach-pxa/lpd270.c
View File

@ -75,7 +75,7 @@ static struct irq_chip lpd270_irq_chip = {
.unmask = lpd270_unmask_irq,
};
static void lpd270_irq_handler(unsigned int irq, struct irqdesc *desc)
static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned long pending;
@ -105,7 +105,7 @@ static void __init lpd270_init_irq(void)
/* setup extra LogicPD PXA270 irqs */
for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
set_irq_chip(irq, &lpd270_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);

4
arch/arm/mach-pxa/lubbock.c
View File

@ -85,7 +85,7 @@ static struct irq_chip lubbock_irq_chip = {
.unmask = lubbock_unmask_irq,
};
static void lubbock_irq_handler(unsigned int irq, struct irqdesc *desc)
static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
do {
@ -108,7 +108,7 @@ static void __init lubbock_init_irq(void)
/* setup extra lubbock irqs */
for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
set_irq_chip(irq, &lubbock_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}

4
arch/arm/mach-pxa/mainstone.c
View File

@ -71,7 +71,7 @@ static struct irq_chip mainstone_irq_chip = {
.unmask = mainstone_unmask_irq,
};
static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc)
static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
do {
@ -94,7 +94,7 @@ static void __init mainstone_init_irq(void)
/* setup extra Mainstone irqs */
for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
set_irq_chip(irq, &mainstone_irq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
else

14
arch/arm/mach-rpc/irq.c
View File

@ -34,7 +34,7 @@ static void iomd_unmask_irq_a(unsigned int irq)
iomd_writeb(val | mask, IOMD_IRQMASKA);
}
static struct irqchip iomd_a_chip = {
static struct irq_chip iomd_a_chip = {
.ack = iomd_ack_irq_a,
.mask = iomd_mask_irq_a,
.unmask = iomd_unmask_irq_a,
@ -58,7 +58,7 @@ static void iomd_unmask_irq_b(unsigned int irq)
iomd_writeb(val | mask, IOMD_IRQMASKB);
}
static struct irqchip iomd_b_chip = {
static struct irq_chip iomd_b_chip = {
.ack = iomd_mask_irq_b,
.mask = iomd_mask_irq_b,
.unmask = iomd_unmask_irq_b,
@ -82,7 +82,7 @@ static void iomd_unmask_irq_dma(unsigned int irq)
iomd_writeb(val | mask, IOMD_DMAMASK);
}
static struct irqchip iomd_dma_chip = {
static struct irq_chip iomd_dma_chip = {
.ack = iomd_mask_irq_dma,
.mask = iomd_mask_irq_dma,
.unmask = iomd_unmask_irq_dma,
@ -106,7 +106,7 @@ static void iomd_unmask_irq_fiq(unsigned int irq)
iomd_writeb(val | mask, IOMD_FIQMASK);
}
static struct irqchip iomd_fiq_chip = {
static struct irq_chip iomd_fiq_chip = {
.ack = iomd_mask_irq_fiq,
.mask = iomd_mask_irq_fiq,
.unmask = iomd_unmask_irq_fiq,
@ -134,19 +134,19 @@ void __init rpc_init_irq(void)
switch (irq) {
case 0 ... 7:
set_irq_chip(irq, &iomd_a_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 8 ... 15:
set_irq_chip(irq, &iomd_b_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 16 ... 21:
set_irq_chip(irq, &iomd_dma_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;

8
arch/arm/mach-s3c2410/bast-irq.c
View File

@ -88,7 +88,7 @@ bast_pc104_mask(unsigned int irqno)
static void
bast_pc104_maskack(unsigned int irqno)
{
struct irqdesc *desc = irq_desc + IRQ_ISA;
struct irq_desc *desc = irq_desc + IRQ_ISA;
bast_pc104_mask(irqno);
desc->chip->ack(IRQ_ISA);
@ -104,7 +104,7 @@ bast_pc104_unmask(unsigned int irqno)
__raw_writeb(temp, BAST_VA_PC104_IRQMASK);
}
static struct irqchip bast_pc104_chip = {
static struct irq_chip bast_pc104_chip = {
.mask = bast_pc104_mask,
.unmask = bast_pc104_unmask,
.ack = bast_pc104_maskack
@ -112,7 +112,7 @@ static struct irqchip bast_pc104_chip = {
static void
bast_irq_pc104_demux(unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
unsigned int stat;
unsigned int irqno;
@ -157,7 +157,7 @@ static __init int bast_irq_init(void)
unsigned int irqno = bast_pc104_irqs[i];
set_irq_chip(irqno, &bast_pc104_chip);
set_irq_handler(irqno, do_level_IRQ);
set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}

48
arch/arm/mach-s3c2410/irq.c
View File

@ -180,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno)
__raw_writel(mask, S3C2410_INTMSK);
}
struct irqchip s3c_irq_level_chip = {
struct irq_chip s3c_irq_level_chip = {
.name = "s3c-level",
.ack = s3c_irq_maskack,
.mask = s3c_irq_mask,
@ -188,7 +188,7 @@ struct irqchip s3c_irq_level_chip = {
.set_wake = s3c_irq_wake
};
static struct irqchip s3c_irq_chip = {
static struct irq_chip s3c_irq_chip = {
.name = "s3c",
.ack = s3c_irq_ack,
.mask = s3c_irq_mask,
@ -344,7 +344,7 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
return 0;
}
static struct irqchip s3c_irqext_chip = {
static struct irq_chip s3c_irqext_chip = {
.name = "s3c-ext",
.mask = s3c_irqext_mask,
.unmask = s3c_irqext_unmask,
@ -353,7 +353,7 @@ static struct irqchip s3c_irqext_chip = {
.set_wake = s3c_irqext_wake
};
static struct irqchip s3c_irq_eint0t4 = {
static struct irq_chip s3c_irq_eint0t4 = {
.name = "s3c-ext0",
.ack = s3c_irq_ack,
.mask = s3c_irq_mask,
@ -390,7 +390,7 @@ s3c_irq_uart0_ack(unsigned int irqno)
s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
}
static struct irqchip s3c_irq_uart0 = {
static struct irq_chip s3c_irq_uart0 = {
.name = "s3c-uart0",
.mask = s3c_irq_uart0_mask,
.unmask = s3c_irq_uart0_unmask,
@ -417,7 +417,7 @@ s3c_irq_uart1_ack(unsigned int irqno)
s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
}
static struct irqchip s3c_irq_uart1 = {
static struct irq_chip s3c_irq_uart1 = {
.name = "s3c-uart1",
.mask = s3c_irq_uart1_mask,
.unmask = s3c_irq_uart1_unmask,
@ -444,7 +444,7 @@ s3c_irq_uart2_ack(unsigned int irqno)
s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
}
static struct irqchip s3c_irq_uart2 = {
static struct irq_chip s3c_irq_uart2 = {
.name = "s3c-uart2",
.mask = s3c_irq_uart2_mask,
.unmask = s3c_irq_uart2_unmask,
@ -471,7 +471,7 @@ s3c_irq_adc_ack(unsigned int irqno)
s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
}
static struct irqchip s3c_irq_adc = {
static struct irq_chip s3c_irq_adc = {
.name = "s3c-adc",
.mask = s3c_irq_adc_mask,
.unmask = s3c_irq_adc_unmask,
@ -480,11 +480,11 @@ static struct irqchip s3c_irq_adc = {
/* irq demux for adc */
static void s3c_irq_demux_adc(unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
unsigned int subsrc, submsk;
unsigned int offset = 9;
struct irqdesc *mydesc;
struct irq_desc *mydesc;
/* read the current pending interrupts, and the mask
* for what it is available */
@ -512,7 +512,7 @@ static void s3c_irq_demux_uart(unsigned int start)
{
unsigned int subsrc, submsk;
unsigned int offset = start - IRQ_S3CUART_RX0;
struct irqdesc *desc;
struct irq_desc *desc;
/* read the current pending interrupts, and the mask
* for what it is available */
@ -549,7 +549,7 @@ static void s3c_irq_demux_uart(unsigned int start)
static void
s3c_irq_demux_uart0(unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
irq = irq;
s3c_irq_demux_uart(IRQ_S3CUART_RX0);
@ -557,7 +557,7 @@ s3c_irq_demux_uart0(unsigned int irq,
static void
s3c_irq_demux_uart1(unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
irq = irq;
s3c_irq_demux_uart(IRQ_S3CUART_RX1);
@ -565,7 +565,7 @@ s3c_irq_demux_uart1(unsigned int irq,
static void
s3c_irq_demux_uart2(unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
irq = irq;
s3c_irq_demux_uart(IRQ_S3CUART_RX2);
@ -573,7 +573,7 @@ s3c_irq_demux_uart2(unsigned int irq,
static void
s3c_irq_demux_extint8(unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@ -595,7 +595,7 @@ s3c_irq_demux_extint8(unsigned int irq,
static void
s3c_irq_demux_extint4t7(unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@ -738,7 +738,7 @@ void __init s3c24xx_init_irq(void)
case IRQ_UART2:
case IRQ_ADCPARENT:
set_irq_chip(irqno, &s3c_irq_level_chip);
set_irq_handler(irqno, do_level_IRQ);
set_irq_handler(irqno, handle_level_irq);
break;
case IRQ_RESERVED6:
@ -749,7 +749,7 @@ void __init s3c24xx_init_irq(void)
default:
//irqdbf("registering irq %d (s3c irq)\n", irqno);
set_irq_chip(irqno, &s3c_irq_chip);
set_irq_handler(irqno, do_edge_IRQ);
set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
@ -769,14 +769,14 @@ void __init s3c24xx_init_irq(void)
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
irqdbf("registering irq %d (ext int)\n", irqno);
set_irq_chip(irqno, &s3c_irq_eint0t4);
set_irq_handler(irqno, do_edge_IRQ);
set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
irqdbf("registering irq %d (extended s3c irq)\n", irqno);
set_irq_chip(irqno, &s3c_irqext_chip);
set_irq_handler(irqno, do_edge_IRQ);
set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
@ -787,28 +787,28 @@ void __init s3c24xx_init_irq(void)
for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
set_irq_chip(irqno, &s3c_irq_uart0);
set_irq_handler(irqno, do_level_IRQ);
set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
set_irq_chip(irqno, &s3c_irq_uart1);
set_irq_handler(irqno, do_level_IRQ);
set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
set_irq_chip(irqno, &s3c_irq_uart2);
set_irq_handler(irqno, do_level_IRQ);
set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
irqdbf("registering irq %d (s3c adc irq)\n", irqno);
set_irq_chip(irqno, &s3c_irq_adc);
set_irq_handler(irqno, do_edge_IRQ);
set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}

2
arch/arm/mach-s3c2410/irq.h
View File

@ -17,7 +17,7 @@
#define EXTINT_OFF (IRQ_EINT4 - 4)
extern struct irqchip s3c_irq_level_chip;
extern struct irq_chip s3c_irq_level_chip;
static inline void
s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,

4
arch/arm/mach-s3c2410/s3c2412-irq.c
View File

@ -98,7 +98,7 @@ s3c2412_irq_unmask(unsigned int irqno)
__raw_writel(mask & ~bitval, S3C2410_INTMSK);
}
static struct irqchip s3c2412_irq_eint0t4 = {
static struct irq_chip s3c2412_irq_eint0t4 = {
.ack = s3c2412_irq_ack,
.mask = s3c2412_irq_mask,
.unmask = s3c2412_irq_unmask,
@ -112,7 +112,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
set_irq_chip(irqno, &s3c2412_irq_eint0t4);
set_irq_handler(irqno, do_edge_IRQ);
set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}

10
arch/arm/mach-s3c2410/s3c2440-irq.c
View File

@ -42,10 +42,10 @@
/* WDT/AC97 */
static void s3c_irq_demux_wdtac97(unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
unsigned int subsrc, submsk;
struct irqdesc *mydesc;
struct irq_desc *mydesc;
/* read the current pending interrupts, and the mask
* for what it is available */
@ -90,7 +90,7 @@ s3c_irq_wdtac97_ack(unsigned int irqno)
s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
}
static struct irqchip s3c_irq_wdtac97 = {
static struct irq_chip s3c_irq_wdtac97 = {
.mask = s3c_irq_wdtac97_mask,
.unmask = s3c_irq_wdtac97_unmask,
.ack = s3c_irq_wdtac97_ack,
@ -105,12 +105,12 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
/* add new chained handler for wdt, ac7 */
set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
set_irq_handler(IRQ_WDT, do_level_IRQ);
set_irq_handler(IRQ_WDT, handle_level_irq);
set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
set_irq_chip(irqno, &s3c_irq_wdtac97);
set_irq_handler(irqno, do_level_IRQ);
set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}

12
arch/arm/mach-s3c2410/s3c244x-irq.c
View File

@ -42,10 +42,10 @@
/* camera irq */
static void s3c_irq_demux_cam(unsigned int irq,
struct irqdesc *desc)
struct irq_desc *desc)
{
unsigned int subsrc, submsk;
struct irqdesc *mydesc;
struct irq_desc *mydesc;
/* read the current pending interrupts, and the mask
* for what it is available */
@ -89,7 +89,7 @@ s3c_irq_cam_ack(unsigned int irqno)
s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
}
static struct irqchip s3c_irq_cam = {
static struct irq_chip s3c_irq_cam = {
.mask = s3c_irq_cam_mask,
.unmask = s3c_irq_cam_unmask,
.ack = s3c_irq_cam_ack,
@ -100,18 +100,18 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
unsigned int irqno;
set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
set_irq_handler(IRQ_NFCON, do_level_IRQ);
set_irq_handler(IRQ_NFCON, handle_level_irq);
set_irq_flags(IRQ_NFCON, IRQF_VALID);
/* add chained handler for camera */
set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
set_irq_handler(IRQ_CAM, do_level_IRQ);
set_irq_handler(IRQ_CAM, handle_level_irq);
set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
set_irq_chip(irqno, &s3c_irq_cam);
set_irq_handler(irqno, do_level_IRQ);
set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}

6
arch/arm/mach-sa1100/h3600.c
View File

@ -702,7 +702,7 @@ static u32 gpio_irq_mask[] = {
GPIO2_SD_CON_SLT,
};
static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc)
static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc)
{
int i;
@ -719,14 +719,14 @@ static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc)
if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq);
for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++)
if (irq & kpio_irq_mask[j])
do_edge_IRQ(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
/* GPIO2 */
irq = H3800_ASIC2_GPIINTFLAG;
if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq);
for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++)
if (irq & gpio_irq_mask[j])
do_edge_IRQ(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
}
if (i >= MAX_ASIC_ISR_LOOPS)

8
arch/arm/mach-sa1100/irq.c
View File

@ -110,7 +110,7 @@ static struct irq_chip sa1100_low_gpio_chip = {
* and call the handler.
*/
static void
sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc)
sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int mask;
@ -327,19 +327,19 @@ void __init sa1100_init_irq(void)
for (irq = 0; irq <= 10; irq++) {
set_irq_chip(irq, &sa1100_low_gpio_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = 12; irq <= 31; irq++) {
set_irq_chip(irq, &sa1100_normal_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
for (irq = 32; irq <= 48; irq++) {
set_irq_chip(irq, &sa1100_high_gpio_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}

8
arch/arm/mach-sa1100/neponset.c
View File

@ -29,12 +29,12 @@
* is rather unfortunate.
*/
static void
neponset_irq_handler(unsigned int irq, struct irqdesc *desc)
neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int irr;
while (1) {
struct irqdesc *d;
struct irq_desc *d;
/*
* Acknowledge the parent IRQ.
@ -168,9 +168,9 @@ static int neponset_probe(struct platform_device *dev)
* Setup other Neponset IRQs. SA1111 will be done by the
* generic SA1111 code.
*/
set_irq_handler(IRQ_NEPONSET_SMC9196, do_simple_IRQ);
set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
set_irq_handler(IRQ_NEPONSET_USAR, do_simple_IRQ);
set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
/*

2
arch/arm/mach-shark/irq.c
View File

@ -82,7 +82,7 @@ void __init shark_init_irq(void)
for (irq = 0; irq < NR_IRQS; irq++) {
set_irq_chip(irq, &fb_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}

4
arch/arm/mach-versatile/core.c
View File

@ -77,7 +77,7 @@ static struct irq_chip sic_chip = {
};
static void
sic_handle_irq(unsigned int irq, struct irqdesc *desc)
sic_handle_irq(unsigned int irq, struct irq_desc *desc)
{
unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
@ -123,7 +123,7 @@ void __init versatile_init_irq(void)
for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
set_irq_chip(i, &sic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}

8
arch/arm/plat-omap/gpio.c
View File

@ -410,7 +410,7 @@ static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int tr
trigger & __IRQT_RISEDGE);
MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
trigger & __IRQT_FALEDGE);
/* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
/* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
* triggering requested. */
}
@ -783,7 +783,7 @@ void omap_free_gpio(int gpio)
* line's interrupt handler has been run, we may miss some nested
* interrupts.
*/
static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
void __iomem *isr_reg = NULL;
u32 isr;
@ -853,7 +853,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
gpio_irq = bank->virtual_irq_start;
for (; isr != 0; isr >>= 1, gpio_irq++) {
struct irqdesc *d;
struct irq_desc *d;
int irq_mask;
if (!(isr & 1))
continue;
@ -1092,7 +1092,7 @@ static int __init _omap_gpio_init(void)
set_irq_chip(j, &mpuio_irq_chip);
else
set_irq_chip(j, &gpio_irq_chip);
set_irq_handler(j, do_simple_IRQ);
set_irq_handler(j, handle_simple_irq);
set_irq_flags(j, IRQF_VALID);
}
set_irq_chained_handler(bank->irq, gpio_irq_handler);

12
include/asm-arm/mach/irq.h
View File

@ -21,12 +21,6 @@ extern void (*init_arch_irq)(void);
extern void init_FIQ(void);
extern int show_fiq_list(struct seq_file *, void *);
/*
* Function wrappers
*/
#define set_irq_chipdata(irq, d) set_irq_chip_data(irq, d)
#define get_irq_chipdata(irq) get_irq_chip_data(irq)
/*
* Obsolete inline function for calling irq descriptor handlers.
*/
@ -44,12 +38,6 @@ void set_irq_flags(unsigned int irq, unsigned int flags);
/*
* This is for easy migration, but should be changed in the source
*/
#define do_level_IRQ handle_level_irq
#define do_edge_IRQ handle_edge_irq
#define do_simple_IRQ handle_simple_irq
#define irqdesc irq_desc
#define irqchip irq_chip
#define do_bad_IRQ(irq,desc) \
do { \
spin_lock(&desc->lock); \