Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm: KVM: Use new smp_call_function_mask() in kvm_flush_remote_tlbs() sched: don't clear PF_VCPU in scheduler KVM: Improve local apic timer wraparound handling KVM: Fix local apic timer divide by zero KVM: Move kvm_guest_exit() after local_irq_enable() KVM: x86 emulator: fix access registers for instructions with ModR/M byte and Mod = 3 KVM: VMX: Force vm86 mode if setting flags during real mode KVM: x86 emulator: implement 'movnti mem, reg' KVM: VMX: Reset mmu context when entering real mode KVM: VMX: Handle NMIs before enabling interrupts and preemption KVM: MMU: Set shadow pte atomically in mmu_pte_write_zap_pte() KVM: x86 emulator: fix repne/repnz decoding KVM: x86 emulator: fix merge screwup due to emulator split
This commit is contained in:
Linus Torvalds
commit
0fd56c7033
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@ -198,21 +198,15 @@ static void vcpu_put(struct kvm_vcpu *vcpu)
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static void ack_flush(void *_completed)
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{
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atomic_t *completed = _completed;
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atomic_inc(completed);
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}
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void kvm_flush_remote_tlbs(struct kvm *kvm)
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{
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int i, cpu, needed;
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int i, cpu;
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cpumask_t cpus;
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struct kvm_vcpu *vcpu;
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atomic_t completed;
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atomic_set(&completed, 0);
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cpus_clear(cpus);
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needed = 0;
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for (i = 0; i < KVM_MAX_VCPUS; ++i) {
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vcpu = kvm->vcpus[i];
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if (!vcpu)
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@ -221,23 +215,9 @@ void kvm_flush_remote_tlbs(struct kvm *kvm)
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continue;
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cpu = vcpu->cpu;
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if (cpu != -1 && cpu != raw_smp_processor_id())
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if (!cpu_isset(cpu, cpus)) {
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cpu_set(cpu, cpus);
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++needed;
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}
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}
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/*
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* We really want smp_call_function_mask() here. But that's not
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* available, so ipi all cpus in parallel and wait for them
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* to complete.
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*/
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for (cpu = first_cpu(cpus); cpu != NR_CPUS; cpu = next_cpu(cpu, cpus))
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smp_call_function_single(cpu, ack_flush, &completed, 1, 0);
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while (atomic_read(&completed) != needed) {
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cpu_relax();
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barrier();
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cpu_set(cpu, cpus);
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}
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smp_call_function_mask(cpus, ack_flush, NULL, 1);
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}
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int kvm_vcpu_init(struct kvm_vcpu *vcpu, struct kvm *kvm, unsigned id)
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@ -2054,12 +2034,21 @@ again:
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kvm_x86_ops->run(vcpu, kvm_run);
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kvm_guest_exit();
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vcpu->guest_mode = 0;
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local_irq_enable();
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++vcpu->stat.exits;
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/*
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* We must have an instruction between local_irq_enable() and
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* kvm_guest_exit(), so the timer interrupt isn't delayed by
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* the interrupt shadow. The stat.exits increment will do nicely.
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* But we need to prevent reordering, hence this barrier():
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*/
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barrier();
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kvm_guest_exit();
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preempt_enable();
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/*
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@ -494,12 +494,19 @@ static void apic_send_ipi(struct kvm_lapic *apic)
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static u32 apic_get_tmcct(struct kvm_lapic *apic)
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{
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u32 counter_passed;
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ktime_t passed, now = apic->timer.dev.base->get_time();
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u32 tmcct = apic_get_reg(apic, APIC_TMICT);
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u64 counter_passed;
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ktime_t passed, now;
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u32 tmcct;
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ASSERT(apic != NULL);
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now = apic->timer.dev.base->get_time();
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tmcct = apic_get_reg(apic, APIC_TMICT);
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/* if initial count is 0, current count should also be 0 */
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if (tmcct == 0)
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return 0;
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if (unlikely(ktime_to_ns(now) <=
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ktime_to_ns(apic->timer.last_update))) {
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/* Wrap around */
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@ -514,15 +521,24 @@ static u32 apic_get_tmcct(struct kvm_lapic *apic)
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counter_passed = div64_64(ktime_to_ns(passed),
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(APIC_BUS_CYCLE_NS * apic->timer.divide_count));
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tmcct -= counter_passed;
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if (tmcct <= 0) {
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if (unlikely(!apic_lvtt_period(apic)))
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if (counter_passed > tmcct) {
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if (unlikely(!apic_lvtt_period(apic))) {
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/* one-shot timers stick at 0 until reset */
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tmcct = 0;
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else
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do {
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tmcct += apic_get_reg(apic, APIC_TMICT);
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} while (tmcct <= 0);
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} else {
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/*
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* periodic timers reset to APIC_TMICT when they
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* hit 0. The while loop simulates this happening N
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* times. (counter_passed %= tmcct) would also work,
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* but might be slower or not work on 32-bit??
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*/
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while (counter_passed > tmcct)
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counter_passed -= tmcct;
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tmcct -= counter_passed;
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}
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} else {
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tmcct -= counter_passed;
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}
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return tmcct;
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@ -853,7 +869,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
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apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
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apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
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}
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apic->timer.divide_count = 0;
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update_divide_count(apic);
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atomic_set(&apic->timer.pending, 0);
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if (vcpu->vcpu_id == 0)
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vcpu->apic_base |= MSR_IA32_APICBASE_BSP;
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@ -1049,6 +1049,7 @@ int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
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destroy_kvm_mmu(vcpu);
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return init_kvm_mmu(vcpu);
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
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int kvm_mmu_load(struct kvm_vcpu *vcpu)
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{
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@ -1088,7 +1089,7 @@ static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
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mmu_page_remove_parent_pte(child, spte);
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}
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}
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*spte = 0;
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set_shadow_pte(spte, 0);
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kvm_flush_remote_tlbs(vcpu->kvm);
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}
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@ -523,6 +523,8 @@ static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
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static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
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{
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if (vcpu->rmode.active)
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rflags |= IOPL_MASK | X86_EFLAGS_VM;
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vmcs_writel(GUEST_RFLAGS, rflags);
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}
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@ -1128,6 +1130,7 @@ static void enter_rmode(struct kvm_vcpu *vcpu)
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fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
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fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
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kvm_mmu_reset_context(vcpu);
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init_rmode_tss(vcpu->kvm);
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}
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@ -1760,10 +1763,8 @@ static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
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set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
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}
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if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
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asm ("int $2");
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return 1;
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}
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if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
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return 1; /* already handled by vmx_vcpu_run() */
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if (is_no_device(intr_info)) {
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vmx_fpu_activate(vcpu);
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@ -2196,6 +2197,7 @@ static void vmx_intr_assist(struct kvm_vcpu *vcpu)
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static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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u32 intr_info;
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/*
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* Loading guest fpu may have cleared host cr0.ts
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@ -2322,6 +2324,12 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
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asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
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vmx->launched = 1;
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intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
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/* We need to handle NMIs before interrupts are enabled */
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if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
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asm("int $2");
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}
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static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
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@ -212,7 +212,8 @@ static u16 twobyte_table[256] = {
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0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
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DstReg | SrcMem16 | ModRM | Mov,
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/* 0xC0 - 0xCF */
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0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
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0, 0, 0, 0, 0, 0, 0, 0,
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/* 0xD0 - 0xDF */
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/* 0xE0 - 0xEF */
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@ -596,11 +597,10 @@ x86_emulate_memop(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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case 0xf0: /* LOCK */
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lock_prefix = 1;
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break;
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case 0xf2: /* REPNE/REPNZ */
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case 0xf3: /* REP/REPE/REPZ */
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rep_prefix = 1;
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break;
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case 0xf2: /* REPNE/REPNZ */
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break;
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default:
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goto done_prefixes;
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}
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@ -825,6 +825,14 @@ done_prefixes:
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if (twobyte && b == 0x01 && modrm_reg == 7)
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break;
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srcmem_common:
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/*
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* For instructions with a ModR/M byte, switch to register
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* access if Mod = 3.
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*/
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if ((d & ModRM) && modrm_mod == 3) {
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src.type = OP_REG;
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break;
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}
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src.type = OP_MEM;
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src.ptr = (unsigned long *)cr2;
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src.val = 0;
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@ -893,6 +901,14 @@ done_prefixes:
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dst.ptr = (unsigned long *)cr2;
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dst.bytes = (d & ByteOp) ? 1 : op_bytes;
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dst.val = 0;
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/*
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* For instructions with a ModR/M byte, switch to register
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* access if Mod = 3.
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*/
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if ((d & ModRM) && modrm_mod == 3) {
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dst.type = OP_REG;
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break;
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}
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if (d & BitOp) {
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unsigned long mask = ~(dst.bytes * 8 - 1);
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@ -1083,31 +1099,6 @@ push:
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case 0xd2 ... 0xd3: /* Grp2 */
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src.val = _regs[VCPU_REGS_RCX];
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goto grp2;
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case 0xe8: /* call (near) */ {
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long int rel;
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switch (op_bytes) {
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case 2:
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rel = insn_fetch(s16, 2, _eip);
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break;
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case 4:
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rel = insn_fetch(s32, 4, _eip);
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break;
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case 8:
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rel = insn_fetch(s64, 8, _eip);
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break;
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default:
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DPRINTF("Call: Invalid op_bytes\n");
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goto cannot_emulate;
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}
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src.val = (unsigned long) _eip;
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JMP_REL(rel);
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goto push;
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}
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case 0xe9: /* jmp rel */
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case 0xeb: /* jmp rel short */
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JMP_REL(src.val);
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no_wb = 1; /* Disable writeback. */
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break;
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case 0xf6 ... 0xf7: /* Grp3 */
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switch (modrm_reg) {
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case 0 ... 1: /* test */
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@ -1350,6 +1341,32 @@ special_insn:
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case 0xae ... 0xaf: /* scas */
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DPRINTF("Urk! I don't handle SCAS.\n");
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goto cannot_emulate;
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case 0xe8: /* call (near) */ {
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long int rel;
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switch (op_bytes) {
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case 2:
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rel = insn_fetch(s16, 2, _eip);
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break;
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case 4:
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rel = insn_fetch(s32, 4, _eip);
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break;
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case 8:
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rel = insn_fetch(s64, 8, _eip);
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break;
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default:
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DPRINTF("Call: Invalid op_bytes\n");
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goto cannot_emulate;
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}
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src.val = (unsigned long) _eip;
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JMP_REL(rel);
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goto push;
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}
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case 0xe9: /* jmp rel */
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case 0xeb: /* jmp rel short */
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JMP_REL(src.val);
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no_wb = 1; /* Disable writeback. */
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break;
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}
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goto writeback;
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@ -1501,6 +1518,10 @@ twobyte_insn:
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dst.bytes = op_bytes;
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dst.val = (d & ByteOp) ? (s8) src.val : (s16) src.val;
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break;
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case 0xc3: /* movnti */
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dst.bytes = op_bytes;
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dst.val = (op_bytes == 4) ? (u32) src.val : (u64) src.val;
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break;
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}
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goto writeback;
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@ -3375,7 +3375,6 @@ void account_system_time(struct task_struct *p, int hardirq_offset,
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if (p->flags & PF_VCPU) {
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account_guest_time(p, cputime);
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p->flags &= ~PF_VCPU;
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return;
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}
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