Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-2.6 into merge
Conflicts: Documentation/feature-removal-schedule.txt drivers/net/wireless/ath/ath5k/phy.c drivers/net/wireless/iwlwifi/iwl-4965.c drivers/net/wireless/iwlwifi/iwl-agn.c drivers/net/wireless/iwlwifi/iwl-core.c drivers/net/wireless/iwlwifi/iwl-core.h drivers/net/wireless/iwlwifi/iwl-tx.c
This commit is contained in:
John W. Linville
commit
0f2df9eac7
|
|
@ -128,3 +128,17 @@ Description:
|
|||
preferred request size for workloads where sustained
|
||||
throughput is desired. If no optimal I/O size is
|
||||
reported this file contains 0.
|
||||
|
||||
What: /sys/block/<disk>/queue/nomerges
|
||||
Date: January 2010
|
||||
Contact:
|
||||
Description:
|
||||
Standard I/O elevator operations include attempts to
|
||||
merge contiguous I/Os. For known random I/O loads these
|
||||
attempts will always fail and result in extra cycles
|
||||
being spent in the kernel. This allows one to turn off
|
||||
this behavior on one of two ways: When set to 1, complex
|
||||
merge checks are disabled, but the simple one-shot merges
|
||||
with the previous I/O request are enabled. When set to 2,
|
||||
all merge tries are disabled. The default value is 0 -
|
||||
which enables all types of merge tries.
|
||||
|
|
|
|||
|
|
@ -59,7 +59,11 @@ PAGE_OFFSET high_memory-1 Kernel direct-mapped RAM region.
|
|||
This maps the platforms RAM, and typically
|
||||
maps all platform RAM in a 1:1 relationship.
|
||||
|
||||
TASK_SIZE PAGE_OFFSET-1 Kernel module space
|
||||
PKMAP_BASE PAGE_OFFSET-1 Permanent kernel mappings
|
||||
One way of mapping HIGHMEM pages into kernel
|
||||
space.
|
||||
|
||||
MODULES_VADDR MODULES_END-1 Kernel module space
|
||||
Kernel modules inserted via insmod are
|
||||
placed here using dynamic mappings.
|
||||
|
||||
|
|
|
|||
|
|
@ -25,11 +25,11 @@ size allowed by the hardware.
|
|||
|
||||
nomerges (RW)
|
||||
-------------
|
||||
This enables the user to disable the lookup logic involved with IO merging
|
||||
requests in the block layer. Merging may still occur through a direct
|
||||
1-hit cache, since that comes for (almost) free. The IO scheduler will not
|
||||
waste cycles doing tree/hash lookups for merges if nomerges is 1. Defaults
|
||||
to 0, enabling all merges.
|
||||
This enables the user to disable the lookup logic involved with IO
|
||||
merging requests in the block layer. By default (0) all merges are
|
||||
enabled. When set to 1 only simple one-hit merges will be tried. When
|
||||
set to 2 no merge algorithms will be tried (including one-hit or more
|
||||
complex tree/hash lookups).
|
||||
|
||||
nr_requests (RW)
|
||||
----------------
|
||||
|
|
|
|||
|
|
@ -88,12 +88,12 @@ changes occur:
|
|||
This is used primarily during fault processing.
|
||||
|
||||
5) void update_mmu_cache(struct vm_area_struct *vma,
|
||||
unsigned long address, pte_t pte)
|
||||
unsigned long address, pte_t *ptep)
|
||||
|
||||
At the end of every page fault, this routine is invoked to
|
||||
tell the architecture specific code that a translation
|
||||
described by "pte" now exists at virtual address "address"
|
||||
for address space "vma->vm_mm", in the software page tables.
|
||||
now exists at virtual address "address" for address space
|
||||
"vma->vm_mm", in the software page tables.
|
||||
|
||||
A port may use this information in any way it so chooses.
|
||||
For example, it could use this event to pre-load TLB
|
||||
|
|
|
|||
|
|
@ -520,6 +520,29 @@ Who: Hans de Goede <hdegoede@redhat.com>
|
|||
|
||||
----------------------------
|
||||
|
||||
What: corgikbd, spitzkbd, tosakbd driver
|
||||
When: 2.6.35
|
||||
Files: drivers/input/keyboard/{corgi,spitz,tosa}kbd.c
|
||||
Why: We now have a generic GPIO based matrix keyboard driver that
|
||||
are fully capable of handling all the keys on these devices.
|
||||
The original drivers manipulate the GPIO registers directly
|
||||
and so are difficult to maintain.
|
||||
Who: Eric Miao <eric.y.miao@gmail.com>
|
||||
|
||||
----------------------------
|
||||
|
||||
What: corgi_ssp and corgi_ts driver
|
||||
When: 2.6.35
|
||||
Files: arch/arm/mach-pxa/corgi_ssp.c, drivers/input/touchscreen/corgi_ts.c
|
||||
Why: The corgi touchscreen is now deprecated in favour of the generic
|
||||
ads7846.c driver. The noise reduction technique used in corgi_ts.c,
|
||||
that's to wait till vsync before ADC sampling, is also integrated into
|
||||
ads7846 driver now. Provided that the original driver is not generic
|
||||
and is difficult to maintain, it will be removed later.
|
||||
Who: Eric Miao <eric.y.miao@gmail.com>
|
||||
|
||||
----------------------------
|
||||
|
||||
What: sysfs-class-rfkill state file
|
||||
When: Feb 2014
|
||||
Files: net/rfkill/core.c
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Copyright (C) 2002-2008 Sentelic Corporation.
|
||||
Last update: Oct-31-2008
|
||||
Copyright (C) 2002-2010 Sentelic Corporation.
|
||||
Last update: Jan-13-2010
|
||||
|
||||
==============================================================================
|
||||
* Finger Sensing Pad Intellimouse Mode(scrolling wheel, 4th and 5th buttons)
|
||||
|
|
@ -44,7 +44,7 @@ B) MSID 6: Horizontal and Vertical scrolling.
|
|||
Packet 1
|
||||
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
|
||||
BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
|
||||
1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|l|r|u|d|
|
||||
1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|r|l|u|d|
|
||||
|---------------| |---------------| |---------------| |---------------|
|
||||
|
||||
Byte 1: Bit7 => Y overflow
|
||||
|
|
@ -59,15 +59,15 @@ Byte 2: X Movement(9-bit 2's complement integers)
|
|||
Byte 3: Y Movement(9-bit 2's complement integers)
|
||||
Byte 4: Bit0 => the Vertical scrolling movement downward.
|
||||
Bit1 => the Vertical scrolling movement upward.
|
||||
Bit2 => the Vertical scrolling movement rightward.
|
||||
Bit3 => the Vertical scrolling movement leftward.
|
||||
Bit2 => the Horizontal scrolling movement leftward.
|
||||
Bit3 => the Horizontal scrolling movement rightward.
|
||||
Bit4 => 1 = 4th mouse button is pressed, Forward one page.
|
||||
0 = 4th mouse button is not pressed.
|
||||
Bit5 => 1 = 5th mouse button is pressed, Backward one page.
|
||||
0 = 5th mouse button is not pressed.
|
||||
|
||||
C) MSID 7:
|
||||
# FSP uses 2 packets(8 Bytes) data to represent Absolute Position
|
||||
# FSP uses 2 packets (8 Bytes) to represent Absolute Position.
|
||||
so we have PACKET NUMBER to identify packets.
|
||||
If PACKET NUMBER is 0, the packet is Packet 1.
|
||||
If PACKET NUMBER is 1, the packet is Packet 2.
|
||||
|
|
@ -129,7 +129,7 @@ Byte 3: Message Type => 0x00 (Disabled)
|
|||
Byte 4: Bit7~Bit0 => Don't Care
|
||||
|
||||
==============================================================================
|
||||
* Absolute position for STL3888-A0.
|
||||
* Absolute position for STL3888-Ax.
|
||||
==============================================================================
|
||||
Packet 1 (ABSOLUTE POSITION)
|
||||
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
|
||||
|
|
@ -179,14 +179,14 @@ Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
|
|||
Bit5~Bit4 => y2_g
|
||||
Bit7~Bit6 => x2_g
|
||||
|
||||
Notify Packet for STL3888-A0
|
||||
Notify Packet for STL3888-Ax
|
||||
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
|
||||
BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
|
||||
1 |1|0|1|P|1|M|R|L| 2 |C|C|C|C|C|C|C|C| 3 |0|0|F|F|0|0|0|i| 4 |r|l|d|u|0|0|0|0|
|
||||
|---------------| |---------------| |---------------| |---------------|
|
||||
|
||||
Byte 1: Bit7~Bit6 => 00, Normal data packet
|
||||
=> 01, Absolute coordination packet
|
||||
=> 01, Absolute coordinates packet
|
||||
=> 10, Notify packet
|
||||
Bit5 => 1
|
||||
Bit4 => when in absolute coordinates mode (valid when EN_PKT_GO is 1):
|
||||
|
|
@ -205,15 +205,106 @@ Byte 4: Bit7 => scroll right button
|
|||
Bit6 => scroll left button
|
||||
Bit5 => scroll down button
|
||||
Bit4 => scroll up button
|
||||
* Note that if gesture and additional button (Bit4~Bit7)
|
||||
happen at the same time, the button information will not
|
||||
be sent.
|
||||
* Note that if gesture and additional buttoni (Bit4~Bit7)
|
||||
happen at the same time, the button information will not
|
||||
be sent.
|
||||
Bit3~Bit0 => Reserved
|
||||
|
||||
Sample sequence of Multi-finger, Multi-coordinate mode:
|
||||
|
||||
notify packet (valid bit == 1), abs pkt 1, abs pkt 2, abs pkt 1,
|
||||
abs pkt 2, ..., notify packet(valid bit == 0)
|
||||
abs pkt 2, ..., notify packet (valid bit == 0)
|
||||
|
||||
==============================================================================
|
||||
* Absolute position for STL3888-B0.
|
||||
==============================================================================
|
||||
Packet 1(ABSOLUTE POSITION)
|
||||
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
|
||||
BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
|
||||
1 |0|1|V|F|1|0|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 |r|l|u|d|X|X|Y|Y|
|
||||
|---------------| |---------------| |---------------| |---------------|
|
||||
|
||||
Byte 1: Bit7~Bit6 => 00, Normal data packet
|
||||
=> 01, Absolute coordinates packet
|
||||
=> 10, Notify packet
|
||||
Bit5 => Valid bit, 0 means that the coordinate is invalid or finger up.
|
||||
When both fingers are up, the last two reports have zero valid
|
||||
bit.
|
||||
Bit4 => finger up/down information. 1: finger down, 0: finger up.
|
||||
Bit3 => 1
|
||||
Bit2 => finger index, 0 is the first finger, 1 is the second finger.
|
||||
Bit1 => Right Button, 1 is pressed, 0 is not pressed.
|
||||
Bit0 => Left Button, 1 is pressed, 0 is not pressed.
|
||||
Byte 2: X coordinate (xpos[9:2])
|
||||
Byte 3: Y coordinate (ypos[9:2])
|
||||
Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
|
||||
Bit3~Bit2 => X coordinate (ypos[1:0])
|
||||
Bit4 => scroll down button
|
||||
Bit5 => scroll up button
|
||||
Bit6 => scroll left button
|
||||
Bit7 => scroll right button
|
||||
|
||||
Packet 2 (ABSOLUTE POSITION)
|
||||
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
|
||||
BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
|
||||
1 |0|1|V|F|1|1|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 |r|l|u|d|X|X|Y|Y|
|
||||
|---------------| |---------------| |---------------| |---------------|
|
||||
|
||||
Byte 1: Bit7~Bit6 => 00, Normal data packet
|
||||
=> 01, Absolute coordination packet
|
||||
=> 10, Notify packet
|
||||
Bit5 => Valid bit, 0 means that the coordinate is invalid or finger up.
|
||||
When both fingers are up, the last two reports have zero valid
|
||||
bit.
|
||||
Bit4 => finger up/down information. 1: finger down, 0: finger up.
|
||||
Bit3 => 1
|
||||
Bit2 => finger index, 0 is the first finger, 1 is the second finger.
|
||||
Bit1 => Right Button, 1 is pressed, 0 is not pressed.
|
||||
Bit0 => Left Button, 1 is pressed, 0 is not pressed.
|
||||
Byte 2: X coordinate (xpos[9:2])
|
||||
Byte 3: Y coordinate (ypos[9:2])
|
||||
Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
|
||||
Bit3~Bit2 => X coordinate (ypos[1:0])
|
||||
Bit4 => scroll down button
|
||||
Bit5 => scroll up button
|
||||
Bit6 => scroll left button
|
||||
Bit7 => scroll right button
|
||||
|
||||
Notify Packet for STL3888-B0
|
||||
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
|
||||
BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
|
||||
1 |1|0|1|P|1|M|R|L| 2 |C|C|C|C|C|C|C|C| 3 |0|0|F|F|0|0|0|i| 4 |r|l|u|d|0|0|0|0|
|
||||
|---------------| |---------------| |---------------| |---------------|
|
||||
|
||||
Byte 1: Bit7~Bit6 => 00, Normal data packet
|
||||
=> 01, Absolute coordination packet
|
||||
=> 10, Notify packet
|
||||
Bit5 => 1
|
||||
Bit4 => when in absolute coordinate mode (valid when EN_PKT_GO is 1):
|
||||
0: left button is generated by the on-pad command
|
||||
1: left button is generated by the external button
|
||||
Bit3 => 1
|
||||
Bit2 => Middle Button, 1 is pressed, 0 is not pressed.
|
||||
Bit1 => Right Button, 1 is pressed, 0 is not pressed.
|
||||
Bit0 => Left Button, 1 is pressed, 0 is not pressed.
|
||||
Byte 2: Message Type => 0xB7 (Multi Finger, Multi Coordinate mode)
|
||||
Byte 3: Bit7~Bit6 => Don't care
|
||||
Bit5~Bit4 => Number of fingers
|
||||
Bit3~Bit1 => Reserved
|
||||
Bit0 => 1: enter gesture mode; 0: leaving gesture mode
|
||||
Byte 4: Bit7 => scroll right button
|
||||
Bit6 => scroll left button
|
||||
Bit5 => scroll up button
|
||||
Bit4 => scroll down button
|
||||
* Note that if gesture and additional button(Bit4~Bit7)
|
||||
happen at the same time, the button information will not
|
||||
be sent.
|
||||
Bit3~Bit0 => Reserved
|
||||
|
||||
Sample sequence of Multi-finger, Multi-coordinate mode:
|
||||
|
||||
notify packet (valid bit == 1), abs pkt 1, abs pkt 2, abs pkt 1,
|
||||
abs pkt 2, ..., notify packet (valid bit == 0)
|
||||
|
||||
==============================================================================
|
||||
* FSP Enable/Disable packet
|
||||
|
|
@ -409,7 +500,8 @@ offset width default r/w name
|
|||
0: read only, 1: read/write enable
|
||||
(Note that following registers does not require clock gating being
|
||||
enabled prior to write: 05 06 07 08 09 0c 0f 10 11 12 16 17 18 23 2e
|
||||
40 41 42 43.)
|
||||
40 41 42 43. In addition to that, this bit must be 1 when gesture
|
||||
mode is enabled)
|
||||
|
||||
0x31 RW on-pad command detection
|
||||
bit7 0 RW on-pad command left button down tag
|
||||
|
|
@ -463,6 +555,10 @@ offset width default r/w name
|
|||
absolute coordinates; otherwise, host only receives packets with
|
||||
relative coordinate.)
|
||||
|
||||
bit7 0 RW EN_PS2_F2: PS/2 gesture mode 2nd
|
||||
finger packet enable
|
||||
0: disable, 1: enable
|
||||
|
||||
0x43 RW on-pad control
|
||||
bit0 0 RW on-pad control enable
|
||||
0: disable, 1: enable
|
||||
|
|
|
|||
|
|
@ -482,6 +482,9 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
|
|||
|
||||
reference_rate - reference sample rate, 44100 or 48000 (default)
|
||||
multiple - multiple to ref. sample rate, 1 or 2 (default)
|
||||
subsystem - override the PCI SSID for probing; the value
|
||||
consists of SSVID << 16 | SSDID. The default is
|
||||
zero, which means no override.
|
||||
|
||||
This module supports multiple cards.
|
||||
|
||||
|
|
@ -1123,6 +1126,21 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
|
|||
|
||||
This module supports multiple cards, autoprobe and ISA PnP.
|
||||
|
||||
Module snd-jazz16
|
||||
-------------------
|
||||
|
||||
Module for Media Vision Jazz16 chipset. The chipset consists of 3 chips:
|
||||
MVD1216 + MVA416 + MVA514.
|
||||
|
||||
port - port # for SB DSP chip (0x210,0x220,0x230,0x240,0x250,0x260)
|
||||
irq - IRQ # for SB DSP chip (3,5,7,9,10,15)
|
||||
dma8 - DMA # for SB DSP chip (1,3)
|
||||
dma16 - DMA # for SB DSP chip (5,7)
|
||||
mpu_port - MPU-401 port # (0x300,0x310,0x320,0x330)
|
||||
mpu_irq - MPU-401 irq # (2,3,5,7)
|
||||
|
||||
This module supports multiple cards.
|
||||
|
||||
Module snd-korg1212
|
||||
-------------------
|
||||
|
||||
|
|
@ -1791,6 +1809,13 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
|
|||
|
||||
The power-management is supported.
|
||||
|
||||
Module snd-ua101
|
||||
----------------
|
||||
|
||||
Module for the Edirol UA-101 audio/MIDI interface.
|
||||
|
||||
This module supports multiple devices, autoprobe and hotplugging.
|
||||
|
||||
Module snd-usb-audio
|
||||
--------------------
|
||||
|
||||
|
|
@ -1923,7 +1948,7 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
|
|||
-------------------
|
||||
|
||||
Module for sound cards based on the Asus AV100/AV200 chips,
|
||||
i.e., Xonar D1, DX, D2, D2X, HDAV1.3 (Deluxe), Essence ST
|
||||
i.e., Xonar D1, DX, D2, D2X, DS, HDAV1.3 (Deluxe), Essence ST
|
||||
(Deluxe) and Essence STX.
|
||||
|
||||
This module supports autoprobe and multiple cards.
|
||||
|
|
|
|||
|
|
@ -124,6 +124,8 @@ ALC882/883/885/888/889
|
|||
asus-a7m ASUS A7M
|
||||
macpro MacPro support
|
||||
mb5 Macbook 5,1
|
||||
macmini3 Macmini 3,1
|
||||
mba21 Macbook Air 2,1
|
||||
mbp3 Macbook Pro rev3
|
||||
imac24 iMac 24'' with jack detection
|
||||
imac91 iMac 9,1
|
||||
|
|
@ -279,13 +281,16 @@ Conexant 5051
|
|||
laptop Basic Laptop config (default)
|
||||
hp HP Spartan laptop
|
||||
hp-dv6736 HP dv6736
|
||||
hp-f700 HP Compaq Presario F700
|
||||
lenovo-x200 Lenovo X200 laptop
|
||||
toshiba Toshiba Satellite M300
|
||||
|
||||
Conexant 5066
|
||||
=============
|
||||
laptop Basic Laptop config (default)
|
||||
dell-laptop Dell laptops
|
||||
olpc-xo-1_5 OLPC XO 1.5
|
||||
ideapad Lenovo IdeaPad U150
|
||||
|
||||
STAC9200
|
||||
========
|
||||
|
|
|
|||
|
|
@ -452,6 +452,33 @@ Similarly, the lines after `[verb]` are parsed as `init_verbs`
|
|||
sysfs entries, and the lines after `[hint]` are parsed as `hints`
|
||||
sysfs entries, respectively.
|
||||
|
||||
Another example to override the codec vendor id from 0x12345678 to
|
||||
0xdeadbeef is like below:
|
||||
------------------------------------------------------------------------
|
||||
[codec]
|
||||
0x12345678 0xabcd1234 2
|
||||
|
||||
[vendor_id]
|
||||
0xdeadbeef
|
||||
------------------------------------------------------------------------
|
||||
|
||||
In the similar way, you can override the codec subsystem_id via
|
||||
`[subsystem_id]`, the revision id via `[revision_id]` line.
|
||||
Also, the codec chip name can be rewritten via `[chip_name]` line.
|
||||
------------------------------------------------------------------------
|
||||
[codec]
|
||||
0x12345678 0xabcd1234 2
|
||||
|
||||
[subsystem_id]
|
||||
0xffff1111
|
||||
|
||||
[revision_id]
|
||||
0x10
|
||||
|
||||
[chip_name]
|
||||
My-own NEWS-0002
|
||||
------------------------------------------------------------------------
|
||||
|
||||
The hd-audio driver reads the file via request_firmware(). Thus,
|
||||
a patch file has to be located on the appropriate firmware path,
|
||||
typically, /lib/firmware. For example, when you pass the option
|
||||
|
|
|
|||
21
MAINTAINERS
21
MAINTAINERS
|
|
@ -1372,20 +1372,30 @@ F: arch/x86/include/asm/calgary.h
|
|||
F: arch/x86/include/asm/tce.h
|
||||
|
||||
CAN NETWORK LAYER
|
||||
M: Urs Thuermann <urs.thuermann@volkswagen.de>
|
||||
M: Oliver Hartkopp <socketcan@hartkopp.net>
|
||||
M: Oliver Hartkopp <oliver.hartkopp@volkswagen.de>
|
||||
L: socketcan-core@lists.berlios.de (subscribers-only)
|
||||
M: Urs Thuermann <urs.thuermann@volkswagen.de>
|
||||
L: socketcan-core@lists.berlios.de
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://developer.berlios.de/projects/socketcan/
|
||||
S: Maintained
|
||||
F: drivers/net/can/
|
||||
F: include/linux/can/
|
||||
F: net/can/
|
||||
F: include/linux/can.h
|
||||
F: include/linux/can/core.h
|
||||
F: include/linux/can/bcm.h
|
||||
F: include/linux/can/raw.h
|
||||
|
||||
CAN NETWORK DRIVERS
|
||||
M: Wolfgang Grandegger <wg@grandegger.com>
|
||||
L: socketcan-core@lists.berlios.de (subscribers-only)
|
||||
L: socketcan-core@lists.berlios.de
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://developer.berlios.de/projects/socketcan/
|
||||
S: Maintained
|
||||
F: drivers/net/can/
|
||||
F: include/linux/can/dev.h
|
||||
F: include/linux/can/error.h
|
||||
F: include/linux/can/netlink.h
|
||||
F: include/linux/can/platform/
|
||||
|
||||
CELL BROADBAND ENGINE ARCHITECTURE
|
||||
M: Arnd Bergmann <arnd@arndb.de>
|
||||
|
|
@ -2095,6 +2105,7 @@ F: drivers/net/eexpress.*
|
|||
ETHERNET BRIDGE
|
||||
M: Stephen Hemminger <shemminger@linux-foundation.org>
|
||||
L: bridge@lists.linux-foundation.org
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://www.linux-foundation.org/en/Net:Bridge
|
||||
S: Maintained
|
||||
F: include/linux/netfilter_bridge/
|
||||
|
|
|
|||
|
|
@ -329,7 +329,7 @@ extern pgd_t swapper_pg_dir[1024];
|
|||
* tables contain all the necessary information.
|
||||
*/
|
||||
extern inline void update_mmu_cache(struct vm_area_struct * vma,
|
||||
unsigned long address, pte_t pte)
|
||||
unsigned long address, pte_t *ptep)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ config ARM
|
|||
select HAVE_IDE
|
||||
select RTC_LIB
|
||||
select SYS_SUPPORTS_APM_EMULATION
|
||||
select GENERIC_ATOMIC64 if (!CPU_32v6K)
|
||||
select HAVE_OPROFILE
|
||||
select HAVE_ARCH_KGDB
|
||||
select HAVE_KPROBES if (!XIP_KERNEL)
|
||||
|
|
@ -20,6 +21,8 @@ config ARM
|
|||
select HAVE_GENERIC_DMA_COHERENT
|
||||
select HAVE_KERNEL_GZIP
|
||||
select HAVE_KERNEL_LZO
|
||||
select HAVE_PERF_EVENTS
|
||||
select PERF_USE_VMALLOC
|
||||
help
|
||||
The ARM series is a line of low-power-consumption RISC chip designs
|
||||
licensed by ARM Ltd and targeted at embedded applications and
|
||||
|
|
@ -52,6 +55,9 @@ config HAVE_TCM
|
|||
bool
|
||||
select GENERIC_ALLOCATOR
|
||||
|
||||
config HAVE_PROC_CPU
|
||||
bool
|
||||
|
||||
config NO_IOPORT
|
||||
bool
|
||||
|
||||
|
|
@ -161,6 +167,11 @@ config ARCH_MTD_XIP
|
|||
config GENERIC_HARDIRQS_NO__DO_IRQ
|
||||
def_bool y
|
||||
|
||||
config ARM_L1_CACHE_SHIFT_6
|
||||
bool
|
||||
help
|
||||
Setting ARM L1 cache line size to 64 Bytes.
|
||||
|
||||
if OPROFILE
|
||||
|
||||
config OPROFILE_ARMV6
|
||||
|
|
@ -550,10 +561,20 @@ config ARCH_W90X900
|
|||
<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
|
||||
ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
|
||||
|
||||
config ARCH_NUC93X
|
||||
bool "Nuvoton NUC93X CPU"
|
||||
select CPU_ARM926T
|
||||
select HAVE_CLK
|
||||
select COMMON_CLKDEV
|
||||
help
|
||||
Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
|
||||
low-power and high performance MPEG-4/JPEG multimedia controller chip.
|
||||
|
||||
config ARCH_PNX4008
|
||||
bool "Philips Nexperia PNX4008 Mobile"
|
||||
select CPU_ARM926T
|
||||
select HAVE_CLK
|
||||
select COMMON_CLKDEV
|
||||
help
|
||||
This enables support for Philips PNX4008 mobile platform.
|
||||
|
||||
|
|
@ -638,6 +659,7 @@ config ARCH_S5PC1XX
|
|||
select GENERIC_GPIO
|
||||
select HAVE_CLK
|
||||
select CPU_V7
|
||||
select ARM_L1_CACHE_SHIFT_6
|
||||
help
|
||||
Samsung S5PC1XX series based systems
|
||||
|
||||
|
|
@ -785,6 +807,8 @@ source "arch/arm/plat-nomadik/Kconfig"
|
|||
|
||||
source "arch/arm/mach-ns9xxx/Kconfig"
|
||||
|
||||
source "arch/arm/mach-nuc93x/Kconfig"
|
||||
|
||||
source "arch/arm/plat-omap/Kconfig"
|
||||
|
||||
source "arch/arm/mach-omap1/Kconfig"
|
||||
|
|
@ -867,6 +891,11 @@ config XSCALE_PMU
|
|||
depends on CPU_XSCALE && !XSCALE_PMU_TIMER
|
||||
default y
|
||||
|
||||
config CPU_HAS_PMU
|
||||
depends on CPU_V6 || CPU_V7 || XSCALE_PMU
|
||||
default y
|
||||
bool
|
||||
|
||||
if !MMU
|
||||
source "arch/arm/Kconfig-nommu"
|
||||
endif
|
||||
|
|
@ -921,6 +950,19 @@ config ARM_ERRATA_460075
|
|||
ACTLR register. Note that setting specific bits in the ACTLR register
|
||||
may not be available in non-secure mode.
|
||||
|
||||
config PL310_ERRATA_588369
|
||||
bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
|
||||
depends on CACHE_L2X0 && ARCH_OMAP4
|
||||
help
|
||||
The PL310 L2 cache controller implements three types of Clean &
|
||||
Invalidate maintenance operations: by Physical Address
|
||||
(offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
|
||||
They are architecturally defined to behave as the execution of a
|
||||
clean operation followed immediately by an invalidate operation,
|
||||
both performing to the same memory location. This functionality
|
||||
is not correctly implemented in PL310 as clean lines are not
|
||||
invalidated as a result of these operations. Note that this errata
|
||||
uses Texas Instrument's secure monitor api.
|
||||
endmenu
|
||||
|
||||
source "arch/arm/common/Kconfig"
|
||||
|
|
@ -1171,6 +1213,14 @@ config HIGHPTE
|
|||
depends on HIGHMEM
|
||||
depends on !OUTER_CACHE
|
||||
|
||||
config HW_PERF_EVENTS
|
||||
bool "Enable hardware performance counter support for perf events"
|
||||
depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7)
|
||||
default y
|
||||
help
|
||||
Enable hardware performance counter support for perf events. If
|
||||
disabled, perf events will use software events only.
|
||||
|
||||
source "mm/Kconfig"
|
||||
|
||||
config LEDS
|
||||
|
|
@ -1230,6 +1280,7 @@ config ALIGNMENT_TRAP
|
|||
bool
|
||||
depends on CPU_CP15_MMU
|
||||
default y if !ARCH_EBSA110
|
||||
select HAVE_PROC_CPU if PROC_FS
|
||||
help
|
||||
ARM processors cannot fetch/store information which is not
|
||||
naturally aligned on the bus, i.e., a 4 byte fetch must start at an
|
||||
|
|
|
|||
|
|
@ -171,6 +171,7 @@ machine-$(CONFIG_ARCH_U300) := u300
|
|||
machine-$(CONFIG_ARCH_U8500) := ux500
|
||||
machine-$(CONFIG_ARCH_VERSATILE) := versatile
|
||||
machine-$(CONFIG_ARCH_W90X900) := w90x900
|
||||
machine-$(CONFIG_ARCH_NUC93X) := nuc93x
|
||||
machine-$(CONFIG_FOOTBRIDGE) := footbridge
|
||||
|
||||
# Platform directory name. This list is sorted alphanumerically
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
#
|
||||
|
||||
HEAD = head.o
|
||||
OBJS = misc.o
|
||||
OBJS = misc.o decompress.o
|
||||
FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c
|
||||
|
||||
#
|
||||
|
|
@ -106,10 +106,6 @@ lib1funcs = $(obj)/lib1funcs.o
|
|||
$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE
|
||||
$(call cmd,shipped)
|
||||
|
||||
# Don't allow any static data in misc.o, which
|
||||
# would otherwise mess up our GOT table
|
||||
CFLAGS_misc.o := -Dstatic=
|
||||
|
||||
$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
|
||||
$(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE
|
||||
$(call if_changed,ld)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,45 @@
|
|||
#define _LINUX_STRING_H_
|
||||
|
||||
#include <linux/compiler.h> /* for inline */
|
||||
#include <linux/types.h> /* for size_t */
|
||||
#include <linux/stddef.h> /* for NULL */
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/string.h>
|
||||
|
||||
extern unsigned long free_mem_ptr;
|
||||
extern unsigned long free_mem_end_ptr;
|
||||
extern void error(char *);
|
||||
|
||||
#define STATIC static
|
||||
|
||||
#define ARCH_HAS_DECOMP_WDOG
|
||||
|
||||
/* Diagnostic functions */
|
||||
#ifdef DEBUG
|
||||
# define Assert(cond,msg) {if(!(cond)) error(msg);}
|
||||
# define Trace(x) fprintf x
|
||||
# define Tracev(x) {if (verbose) fprintf x ;}
|
||||
# define Tracevv(x) {if (verbose>1) fprintf x ;}
|
||||
# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
|
||||
# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
|
||||
#else
|
||||
# define Assert(cond,msg)
|
||||
# define Trace(x)
|
||||
# define Tracev(x)
|
||||
# define Tracevv(x)
|
||||
# define Tracec(c,x)
|
||||
# define Tracecv(c,x)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KERNEL_GZIP
|
||||
#include "../../../../lib/decompress_inflate.c"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KERNEL_LZO
|
||||
#include "../../../../lib/decompress_unlzo.c"
|
||||
#endif
|
||||
|
||||
void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
|
||||
{
|
||||
decompress(input, len, NULL, NULL, output, NULL, error);
|
||||
}
|
||||
|
|
@ -22,13 +22,13 @@
|
|||
#if defined(CONFIG_DEBUG_ICEDCC)
|
||||
|
||||
#ifdef CONFIG_CPU_V6
|
||||
.macro loadsp, rb
|
||||
.macro loadsp, rb, tmp
|
||||
.endm
|
||||
.macro writeb, ch, rb
|
||||
mcr p14, 0, \ch, c0, c5, 0
|
||||
.endm
|
||||
#elif defined(CONFIG_CPU_V7)
|
||||
.macro loadsp, rb
|
||||
.macro loadsp, rb, tmp
|
||||
.endm
|
||||
.macro writeb, ch, rb
|
||||
wait: mrc p14, 0, pc, c0, c1, 0
|
||||
|
|
@ -36,13 +36,13 @@ wait: mrc p14, 0, pc, c0, c1, 0
|
|||
mcr p14, 0, \ch, c0, c5, 0
|
||||
.endm
|
||||
#elif defined(CONFIG_CPU_XSCALE)
|
||||
.macro loadsp, rb
|
||||
.macro loadsp, rb, tmp
|
||||
.endm
|
||||
.macro writeb, ch, rb
|
||||
mcr p14, 0, \ch, c8, c0, 0
|
||||
.endm
|
||||
#else
|
||||
.macro loadsp, rb
|
||||
.macro loadsp, rb, tmp
|
||||
.endm
|
||||
.macro writeb, ch, rb
|
||||
mcr p14, 0, \ch, c1, c0, 0
|
||||
|
|
@ -58,7 +58,7 @@ wait: mrc p14, 0, pc, c0, c1, 0
|
|||
.endm
|
||||
|
||||
#if defined(CONFIG_ARCH_SA1100)
|
||||
.macro loadsp, rb
|
||||
.macro loadsp, rb, tmp
|
||||
mov \rb, #0x80000000 @ physical base address
|
||||
#ifdef CONFIG_DEBUG_LL_SER3
|
||||
add \rb, \rb, #0x00050000 @ Ser3
|
||||
|
|
@ -67,13 +67,13 @@ wait: mrc p14, 0, pc, c0, c1, 0
|
|||
#endif
|
||||
.endm
|
||||
#elif defined(CONFIG_ARCH_S3C2410)
|
||||
.macro loadsp, rb
|
||||
.macro loadsp, rb, tmp
|
||||
mov \rb, #0x50000000
|
||||
add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
|
||||
.endm
|
||||
#else
|
||||
.macro loadsp, rb
|
||||
addruart \rb
|
||||
.macro loadsp, rb, tmp
|
||||
addruart \rb, \tmp
|
||||
.endm
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -1025,7 +1025,7 @@ phex: adr r3, phexbuf
|
|||
strb r2, [r3, r1]
|
||||
b 1b
|
||||
|
||||
puts: loadsp r3
|
||||
puts: loadsp r3, r1
|
||||
1: ldrb r2, [r0], #1
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
|
@ -1042,7 +1042,7 @@ puts: loadsp r3
|
|||
putc:
|
||||
mov r2, r0
|
||||
mov r0, #0
|
||||
loadsp r3
|
||||
loadsp r3, r1
|
||||
b 2b
|
||||
|
||||
memdump: mov r12, r0
|
||||
|
|
|
|||
|
|
@ -23,8 +23,8 @@ unsigned int __machine_arch_type;
|
|||
#include <linux/compiler.h> /* for inline */
|
||||
#include <linux/types.h> /* for size_t */
|
||||
#include <linux/stddef.h> /* for NULL */
|
||||
#include <asm/string.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/string.h>
|
||||
|
||||
#include <asm/unaligned.h>
|
||||
|
||||
|
|
@ -117,57 +117,7 @@ static void putstr(const char *ptr)
|
|||
|
||||
#endif
|
||||
|
||||
#define __ptr_t void *
|
||||
|
||||
#define memzero(s,n) __memzero(s,n)
|
||||
|
||||
/*
|
||||
* Optimised C version of memzero for the ARM.
|
||||
*/
|
||||
void __memzero (__ptr_t s, size_t n)
|
||||
{
|
||||
union { void *vp; unsigned long *ulp; unsigned char *ucp; } u;
|
||||
int i;
|
||||
|
||||
u.vp = s;
|
||||
|
||||
for (i = n >> 5; i > 0; i--) {
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
}
|
||||
|
||||
if (n & 1 << 4) {
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
}
|
||||
|
||||
if (n & 1 << 3) {
|
||||
*u.ulp++ = 0;
|
||||
*u.ulp++ = 0;
|
||||
}
|
||||
|
||||
if (n & 1 << 2)
|
||||
*u.ulp++ = 0;
|
||||
|
||||
if (n & 1 << 1) {
|
||||
*u.ucp++ = 0;
|
||||
*u.ucp++ = 0;
|
||||
}
|
||||
|
||||
if (n & 1)
|
||||
*u.ucp++ = 0;
|
||||
}
|
||||
|
||||
static inline __ptr_t memcpy(__ptr_t __dest, __const __ptr_t __src,
|
||||
size_t __n)
|
||||
void *memcpy(void *__dest, __const void *__src, size_t __n)
|
||||
{
|
||||
int i = 0;
|
||||
unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
|
||||
|
|
@ -204,59 +154,20 @@ static inline __ptr_t memcpy(__ptr_t __dest, __const __ptr_t __src,
|
|||
/*
|
||||
* gzip delarations
|
||||
*/
|
||||
#define STATIC static
|
||||
|
||||
/* Diagnostic functions */
|
||||
#ifdef DEBUG
|
||||
# define Assert(cond,msg) {if(!(cond)) error(msg);}
|
||||
# define Trace(x) fprintf x
|
||||
# define Tracev(x) {if (verbose) fprintf x ;}
|
||||
# define Tracevv(x) {if (verbose>1) fprintf x ;}
|
||||
# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
|
||||
# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
|
||||
#else
|
||||
# define Assert(cond,msg)
|
||||
# define Trace(x)
|
||||
# define Tracev(x)
|
||||
# define Tracevv(x)
|
||||
# define Tracec(c,x)
|
||||
# define Tracecv(c,x)
|
||||
#endif
|
||||
|
||||
static void error(char *m);
|
||||
|
||||
extern char input_data[];
|
||||
extern char input_data_end[];
|
||||
|
||||
static unsigned char *output_data;
|
||||
static unsigned long output_ptr;
|
||||
unsigned char *output_data;
|
||||
unsigned long output_ptr;
|
||||
|
||||
static void error(char *m);
|
||||
|
||||
static void putstr(const char *);
|
||||
|
||||
static unsigned long free_mem_ptr;
|
||||
static unsigned long free_mem_end_ptr;
|
||||
|
||||
#ifdef STANDALONE_DEBUG
|
||||
#define NO_INFLATE_MALLOC
|
||||
#endif
|
||||
|
||||
#define ARCH_HAS_DECOMP_WDOG
|
||||
|
||||
#ifdef CONFIG_KERNEL_GZIP
|
||||
#include "../../../../lib/decompress_inflate.c"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KERNEL_LZO
|
||||
#include "../../../../lib/decompress_unlzo.c"
|
||||
#endif
|
||||
unsigned long free_mem_ptr;
|
||||
unsigned long free_mem_end_ptr;
|
||||
|
||||
#ifndef arch_error
|
||||
#define arch_error(x)
|
||||
#endif
|
||||
|
||||
static void error(char *x)
|
||||
void error(char *x)
|
||||
{
|
||||
arch_error(x);
|
||||
|
||||
|
|
@ -272,6 +183,8 @@ asmlinkage void __div0(void)
|
|||
error("Attempting division by 0!");
|
||||
}
|
||||
|
||||
extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
|
||||
|
||||
#ifndef STANDALONE_DEBUG
|
||||
|
||||
unsigned long
|
||||
|
|
@ -292,8 +205,8 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
|
|||
output_ptr = get_unaligned_le32(tmp);
|
||||
|
||||
putstr("Uncompressing Linux...");
|
||||
decompress(input_data, input_data_end - input_data,
|
||||
NULL, NULL, output_data, NULL, error);
|
||||
do_decompress(input_data, input_data_end - input_data,
|
||||
output_data, error);
|
||||
putstr(" done, booting the kernel.\n");
|
||||
return output_ptr;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,6 +14,13 @@ SECTIONS
|
|||
/DISCARD/ : {
|
||||
*(.ARM.exidx*)
|
||||
*(.ARM.extab*)
|
||||
/*
|
||||
* Discard any r/w data - this produces a link error if we have any,
|
||||
* which is required for PIC decompression. Local data generates
|
||||
* GOTOFF relocations, which prevents it being relocated independently
|
||||
* of the text/got segments.
|
||||
*/
|
||||
*(.data)
|
||||
}
|
||||
|
||||
. = TEXT_START;
|
||||
|
|
@ -40,7 +47,6 @@ SECTIONS
|
|||
.got : { *(.got) }
|
||||
_got_end = .;
|
||||
.got.plt : { *(.got.plt) }
|
||||
.data : { *(.data) }
|
||||
_edata = .;
|
||||
|
||||
. = BSS_START;
|
||||
|
|
|
|||
|
|
@ -99,6 +99,16 @@ void clkdev_add(struct clk_lookup *cl)
|
|||
}
|
||||
EXPORT_SYMBOL(clkdev_add);
|
||||
|
||||
void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
|
||||
{
|
||||
mutex_lock(&clocks_mutex);
|
||||
while (num--) {
|
||||
list_add_tail(&cl->node, &clocks);
|
||||
cl++;
|
||||
}
|
||||
mutex_unlock(&clocks_mutex);
|
||||
}
|
||||
|
||||
#define MAX_DEV_ID 20
|
||||
#define MAX_CON_ID 16
|
||||
|
||||
|
|
|
|||
|
|
@ -277,7 +277,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
|
|||
* We don't need to sync the DMA buffer since
|
||||
* it was allocated via the coherent allocators.
|
||||
*/
|
||||
dma_cache_maint(ptr, size, dir);
|
||||
__dma_single_cpu_to_dev(ptr, size, dir);
|
||||
}
|
||||
|
||||
return dma_addr;
|
||||
|
|
@ -315,6 +315,8 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
|
|||
__cpuc_flush_dcache_area(ptr, size);
|
||||
}
|
||||
free_safe_buffer(dev->archdata.dmabounce, buf);
|
||||
} else {
|
||||
__dma_single_dev_to_cpu(dma_to_virt(dev, dma_addr), size, dir);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/io.h>
|
||||
|
|
@ -28,48 +29,6 @@
|
|||
#include <asm/mach/irq.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
|
||||
static void vic_ack_irq(unsigned int irq)
|
||||
{
|
||||
void __iomem *base = get_irq_chip_data(irq);
|
||||
irq &= 31;
|
||||
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
|
||||
/* moreover, clear the soft-triggered, in case it was the reason */
|
||||
writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
|
||||
}
|
||||
|
||||
static void vic_mask_irq(unsigned int irq)
|
||||
{
|
||||
void __iomem *base = get_irq_chip_data(irq);
|
||||
irq &= 31;
|
||||
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
|
||||
}
|
||||
|
||||
static void vic_unmask_irq(unsigned int irq)
|
||||
{
|
||||
void __iomem *base = get_irq_chip_data(irq);
|
||||
irq &= 31;
|
||||
writel(1 << irq, base + VIC_INT_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* vic_init2 - common initialisation code
|
||||
* @base: Base of the VIC.
|
||||
*
|
||||
* Common initialisation code for registeration
|
||||
* and resume.
|
||||
*/
|
||||
static void vic_init2(void __iomem *base)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
|
||||
writel(VIC_VECT_CNTL_ENABLE | i, reg);
|
||||
}
|
||||
|
||||
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PM)
|
||||
/**
|
||||
* struct vic_device - VIC PM device
|
||||
|
|
@ -99,13 +58,34 @@ struct vic_device {
|
|||
/* we cannot allocate memory when VICs are initially registered */
|
||||
static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
|
||||
|
||||
static int vic_id;
|
||||
|
||||
static inline struct vic_device *to_vic(struct sys_device *sys)
|
||||
{
|
||||
return container_of(sys, struct vic_device, sysdev);
|
||||
}
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static int vic_id;
|
||||
/**
|
||||
* vic_init2 - common initialisation code
|
||||
* @base: Base of the VIC.
|
||||
*
|
||||
* Common initialisation code for registeration
|
||||
* and resume.
|
||||
*/
|
||||
static void vic_init2(void __iomem *base)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
|
||||
writel(VIC_VECT_CNTL_ENABLE | i, reg);
|
||||
}
|
||||
|
||||
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PM)
|
||||
static int vic_class_resume(struct sys_device *dev)
|
||||
{
|
||||
struct vic_device *vic = to_vic(dev);
|
||||
|
|
@ -158,31 +138,6 @@ struct sysdev_class vic_class = {
|
|||
.resume = vic_class_resume,
|
||||
};
|
||||
|
||||
/**
|
||||
* vic_pm_register - Register a VIC for later power management control
|
||||
* @base: The base address of the VIC.
|
||||
* @irq: The base IRQ for the VIC.
|
||||
* @resume_sources: bitmask of interrupts allowed for resume sources.
|
||||
*
|
||||
* Register the VIC with the system device tree so that it can be notified
|
||||
* of suspend and resume requests and ensure that the correct actions are
|
||||
* taken to re-instate the settings on resume.
|
||||
*/
|
||||
static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
|
||||
{
|
||||
struct vic_device *v;
|
||||
|
||||
if (vic_id >= ARRAY_SIZE(vic_devices))
|
||||
printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
|
||||
else {
|
||||
v = &vic_devices[vic_id];
|
||||
v->base = base;
|
||||
v->resume_sources = resume_sources;
|
||||
v->irq = irq;
|
||||
vic_id++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* vic_pm_init - initicall to register VIC pm
|
||||
*
|
||||
|
|
@ -219,9 +174,60 @@ static int __init vic_pm_init(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
late_initcall(vic_pm_init);
|
||||
|
||||
/**
|
||||
* vic_pm_register - Register a VIC for later power management control
|
||||
* @base: The base address of the VIC.
|
||||
* @irq: The base IRQ for the VIC.
|
||||
* @resume_sources: bitmask of interrupts allowed for resume sources.
|
||||
*
|
||||
* Register the VIC with the system device tree so that it can be notified
|
||||
* of suspend and resume requests and ensure that the correct actions are
|
||||
* taken to re-instate the settings on resume.
|
||||
*/
|
||||
static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
|
||||
{
|
||||
struct vic_device *v;
|
||||
|
||||
if (vic_id >= ARRAY_SIZE(vic_devices))
|
||||
printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
|
||||
else {
|
||||
v = &vic_devices[vic_id];
|
||||
v->base = base;
|
||||
v->resume_sources = resume_sources;
|
||||
v->irq = irq;
|
||||
vic_id++;
|
||||
}
|
||||
}
|
||||
#else
|
||||
static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static void vic_ack_irq(unsigned int irq)
|
||||
{
|
||||
void __iomem *base = get_irq_chip_data(irq);
|
||||
irq &= 31;
|
||||
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
|
||||
/* moreover, clear the soft-triggered, in case it was the reason */
|
||||
writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
|
||||
}
|
||||
|
||||
static void vic_mask_irq(unsigned int irq)
|
||||
{
|
||||
void __iomem *base = get_irq_chip_data(irq);
|
||||
irq &= 31;
|
||||
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
|
||||
}
|
||||
|
||||
static void vic_unmask_irq(unsigned int irq)
|
||||
{
|
||||
void __iomem *base = get_irq_chip_data(irq);
|
||||
irq &= 31;
|
||||
writel(1 << irq, base + VIC_INT_ENABLE);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PM)
|
||||
static struct vic_device *vic_from_irq(unsigned int irq)
|
||||
{
|
||||
struct vic_device *v = vic_devices;
|
||||
|
|
@ -255,10 +261,7 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
|
||||
|
||||
#define vic_set_wake NULL
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
|
|
@ -270,80 +273,6 @@ static struct irq_chip vic_chip = {
|
|||
.set_wake = vic_set_wake,
|
||||
};
|
||||
|
||||
/* The PL190 cell from ARM has been modified by ST, so handle both here */
|
||||
static void vik_init_st(void __iomem *base, unsigned int irq_start,
|
||||
u32 vic_sources);
|
||||
|
||||
/**
|
||||
* vic_init - initialise a vectored interrupt controller
|
||||
* @base: iomem base address
|
||||
* @irq_start: starting interrupt number, must be muliple of 32
|
||||
* @vic_sources: bitmask of interrupt sources to allow
|
||||
* @resume_sources: bitmask of interrupt sources to allow for resume
|
||||
*/
|
||||
void __init vic_init(void __iomem *base, unsigned int irq_start,
|
||||
u32 vic_sources, u32 resume_sources)
|
||||
{
|
||||
unsigned int i;
|
||||
u32 cellid = 0;
|
||||
enum amba_vendor vendor;
|
||||
|
||||
/* Identify which VIC cell this one is, by reading the ID */
|
||||
for (i = 0; i < 4; i++) {
|
||||
u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
|
||||
cellid |= (readl(addr) & 0xff) << (8 * i);
|
||||
}
|
||||
vendor = (cellid >> 12) & 0xff;
|
||||
printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
|
||||
base, cellid, vendor);
|
||||
|
||||
switch(vendor) {
|
||||
case AMBA_VENDOR_ST:
|
||||
vik_init_st(base, irq_start, vic_sources);
|
||||
return;
|
||||
default:
|
||||
printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
|
||||
/* fall through */
|
||||
case AMBA_VENDOR_ARM:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable all interrupts initially. */
|
||||
|
||||
writel(0, base + VIC_INT_SELECT);
|
||||
writel(0, base + VIC_INT_ENABLE);
|
||||
writel(~0, base + VIC_INT_ENABLE_CLEAR);
|
||||
writel(0, base + VIC_IRQ_STATUS);
|
||||
writel(0, base + VIC_ITCR);
|
||||
writel(~0, base + VIC_INT_SOFT_CLEAR);
|
||||
|
||||
/*
|
||||
* Make sure we clear all existing interrupts
|
||||
*/
|
||||
writel(0, base + VIC_PL190_VECT_ADDR);
|
||||
for (i = 0; i < 19; i++) {
|
||||
unsigned int value;
|
||||
|
||||
value = readl(base + VIC_PL190_VECT_ADDR);
|
||||
writel(value, base + VIC_PL190_VECT_ADDR);
|
||||
}
|
||||
|
||||
vic_init2(base);
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
if (vic_sources & (1 << i)) {
|
||||
unsigned int irq = irq_start + i;
|
||||
|
||||
set_irq_chip(irq, &vic_chip);
|
||||
set_irq_chip_data(irq, base);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
||||
vic_pm_register(base, irq_start, resume_sources);
|
||||
}
|
||||
|
||||
/*
|
||||
* The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
|
||||
* The original cell has 32 interrupts, while the modified one has 64,
|
||||
|
|
@ -351,7 +280,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
|
|||
* the probe function is called twice, with base set to offset 000
|
||||
* and 020 within the page. We call this "second block".
|
||||
*/
|
||||
static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
|
||||
static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
|
||||
u32 vic_sources)
|
||||
{
|
||||
unsigned int i;
|
||||
|
|
@ -400,3 +329,73 @@ static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* vic_init - initialise a vectored interrupt controller
|
||||
* @base: iomem base address
|
||||
* @irq_start: starting interrupt number, must be muliple of 32
|
||||
* @vic_sources: bitmask of interrupt sources to allow
|
||||
* @resume_sources: bitmask of interrupt sources to allow for resume
|
||||
*/
|
||||
void __init vic_init(void __iomem *base, unsigned int irq_start,
|
||||
u32 vic_sources, u32 resume_sources)
|
||||
{
|
||||
unsigned int i;
|
||||
u32 cellid = 0;
|
||||
enum amba_vendor vendor;
|
||||
|
||||
/* Identify which VIC cell this one is, by reading the ID */
|
||||
for (i = 0; i < 4; i++) {
|
||||
u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
|
||||
cellid |= (readl(addr) & 0xff) << (8 * i);
|
||||
}
|
||||
vendor = (cellid >> 12) & 0xff;
|
||||
printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
|
||||
base, cellid, vendor);
|
||||
|
||||
switch(vendor) {
|
||||
case AMBA_VENDOR_ST:
|
||||
vic_init_st(base, irq_start, vic_sources);
|
||||
return;
|
||||
default:
|
||||
printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
|
||||
/* fall through */
|
||||
case AMBA_VENDOR_ARM:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable all interrupts initially. */
|
||||
|
||||
writel(0, base + VIC_INT_SELECT);
|
||||
writel(0, base + VIC_INT_ENABLE);
|
||||
writel(~0, base + VIC_INT_ENABLE_CLEAR);
|
||||
writel(0, base + VIC_IRQ_STATUS);
|
||||
writel(0, base + VIC_ITCR);
|
||||
writel(~0, base + VIC_INT_SOFT_CLEAR);
|
||||
|
||||
/*
|
||||
* Make sure we clear all existing interrupts
|
||||
*/
|
||||
writel(0, base + VIC_PL190_VECT_ADDR);
|
||||
for (i = 0; i < 19; i++) {
|
||||
unsigned int value;
|
||||
|
||||
value = readl(base + VIC_PL190_VECT_ADDR);
|
||||
writel(value, base + VIC_PL190_VECT_ADDR);
|
||||
}
|
||||
|
||||
vic_init2(base);
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
if (vic_sources & (1 << i)) {
|
||||
unsigned int irq = irq_start + i;
|
||||
|
||||
set_irq_chip(irq, &vic_chip);
|
||||
set_irq_chip_data(irq, base);
|
||||
set_irq_handler(irq, handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
||||
vic_pm_register(base, irq_start, resume_sources);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -201,7 +201,7 @@ CONFIG_ARCH_OMAP3=y
|
|||
# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
|
||||
# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
|
||||
CONFIG_OMAP_RESET_CLOCKS=y
|
||||
# CONFIG_OMAP_MUX is not set
|
||||
CONFIG_OMAP_MUX=y
|
||||
# CONFIG_OMAP_MCBSP is not set
|
||||
# CONFIG_OMAP_MBOX_FWK is not set
|
||||
# CONFIG_OMAP_MPU_TIMER is not set
|
||||
|
|
@ -590,7 +590,46 @@ CONFIG_HW_RANDOM=y
|
|||
# CONFIG_R3964 is not set
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
# CONFIG_TCG_TPM is not set
|
||||
# CONFIG_I2C is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
|
||||
#
|
||||
# I2C Hardware Bus support
|
||||
#
|
||||
|
||||
#
|
||||
# I2C system bus drivers (mostly embedded / system-on-chip)
|
||||
#
|
||||
# CONFIG_I2C_DESIGNWARE is not set
|
||||
# CONFIG_I2C_GPIO is not set
|
||||
# CONFIG_I2C_OCORES is not set
|
||||
CONFIG_I2C_OMAP=y
|
||||
# CONFIG_I2C_SIMTEC is not set
|
||||
|
||||
#
|
||||
# External I2C/SMBus adapter drivers
|
||||
#
|
||||
# CONFIG_I2C_PARPORT_LIGHT is not set
|
||||
# CONFIG_I2C_TAOS_EVM is not set
|
||||
# CONFIG_I2C_TINY_USB is not set
|
||||
|
||||
#
|
||||
# Other I2C/SMBus bus drivers
|
||||
#
|
||||
# CONFIG_I2C_PCA_PLATFORM is not set
|
||||
# CONFIG_I2C_STUB is not set
|
||||
|
||||
#
|
||||
# Miscellaneous I2C Chip support
|
||||
#
|
||||
# CONFIG_SENSORS_TSL2550 is not set
|
||||
# CONFIG_I2C_DEBUG_CORE is not set
|
||||
# CONFIG_I2C_DEBUG_ALGO is not set
|
||||
# CONFIG_I2C_DEBUG_BUS is not set
|
||||
# CONFIG_I2C_DEBUG_CHIP is not set
|
||||
# CONFIG_SPI is not set
|
||||
|
||||
#
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.32-rc6
|
||||
# Fri Nov 13 12:01:17 2009
|
||||
# Linux kernel version: 2.6.33-rc3
|
||||
# Thu Jan 7 16:14:55 2010
|
||||
#
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
|
|
@ -46,6 +46,7 @@ CONFIG_BSD_PROCESS_ACCT=y
|
|||
#
|
||||
CONFIG_TREE_RCU=y
|
||||
# CONFIG_TREE_PREEMPT_RCU is not set
|
||||
# CONFIG_TINY_RCU is not set
|
||||
# CONFIG_RCU_TRACE is not set
|
||||
CONFIG_RCU_FANOUT=32
|
||||
# CONFIG_RCU_FANOUT_EXACT is not set
|
||||
|
|
@ -126,14 +127,41 @@ CONFIG_LBDAF=y
|
|||
# IO Schedulers
|
||||
#
|
||||
CONFIG_IOSCHED_NOOP=y
|
||||
CONFIG_IOSCHED_AS=y
|
||||
CONFIG_IOSCHED_DEADLINE=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
CONFIG_DEFAULT_AS=y
|
||||
# CONFIG_DEFAULT_DEADLINE is not set
|
||||
# CONFIG_DEFAULT_CFQ is not set
|
||||
CONFIG_DEFAULT_CFQ=y
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="anticipatory"
|
||||
CONFIG_DEFAULT_IOSCHED="cfq"
|
||||
# CONFIG_INLINE_SPIN_TRYLOCK is not set
|
||||
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
|
||||
# CONFIG_INLINE_SPIN_LOCK is not set
|
||||
# CONFIG_INLINE_SPIN_LOCK_BH is not set
|
||||
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
|
||||
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
|
||||
CONFIG_INLINE_SPIN_UNLOCK=y
|
||||
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
|
||||
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
|
||||
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
|
||||
# CONFIG_INLINE_READ_TRYLOCK is not set
|
||||
# CONFIG_INLINE_READ_LOCK is not set
|
||||
# CONFIG_INLINE_READ_LOCK_BH is not set
|
||||
# CONFIG_INLINE_READ_LOCK_IRQ is not set
|
||||
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
|
||||
CONFIG_INLINE_READ_UNLOCK=y
|
||||
# CONFIG_INLINE_READ_UNLOCK_BH is not set
|
||||
CONFIG_INLINE_READ_UNLOCK_IRQ=y
|
||||
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
|
||||
# CONFIG_INLINE_WRITE_TRYLOCK is not set
|
||||
# CONFIG_INLINE_WRITE_LOCK is not set
|
||||
# CONFIG_INLINE_WRITE_LOCK_BH is not set
|
||||
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
|
||||
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
|
||||
CONFIG_INLINE_WRITE_UNLOCK=y
|
||||
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
|
||||
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
|
||||
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
|
||||
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
|
||||
# CONFIG_FREEZER is not set
|
||||
|
||||
#
|
||||
|
|
@ -162,6 +190,7 @@ CONFIG_MMU=y
|
|||
# CONFIG_ARCH_IXP2000 is not set
|
||||
# CONFIG_ARCH_IXP4XX is not set
|
||||
# CONFIG_ARCH_L7200 is not set
|
||||
# CONFIG_ARCH_DOVE is not set
|
||||
# CONFIG_ARCH_KIRKWOOD is not set
|
||||
# CONFIG_ARCH_LOKI is not set
|
||||
# CONFIG_ARCH_MV78XX0 is not set
|
||||
|
|
@ -184,6 +213,7 @@ CONFIG_MMU=y
|
|||
# CONFIG_ARCH_DAVINCI is not set
|
||||
CONFIG_ARCH_OMAP=y
|
||||
# CONFIG_ARCH_BCMRING is not set
|
||||
# CONFIG_ARCH_U8500 is not set
|
||||
|
||||
#
|
||||
# TI OMAP Implementations
|
||||
|
|
@ -197,12 +227,8 @@ CONFIG_ARCH_OMAP3=y
|
|||
#
|
||||
# OMAP Feature Selections
|
||||
#
|
||||
# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
|
||||
# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
|
||||
# CONFIG_OMAP_RESET_CLOCKS is not set
|
||||
CONFIG_OMAP_MUX=y
|
||||
CONFIG_OMAP_MUX_DEBUG=y
|
||||
CONFIG_OMAP_MUX_WARNINGS=y
|
||||
CONFIG_OMAP_RESET_CLOCKS=y
|
||||
# CONFIG_OMAP_MUX is not set
|
||||
CONFIG_OMAP_MCBSP=y
|
||||
# CONFIG_OMAP_MBOX_FWK is not set
|
||||
# CONFIG_OMAP_MPU_TIMER is not set
|
||||
|
|
@ -217,6 +243,7 @@ CONFIG_OMAP_LL_DEBUG_UART3=y
|
|||
CONFIG_OMAP_PM_NOOP=y
|
||||
CONFIG_ARCH_OMAP34XX=y
|
||||
CONFIG_ARCH_OMAP3430=y
|
||||
CONFIG_OMAP_PACKAGE_CBB=y
|
||||
|
||||
#
|
||||
# OMAP Board Type
|
||||
|
|
@ -227,13 +254,16 @@ CONFIG_ARCH_OMAP3430=y
|
|||
# CONFIG_MACH_OMAP3EVM is not set
|
||||
# CONFIG_MACH_OMAP3517EVM is not set
|
||||
# CONFIG_MACH_OMAP3_PANDORA is not set
|
||||
# CONFIG_MACH_OMAP3_TOUCHBOOK is not set
|
||||
# CONFIG_MACH_OMAP_3430SDP is not set
|
||||
# CONFIG_MACH_NOKIA_RX51 is not set
|
||||
# CONFIG_MACH_OMAP_ZOOM2 is not set
|
||||
# CONFIG_MACH_CM_T35 is not set
|
||||
# CONFIG_MACH_OMAP_ZOOM3 is not set
|
||||
# CONFIG_MACH_OMAP_3630SDP is not set
|
||||
# CONFIG_MACH_CM_T35 is not set
|
||||
CONFIG_MACH_IGEP0020=y
|
||||
# CONFIG_MACH_OMAP_3630SDP is not set
|
||||
# CONFIG_OMAP3_EMU is not set
|
||||
# CONFIG_OMAP3_SDRC_AC_TIMING is not set
|
||||
|
||||
#
|
||||
# Processor Type
|
||||
|
|
@ -305,8 +335,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
|
|||
# CONFIG_PHYS_ADDR_T_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
CONFIG_VIRT_TO_BUS=y
|
||||
CONFIG_HAVE_MLOCK=y
|
||||
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
|
||||
# CONFIG_KSM is not set
|
||||
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
|
||||
# CONFIG_LEDS is not set
|
||||
|
|
@ -440,35 +468,35 @@ CONFIG_BT_HIDP=m
|
|||
#
|
||||
# Bluetooth device drivers
|
||||
#
|
||||
CONFIG_BT_HCIBTUSB=m
|
||||
# CONFIG_BT_HCIBTUSB is not set
|
||||
# CONFIG_BT_HCIBTSDIO is not set
|
||||
CONFIG_BT_HCIUART=m
|
||||
CONFIG_BT_HCIUART_H4=y
|
||||
CONFIG_BT_HCIUART_BCSP=y
|
||||
CONFIG_BT_HCIUART_LL=y
|
||||
CONFIG_BT_HCIBCM203X=m
|
||||
CONFIG_BT_HCIBPA10X=m
|
||||
CONFIG_BT_HCIBFUSB=m
|
||||
# CONFIG_BT_HCIBCM203X is not set
|
||||
# CONFIG_BT_HCIBPA10X is not set
|
||||
# CONFIG_BT_HCIBFUSB is not set
|
||||
CONFIG_BT_HCIVHCI=m
|
||||
CONFIG_BT_MRVL=m
|
||||
CONFIG_BT_MRVL_SDIO=m
|
||||
# CONFIG_AF_RXRPC is not set
|
||||
CONFIG_WIRELESS=y
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_WIRELESS_EXT=y
|
||||
CONFIG_WEXT_CORE=y
|
||||
CONFIG_WEXT_PROC=y
|
||||
CONFIG_WEXT_SPY=y
|
||||
CONFIG_CFG80211=y
|
||||
# CONFIG_NL80211_TESTMODE is not set
|
||||
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
|
||||
# CONFIG_CFG80211_REG_DEBUG is not set
|
||||
CONFIG_CFG80211_DEFAULT_PS=y
|
||||
CONFIG_CFG80211_DEFAULT_PS_VALUE=1
|
||||
# CONFIG_WIRELESS_OLD_REGULATORY is not set
|
||||
CONFIG_WIRELESS_EXT=y
|
||||
CONFIG_CFG80211_WEXT=y
|
||||
CONFIG_WIRELESS_EXT_SYSFS=y
|
||||
CONFIG_LIB80211=m
|
||||
CONFIG_LIB80211_CRYPT_WEP=m
|
||||
CONFIG_LIB80211_CRYPT_CCMP=m
|
||||
CONFIG_LIB80211_CRYPT_TKIP=m
|
||||
CONFIG_LIB80211=y
|
||||
# CONFIG_LIB80211_DEBUG is not set
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211=y
|
||||
# CONFIG_MAC80211_RC_PID is not set
|
||||
CONFIG_MAC80211_RC_MINSTREL=y
|
||||
# CONFIG_MAC80211_RC_DEFAULT_PID is not set
|
||||
|
|
@ -500,12 +528,95 @@ CONFIG_EXTRA_FIRMWARE=""
|
|||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
CONFIG_CONNECTOR=y
|
||||
CONFIG_PROC_EVENTS=y
|
||||
# CONFIG_MTD is not set
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_MTD_DEBUG is not set
|
||||
# CONFIG_MTD_TESTS is not set
|
||||
# CONFIG_MTD_CONCAT is not set
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_AFS_PARTS is not set
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
|
||||
#
|
||||
# User Modules And Translation Layers
|
||||
#
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLKDEVS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
# CONFIG_FTL is not set
|
||||
# CONFIG_NFTL is not set
|
||||
# CONFIG_INFTL is not set
|
||||
# CONFIG_RFD_FTL is not set
|
||||
# CONFIG_SSFDC is not set
|
||||
# CONFIG_MTD_OOPS is not set
|
||||
|
||||
#
|
||||
# RAM/ROM/Flash chip drivers
|
||||
#
|
||||
# CONFIG_MTD_CFI is not set
|
||||
# CONFIG_MTD_JEDECPROBE is not set
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_1=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_2=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_4=y
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
|
||||
CONFIG_MTD_CFI_I1=y
|
||||
CONFIG_MTD_CFI_I2=y
|
||||
# CONFIG_MTD_CFI_I4 is not set
|
||||
# CONFIG_MTD_CFI_I8 is not set
|
||||
# CONFIG_MTD_RAM is not set
|
||||
# CONFIG_MTD_ROM is not set
|
||||
# CONFIG_MTD_ABSENT is not set
|
||||
|
||||
#
|
||||
# Mapping drivers for chip access
|
||||
#
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
# CONFIG_MTD_PLATRAM is not set
|
||||
|
||||
#
|
||||
# Self-contained MTD device drivers
|
||||
#
|
||||
# CONFIG_MTD_DATAFLASH is not set
|
||||
# CONFIG_MTD_M25P80 is not set
|
||||
# CONFIG_MTD_SST25L is not set
|
||||
# CONFIG_MTD_SLRAM is not set
|
||||
# CONFIG_MTD_PHRAM is not set
|
||||
# CONFIG_MTD_MTDRAM is not set
|
||||
# CONFIG_MTD_BLOCK2MTD is not set
|
||||
|
||||
#
|
||||
# Disk-On-Chip Device Drivers
|
||||
#
|
||||
# CONFIG_MTD_DOC2000 is not set
|
||||
# CONFIG_MTD_DOC2001 is not set
|
||||
# CONFIG_MTD_DOC2001PLUS is not set
|
||||
# CONFIG_MTD_NAND is not set
|
||||
CONFIG_MTD_ONENAND=y
|
||||
# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
|
||||
# CONFIG_MTD_ONENAND_GENERIC is not set
|
||||
CONFIG_MTD_ONENAND_OMAP2=y
|
||||
# CONFIG_MTD_ONENAND_OTP is not set
|
||||
CONFIG_MTD_ONENAND_2X_PROGRAM=y
|
||||
# CONFIG_MTD_ONENAND_SIM is not set
|
||||
|
||||
#
|
||||
# LPDDR flash memory drivers
|
||||
#
|
||||
# CONFIG_MTD_LPDDR is not set
|
||||
|
||||
#
|
||||
# UBI - Unsorted block images
|
||||
#
|
||||
# CONFIG_MTD_UBI is not set
|
||||
# CONFIG_PARPORT is not set
|
||||
CONFIG_BLK_DEV=y
|
||||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
|
||||
# CONFIG_BLK_DEV_DRBD is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_UB is not set
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
|
|
@ -516,7 +627,6 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
|
|||
# CONFIG_ATA_OVER_ETH is not set
|
||||
# CONFIG_MG_DISK is not set
|
||||
# CONFIG_MISC_DEVICES is not set
|
||||
CONFIG_EEPROM_93CX6=m
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
|
|
@ -613,56 +723,26 @@ CONFIG_SMSC911X=y
|
|||
# CONFIG_NETDEV_1000 is not set
|
||||
# CONFIG_NETDEV_10000 is not set
|
||||
CONFIG_WLAN=y
|
||||
# CONFIG_WLAN_PRE80211 is not set
|
||||
CONFIG_WLAN_80211=y
|
||||
CONFIG_LIBERTAS=m
|
||||
CONFIG_LIBERTAS_USB=m
|
||||
CONFIG_LIBERTAS_SDIO=m
|
||||
# CONFIG_LIBERTAS_THINFIRM is not set
|
||||
# CONFIG_AT76C50X_USB is not set
|
||||
# CONFIG_USB_ZD1201 is not set
|
||||
# CONFIG_USB_NET_RNDIS_WLAN is not set
|
||||
# CONFIG_RTL8187 is not set
|
||||
# CONFIG_MAC80211_HWSIM is not set
|
||||
# CONFIG_ATH_COMMON is not set
|
||||
# CONFIG_B43 is not set
|
||||
# CONFIG_B43LEGACY is not set
|
||||
# CONFIG_HOSTAP is not set
|
||||
# CONFIG_IWM is not set
|
||||
CONFIG_LIBERTAS=y
|
||||
# CONFIG_LIBERTAS_USB is not set
|
||||
CONFIG_LIBERTAS_SDIO=y
|
||||
# CONFIG_LIBERTAS_SPI is not set
|
||||
# CONFIG_LIBERTAS_DEBUG is not set
|
||||
# CONFIG_LIBERTAS_THINFIRM is not set
|
||||
CONFIG_AT76C50X_USB=m
|
||||
CONFIG_USB_ZD1201=m
|
||||
CONFIG_USB_NET_RNDIS_WLAN=m
|
||||
CONFIG_RTL8187=m
|
||||
# CONFIG_MAC80211_HWSIM is not set
|
||||
CONFIG_P54_COMMON=m
|
||||
CONFIG_P54_USB=m
|
||||
CONFIG_P54_SPI=m
|
||||
CONFIG_ATH_COMMON=m
|
||||
CONFIG_AR9170_USB=m
|
||||
CONFIG_HOSTAP=m
|
||||
CONFIG_HOSTAP_FIRMWARE=y
|
||||
CONFIG_HOSTAP_FIRMWARE_NVRAM=y
|
||||
CONFIG_B43=m
|
||||
# CONFIG_B43_SDIO is not set
|
||||
# CONFIG_B43_PHY_LP is not set
|
||||
CONFIG_B43_HWRNG=y
|
||||
# CONFIG_B43_DEBUG is not set
|
||||
CONFIG_B43LEGACY=m
|
||||
CONFIG_B43LEGACY_HWRNG=y
|
||||
# CONFIG_B43LEGACY_DEBUG is not set
|
||||
CONFIG_B43LEGACY_DMA=y
|
||||
CONFIG_B43LEGACY_PIO=y
|
||||
CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
|
||||
# CONFIG_B43LEGACY_DMA_MODE is not set
|
||||
# CONFIG_B43LEGACY_PIO_MODE is not set
|
||||
CONFIG_ZD1211RW=m
|
||||
# CONFIG_ZD1211RW_DEBUG is not set
|
||||
CONFIG_RT2X00=m
|
||||
CONFIG_RT2500USB=m
|
||||
CONFIG_RT73USB=m
|
||||
CONFIG_RT2800USB=m
|
||||
CONFIG_RT2X00_LIB_USB=m
|
||||
CONFIG_RT2X00_LIB=m
|
||||
CONFIG_RT2X00_LIB_HT=y
|
||||
CONFIG_RT2X00_LIB_FIRMWARE=y
|
||||
CONFIG_RT2X00_LIB_CRYPTO=y
|
||||
# CONFIG_RT2X00_DEBUG is not set
|
||||
CONFIG_WL12XX=m
|
||||
# CONFIG_WL1251 is not set
|
||||
# CONFIG_WL1271 is not set
|
||||
# CONFIG_IWM is not set
|
||||
# CONFIG_P54_COMMON is not set
|
||||
# CONFIG_RT2X00 is not set
|
||||
# CONFIG_WL12XX is not set
|
||||
# CONFIG_ZD1211RW is not set
|
||||
|
||||
#
|
||||
# Enable WiMAX (Networking options) to see the WiMAX drivers
|
||||
|
|
@ -672,29 +752,10 @@ CONFIG_WL12XX=m
|
|||
# USB Network Adapters
|
||||
#
|
||||
# CONFIG_USB_CATC is not set
|
||||
CONFIG_USB_KAWETH=m
|
||||
CONFIG_USB_PEGASUS=m
|
||||
# CONFIG_USB_KAWETH is not set
|
||||
# CONFIG_USB_PEGASUS is not set
|
||||
# CONFIG_USB_RTL8150 is not set
|
||||
CONFIG_USB_USBNET=m
|
||||
CONFIG_USB_NET_AX8817X=m
|
||||
CONFIG_USB_NET_CDCETHER=m
|
||||
CONFIG_USB_NET_CDC_EEM=m
|
||||
CONFIG_USB_NET_DM9601=m
|
||||
CONFIG_USB_NET_SMSC95XX=m
|
||||
CONFIG_USB_NET_GL620A=m
|
||||
CONFIG_USB_NET_NET1080=m
|
||||
CONFIG_USB_NET_PLUSB=m
|
||||
CONFIG_USB_NET_MCS7830=m
|
||||
CONFIG_USB_NET_RNDIS_HOST=m
|
||||
CONFIG_USB_NET_CDC_SUBSET=m
|
||||
# CONFIG_USB_ALI_M5632 is not set
|
||||
# CONFIG_USB_AN2720 is not set
|
||||
CONFIG_USB_BELKIN=y
|
||||
CONFIG_USB_ARMLINUX=y
|
||||
# CONFIG_USB_EPSON2888 is not set
|
||||
# CONFIG_USB_KC2190 is not set
|
||||
CONFIG_USB_NET_ZAURUS=m
|
||||
# CONFIG_USB_NET_INT51X1 is not set
|
||||
# CONFIG_USB_USBNET is not set
|
||||
# CONFIG_WAN is not set
|
||||
# CONFIG_PPP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
|
|
@ -710,6 +771,7 @@ CONFIG_USB_NET_ZAURUS=m
|
|||
CONFIG_INPUT=y
|
||||
# CONFIG_INPUT_FF_MEMLESS is not set
|
||||
# CONFIG_INPUT_POLLDEV is not set
|
||||
# CONFIG_INPUT_SPARSEKMAP is not set
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
|
|
@ -809,7 +871,6 @@ CONFIG_I2C_OMAP=y
|
|||
#
|
||||
# Miscellaneous I2C Chip support
|
||||
#
|
||||
# CONFIG_DS1682 is not set
|
||||
# CONFIG_SENSORS_TSL2550 is not set
|
||||
# CONFIG_I2C_DEBUG_CORE is not set
|
||||
# CONFIG_I2C_DEBUG_ALGO is not set
|
||||
|
|
@ -825,6 +886,8 @@ CONFIG_SPI_MASTER=y
|
|||
# CONFIG_SPI_BITBANG is not set
|
||||
# CONFIG_SPI_GPIO is not set
|
||||
CONFIG_SPI_OMAP24XX=y
|
||||
# CONFIG_SPI_XILINX is not set
|
||||
# CONFIG_SPI_DESIGNWARE is not set
|
||||
|
||||
#
|
||||
# SPI Protocol Masters
|
||||
|
|
@ -892,7 +955,7 @@ CONFIG_SSB_SDIOHOST_POSSIBLE=y
|
|||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_CORE is not set
|
||||
CONFIG_MFD_CORE=y
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
# CONFIG_MFD_ASIC3 is not set
|
||||
# CONFIG_HTC_EGPIO is not set
|
||||
|
|
@ -900,11 +963,13 @@ CONFIG_SSB_SDIOHOST_POSSIBLE=y
|
|||
# CONFIG_TPS65010 is not set
|
||||
CONFIG_TWL4030_CORE=y
|
||||
# CONFIG_TWL4030_POWER is not set
|
||||
CONFIG_TWL4030_CODEC=y
|
||||
# CONFIG_MFD_TMIO is not set
|
||||
# CONFIG_MFD_T7L66XB is not set
|
||||
# CONFIG_MFD_TC6387XB is not set
|
||||
# CONFIG_MFD_TC6393XB is not set
|
||||
# CONFIG_PMIC_DA903X is not set
|
||||
# CONFIG_PMIC_ADP5520 is not set
|
||||
# CONFIG_MFD_WM8400 is not set
|
||||
# CONFIG_MFD_WM831X is not set
|
||||
# CONFIG_MFD_WM8350_I2C is not set
|
||||
|
|
@ -912,6 +977,8 @@ CONFIG_TWL4030_CORE=y
|
|||
# CONFIG_MFD_MC13783 is not set
|
||||
# CONFIG_AB3100_CORE is not set
|
||||
# CONFIG_EZX_PCAP is not set
|
||||
# CONFIG_MFD_88PM8607 is not set
|
||||
# CONFIG_AB4500_CORE is not set
|
||||
CONFIG_REGULATOR=y
|
||||
# CONFIG_REGULATOR_DEBUG is not set
|
||||
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
|
||||
|
|
@ -919,6 +986,7 @@ CONFIG_REGULATOR=y
|
|||
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
|
||||
# CONFIG_REGULATOR_BQ24022 is not set
|
||||
# CONFIG_REGULATOR_MAX1586 is not set
|
||||
# CONFIG_REGULATOR_MAX8660 is not set
|
||||
CONFIG_REGULATOR_TWL4030=y
|
||||
# CONFIG_REGULATOR_LP3971 is not set
|
||||
# CONFIG_REGULATOR_TPS65023 is not set
|
||||
|
|
@ -930,65 +998,129 @@ CONFIG_REGULATOR_TWL4030=y
|
|||
#
|
||||
# CONFIG_VGASTATE is not set
|
||||
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
|
||||
# CONFIG_FB is not set
|
||||
CONFIG_FB=y
|
||||
# CONFIG_FIRMWARE_EDID is not set
|
||||
# CONFIG_FB_DDC is not set
|
||||
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
|
||||
CONFIG_FB_CFB_FILLRECT=y
|
||||
CONFIG_FB_CFB_COPYAREA=y
|
||||
CONFIG_FB_CFB_IMAGEBLIT=y
|
||||
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
|
||||
# CONFIG_FB_SYS_FILLRECT is not set
|
||||
# CONFIG_FB_SYS_COPYAREA is not set
|
||||
# CONFIG_FB_SYS_IMAGEBLIT is not set
|
||||
# CONFIG_FB_FOREIGN_ENDIAN is not set
|
||||
# CONFIG_FB_SYS_FOPS is not set
|
||||
# CONFIG_FB_SVGALIB is not set
|
||||
# CONFIG_FB_MACMODES is not set
|
||||
# CONFIG_FB_BACKLIGHT is not set
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
# CONFIG_FB_TILEBLITTING is not set
|
||||
|
||||
#
|
||||
# Frame buffer hardware drivers
|
||||
#
|
||||
# CONFIG_FB_UVESA is not set
|
||||
# CONFIG_FB_S1D13XXX is not set
|
||||
# CONFIG_FB_TMIO is not set
|
||||
# CONFIG_FB_VIRTUAL is not set
|
||||
# CONFIG_FB_METRONOME is not set
|
||||
# CONFIG_FB_MB862XX is not set
|
||||
# CONFIG_FB_BROADSHEET is not set
|
||||
# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
|
||||
CONFIG_OMAP2_VRAM=y
|
||||
CONFIG_OMAP2_VRFB=y
|
||||
CONFIG_OMAP2_DSS=y
|
||||
CONFIG_OMAP2_VRAM_SIZE=14
|
||||
# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set
|
||||
# CONFIG_OMAP2_DSS_RFBI is not set
|
||||
# CONFIG_OMAP2_DSS_VENC is not set
|
||||
# CONFIG_OMAP2_DSS_SDI is not set
|
||||
CONFIG_OMAP2_DSS_DSI=y
|
||||
CONFIG_OMAP2_DSS_USE_DSI_PLL=y
|
||||
# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
|
||||
CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
|
||||
CONFIG_FB_OMAP2=y
|
||||
# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set
|
||||
# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
|
||||
CONFIG_FB_OMAP2_NUM_FBS=3
|
||||
|
||||
#
|
||||
# OMAP2/3 Display Device Drivers
|
||||
#
|
||||
CONFIG_PANEL_GENERIC=y
|
||||
# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
|
||||
# CONFIG_PANEL_TAAL is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Display device support
|
||||
#
|
||||
# CONFIG_DISPLAY_SUPPORT is not set
|
||||
CONFIG_DISPLAY_SUPPORT=y
|
||||
|
||||
#
|
||||
# Display hardware drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Console display driver support
|
||||
#
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
# CONFIG_SOUND is not set
|
||||
CONFIG_HID_SUPPORT=y
|
||||
CONFIG_HID=y
|
||||
# CONFIG_HIDRAW is not set
|
||||
|
||||
#
|
||||
# USB Input Devices
|
||||
#
|
||||
CONFIG_USB_HID=y
|
||||
# CONFIG_HID_PID is not set
|
||||
# CONFIG_USB_HIDDEV is not set
|
||||
|
||||
#
|
||||
# Special HID drivers
|
||||
#
|
||||
# CONFIG_HID_A4TECH is not set
|
||||
# CONFIG_HID_APPLE is not set
|
||||
# CONFIG_HID_BELKIN is not set
|
||||
# CONFIG_HID_CHERRY is not set
|
||||
# CONFIG_HID_CHICONY is not set
|
||||
# CONFIG_HID_CYPRESS is not set
|
||||
# CONFIG_HID_DRAGONRISE is not set
|
||||
# CONFIG_HID_EZKEY is not set
|
||||
# CONFIG_HID_KYE is not set
|
||||
# CONFIG_HID_GYRATION is not set
|
||||
# CONFIG_HID_TWINHAN is not set
|
||||
# CONFIG_HID_KENSINGTON is not set
|
||||
# CONFIG_HID_LOGITECH is not set
|
||||
# CONFIG_HID_MICROSOFT is not set
|
||||
# CONFIG_HID_MONTEREY is not set
|
||||
# CONFIG_HID_NTRIG is not set
|
||||
# CONFIG_HID_PANTHERLORD is not set
|
||||
# CONFIG_HID_PETALYNX is not set
|
||||
# CONFIG_HID_SAMSUNG is not set
|
||||
# CONFIG_HID_SONY is not set
|
||||
# CONFIG_HID_SUNPLUS is not set
|
||||
# CONFIG_HID_GREENASIA is not set
|
||||
# CONFIG_HID_SMARTJOYPLUS is not set
|
||||
# CONFIG_HID_TOPSEED is not set
|
||||
# CONFIG_HID_THRUSTMASTER is not set
|
||||
# CONFIG_HID_WACOM is not set
|
||||
# CONFIG_HID_ZEROPLUS is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
|
||||
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
|
||||
# CONFIG_FONTS is not set
|
||||
CONFIG_FONT_8x8=y
|
||||
CONFIG_FONT_8x16=y
|
||||
CONFIG_LOGO=y
|
||||
# CONFIG_LOGO_LINUX_MONO is not set
|
||||
# CONFIG_LOGO_LINUX_VGA16 is not set
|
||||
CONFIG_LOGO_LINUX_CLUT224=y
|
||||
CONFIG_SOUND=y
|
||||
# CONFIG_SOUND_OSS_CORE is not set
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_TIMER=y
|
||||
CONFIG_SND_PCM=y
|
||||
CONFIG_SND_JACK=y
|
||||
# CONFIG_SND_SEQUENCER is not set
|
||||
# CONFIG_SND_MIXER_OSS is not set
|
||||
# CONFIG_SND_PCM_OSS is not set
|
||||
# CONFIG_SND_HRTIMER is not set
|
||||
# CONFIG_SND_DYNAMIC_MINORS is not set
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
# CONFIG_SND_VERBOSE_PROCFS is not set
|
||||
# CONFIG_SND_VERBOSE_PRINTK is not set
|
||||
# CONFIG_SND_DEBUG is not set
|
||||
# CONFIG_SND_RAWMIDI_SEQ is not set
|
||||
# CONFIG_SND_OPL3_LIB_SEQ is not set
|
||||
# CONFIG_SND_OPL4_LIB_SEQ is not set
|
||||
# CONFIG_SND_SBAWE_SEQ is not set
|
||||
# CONFIG_SND_EMU10K1_SEQ is not set
|
||||
CONFIG_SND_DRIVERS=y
|
||||
# CONFIG_SND_DUMMY is not set
|
||||
# CONFIG_SND_MTPAV is not set
|
||||
# CONFIG_SND_SERIAL_U16550 is not set
|
||||
# CONFIG_SND_MPU401 is not set
|
||||
CONFIG_SND_ARM=y
|
||||
CONFIG_SND_SPI=y
|
||||
CONFIG_SND_USB=y
|
||||
# CONFIG_SND_USB_AUDIO is not set
|
||||
# CONFIG_SND_USB_CAIAQ is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_OMAP_SOC=y
|
||||
CONFIG_SND_OMAP_SOC_MCBSP=y
|
||||
CONFIG_SND_OMAP_SOC_IGEP0020=y
|
||||
CONFIG_SND_SOC_I2C_AND_SPI=y
|
||||
# CONFIG_SND_SOC_ALL_CODECS is not set
|
||||
CONFIG_SND_SOC_TWL4030=y
|
||||
# CONFIG_SOUND_PRIME is not set
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
CONFIG_HID=m
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ARCH_HAS_HCD=y
|
||||
CONFIG_USB_ARCH_HAS_OHCI=y
|
||||
# CONFIG_USB_ARCH_HAS_EHCI is not set
|
||||
CONFIG_USB_ARCH_HAS_EHCI=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_USB_DEBUG is not set
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
|
|
@ -997,12 +1129,12 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
|||
# Miscellaneous USB options
|
||||
#
|
||||
# CONFIG_USB_DEVICEFS is not set
|
||||
# CONFIG_USB_DEVICE_CLASS is not set
|
||||
CONFIG_USB_DEVICE_CLASS=y
|
||||
# CONFIG_USB_DYNAMIC_MINORS is not set
|
||||
# CONFIG_USB_OTG is not set
|
||||
# CONFIG_USB_OTG_WHITELIST is not set
|
||||
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
|
||||
CONFIG_USB_MON=m
|
||||
# CONFIG_USB_MON is not set
|
||||
# CONFIG_USB_WUSB is not set
|
||||
# CONFIG_USB_WUSB_CBAF is not set
|
||||
|
||||
|
|
@ -1010,29 +1142,21 @@ CONFIG_USB_MON=m
|
|||
# USB Host Controller Drivers
|
||||
#
|
||||
# CONFIG_USB_C67X00_HCD is not set
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
# CONFIG_USB_OXU210HP_HCD is not set
|
||||
# CONFIG_USB_ISP116X_HCD is not set
|
||||
# CONFIG_USB_ISP1760_HCD is not set
|
||||
# CONFIG_USB_ISP1362_HCD is not set
|
||||
# CONFIG_USB_OHCI_HCD is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
|
||||
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
|
||||
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
|
||||
# CONFIG_USB_SL811_HCD is not set
|
||||
# CONFIG_USB_R8A66597_HCD is not set
|
||||
# CONFIG_USB_HWA_HCD is not set
|
||||
CONFIG_USB_MUSB_HDRC=y
|
||||
CONFIG_USB_MUSB_SOC=y
|
||||
|
||||
#
|
||||
# OMAP 343x high speed USB support
|
||||
#
|
||||
CONFIG_USB_MUSB_HOST=y
|
||||
# CONFIG_USB_MUSB_PERIPHERAL is not set
|
||||
# CONFIG_USB_MUSB_OTG is not set
|
||||
# CONFIG_USB_GADGET_MUSB_HDRC is not set
|
||||
CONFIG_USB_MUSB_HDRC_HCD=y
|
||||
# CONFIG_MUSB_PIO_ONLY is not set
|
||||
CONFIG_USB_INVENTRA_DMA=y
|
||||
# CONFIG_USB_TI_CPPI_DMA is not set
|
||||
# CONFIG_USB_MUSB_DEBUG is not set
|
||||
# CONFIG_USB_MUSB_HDRC is not set
|
||||
|
||||
#
|
||||
# USB Device Class drivers
|
||||
|
|
@ -1049,19 +1173,7 @@ CONFIG_USB_INVENTRA_DMA=y
|
|||
#
|
||||
# also be needed; see USB_STORAGE Help for more info
|
||||
#
|
||||
CONFIG_USB_STORAGE=m
|
||||
# CONFIG_USB_STORAGE_DEBUG is not set
|
||||
# CONFIG_USB_STORAGE_DATAFAB is not set
|
||||
# CONFIG_USB_STORAGE_FREECOM is not set
|
||||
# CONFIG_USB_STORAGE_ISD200 is not set
|
||||
# CONFIG_USB_STORAGE_USBAT is not set
|
||||
# CONFIG_USB_STORAGE_SDDR09 is not set
|
||||
# CONFIG_USB_STORAGE_SDDR55 is not set
|
||||
# CONFIG_USB_STORAGE_JUMPSHOT is not set
|
||||
# CONFIG_USB_STORAGE_ALAUDA is not set
|
||||
# CONFIG_USB_STORAGE_ONETOUCH is not set
|
||||
# CONFIG_USB_STORAGE_KARMA is not set
|
||||
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
|
||||
# CONFIG_USB_STORAGE is not set
|
||||
# CONFIG_USB_LIBUSUAL is not set
|
||||
|
||||
#
|
||||
|
|
@ -1099,41 +1211,7 @@ CONFIG_USB_STORAGE=m
|
|||
# CONFIG_USB_TEST is not set
|
||||
# CONFIG_USB_ISIGHTFW is not set
|
||||
# CONFIG_USB_VST is not set
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DEBUG=y
|
||||
CONFIG_USB_GADGET_DEBUG_FILES=y
|
||||
CONFIG_USB_GADGET_VBUS_DRAW=2
|
||||
CONFIG_USB_GADGET_SELECTED=y
|
||||
# CONFIG_USB_GADGET_AT91 is not set
|
||||
# CONFIG_USB_GADGET_ATMEL_USBA is not set
|
||||
# CONFIG_USB_GADGET_FSL_USB2 is not set
|
||||
# CONFIG_USB_GADGET_LH7A40X is not set
|
||||
CONFIG_USB_GADGET_OMAP=y
|
||||
CONFIG_USB_OMAP=y
|
||||
# CONFIG_USB_GADGET_PXA25X is not set
|
||||
# CONFIG_USB_GADGET_R8A66597 is not set
|
||||
# CONFIG_USB_GADGET_PXA27X is not set
|
||||
# CONFIG_USB_GADGET_S3C_HSOTG is not set
|
||||
# CONFIG_USB_GADGET_IMX is not set
|
||||
# CONFIG_USB_GADGET_S3C2410 is not set
|
||||
# CONFIG_USB_GADGET_M66592 is not set
|
||||
# CONFIG_USB_GADGET_AMD5536UDC is not set
|
||||
# CONFIG_USB_GADGET_FSL_QE is not set
|
||||
# CONFIG_USB_GADGET_CI13XXX is not set
|
||||
# CONFIG_USB_GADGET_NET2280 is not set
|
||||
# CONFIG_USB_GADGET_GOKU is not set
|
||||
# CONFIG_USB_GADGET_LANGWELL is not set
|
||||
# CONFIG_USB_GADGET_DUMMY_HCD is not set
|
||||
# CONFIG_USB_GADGET_DUALSPEED is not set
|
||||
CONFIG_USB_ZERO=m
|
||||
# CONFIG_USB_AUDIO is not set
|
||||
# CONFIG_USB_ETH is not set
|
||||
# CONFIG_USB_GADGETFS is not set
|
||||
# CONFIG_USB_FILE_STORAGE is not set
|
||||
# CONFIG_USB_G_SERIAL is not set
|
||||
# CONFIG_USB_MIDI_GADGET is not set
|
||||
# CONFIG_USB_G_PRINTER is not set
|
||||
# CONFIG_USB_CDC_COMPOSITE is not set
|
||||
# CONFIG_USB_GADGET is not set
|
||||
|
||||
#
|
||||
# OTG and related infrastructure
|
||||
|
|
@ -1141,10 +1219,11 @@ CONFIG_USB_ZERO=m
|
|||
CONFIG_USB_OTG_UTILS=y
|
||||
# CONFIG_USB_GPIO_VBUS is not set
|
||||
# CONFIG_ISP1301_OMAP is not set
|
||||
CONFIG_TWL4030_USB=y
|
||||
# CONFIG_USB_ULPI is not set
|
||||
# CONFIG_TWL4030_USB is not set
|
||||
# CONFIG_NOP_USB_XCEIV is not set
|
||||
CONFIG_MMC=y
|
||||
# CONFIG_MMC_DEBUG is not set
|
||||
CONFIG_MMC_DEBUG=y
|
||||
# CONFIG_MMC_UNSAFE_RESUME is not set
|
||||
|
||||
#
|
||||
|
|
@ -1158,7 +1237,8 @@ CONFIG_MMC_BLOCK_BOUNCE=y
|
|||
#
|
||||
# MMC/SD/SDIO Host Controller Drivers
|
||||
#
|
||||
# CONFIG_MMC_SDHCI is not set
|
||||
CONFIG_MMC_SDHCI=y
|
||||
# CONFIG_MMC_SDHCI_PLTFM is not set
|
||||
# CONFIG_MMC_OMAP is not set
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
# CONFIG_MMC_AT91 is not set
|
||||
|
|
@ -1178,6 +1258,11 @@ CONFIG_RTC_LIB=y
|
|||
#
|
||||
# CONFIG_STAGING is not set
|
||||
|
||||
#
|
||||
# CBUS support
|
||||
#
|
||||
# CONFIG_CBUS is not set
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
|
|
@ -1253,6 +1338,7 @@ CONFIG_MISC_FILESYSTEMS=y
|
|||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
# CONFIG_JFFS2_FS is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_SQUASHFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
|
|
@ -1401,6 +1487,7 @@ CONFIG_DEBUG_INFO=y
|
|||
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
|
||||
# CONFIG_FAULT_INJECTION is not set
|
||||
# CONFIG_LATENCYTOP is not set
|
||||
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
|
||||
# CONFIG_PAGE_POISONING is not set
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_TRACING_SUPPORT=y
|
||||
|
|
@ -1425,7 +1512,9 @@ CONFIG_ARM_UNWIND=y
|
|||
# CONFIG_DEBUG_ERRORS is not set
|
||||
# CONFIG_DEBUG_STACK_USAGE is not set
|
||||
CONFIG_DEBUG_LL=y
|
||||
# CONFIG_EARLY_PRINTK is not set
|
||||
# CONFIG_DEBUG_ICEDCC is not set
|
||||
# CONFIG_OC_ETM is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
|
|
@ -1433,7 +1522,11 @@ CONFIG_DEBUG_LL=y
|
|||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
# CONFIG_SECURITYFS is not set
|
||||
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
|
||||
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
|
||||
# CONFIG_DEFAULT_SECURITY_SMACK is not set
|
||||
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
|
||||
CONFIG_DEFAULT_SECURITY_DAC=y
|
||||
CONFIG_DEFAULT_SECURITY=""
|
||||
CONFIG_CRYPTO=y
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.32-rc8
|
||||
# Tue Dec 1 14:04:02 2009
|
||||
# Linux kernel version: 2.6.33-rc5
|
||||
# Tue Jan 26 11:05:31 2010
|
||||
#
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
|
|
@ -20,6 +20,8 @@ CONFIG_ARCH_HAS_CPUFREQ=y
|
|||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
|
||||
CONFIG_OPROFILE_ARMV6=y
|
||||
CONFIG_OPROFILE_ARM11_CORE=y
|
||||
CONFIG_OPROFILE_ARMV7=y
|
||||
CONFIG_VECTORS_BASE=0xffff0000
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
|
|
@ -33,6 +35,12 @@ CONFIG_BROKEN_ON_SMP=y
|
|||
CONFIG_INIT_ENV_ARG_LIMIT=32
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_HAVE_KERNEL_GZIP=y
|
||||
CONFIG_HAVE_KERNEL_LZO=y
|
||||
CONFIG_KERNEL_GZIP=y
|
||||
# CONFIG_KERNEL_BZIP2 is not set
|
||||
# CONFIG_KERNEL_LZMA is not set
|
||||
# CONFIG_KERNEL_LZO is not set
|
||||
CONFIG_SWAP=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_SYSVIPC_SYSCTL=y
|
||||
|
|
@ -48,6 +56,7 @@ CONFIG_BSD_PROCESS_ACCT=y
|
|||
#
|
||||
CONFIG_TREE_RCU=y
|
||||
# CONFIG_TREE_PREEMPT_RCU is not set
|
||||
# CONFIG_TINY_RCU is not set
|
||||
# CONFIG_RCU_TRACE is not set
|
||||
CONFIG_RCU_FANOUT=32
|
||||
# CONFIG_RCU_FANOUT_EXACT is not set
|
||||
|
|
@ -69,6 +78,7 @@ CONFIG_INITRAMFS_SOURCE=""
|
|||
CONFIG_RD_GZIP=y
|
||||
# CONFIG_RD_BZIP2 is not set
|
||||
# CONFIG_RD_LZMA is not set
|
||||
# CONFIG_RD_LZO is not set
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_ANON_INODES=y
|
||||
|
|
@ -133,14 +143,41 @@ CONFIG_LBDAF=y
|
|||
# IO Schedulers
|
||||
#
|
||||
CONFIG_IOSCHED_NOOP=y
|
||||
CONFIG_IOSCHED_AS=y
|
||||
CONFIG_IOSCHED_DEADLINE=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
# CONFIG_DEFAULT_AS is not set
|
||||
# CONFIG_DEFAULT_DEADLINE is not set
|
||||
CONFIG_DEFAULT_CFQ=y
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="cfq"
|
||||
# CONFIG_INLINE_SPIN_TRYLOCK is not set
|
||||
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
|
||||
# CONFIG_INLINE_SPIN_LOCK is not set
|
||||
# CONFIG_INLINE_SPIN_LOCK_BH is not set
|
||||
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
|
||||
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
|
||||
# CONFIG_INLINE_SPIN_UNLOCK is not set
|
||||
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
|
||||
# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
|
||||
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
|
||||
# CONFIG_INLINE_READ_TRYLOCK is not set
|
||||
# CONFIG_INLINE_READ_LOCK is not set
|
||||
# CONFIG_INLINE_READ_LOCK_BH is not set
|
||||
# CONFIG_INLINE_READ_LOCK_IRQ is not set
|
||||
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
|
||||
# CONFIG_INLINE_READ_UNLOCK is not set
|
||||
# CONFIG_INLINE_READ_UNLOCK_BH is not set
|
||||
# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
|
||||
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
|
||||
# CONFIG_INLINE_WRITE_TRYLOCK is not set
|
||||
# CONFIG_INLINE_WRITE_LOCK is not set
|
||||
# CONFIG_INLINE_WRITE_LOCK_BH is not set
|
||||
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
|
||||
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
|
||||
# CONFIG_INLINE_WRITE_UNLOCK is not set
|
||||
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
|
||||
# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
|
||||
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
|
||||
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
|
||||
CONFIG_FREEZER=y
|
||||
|
||||
#
|
||||
|
|
@ -169,6 +206,7 @@ CONFIG_MMU=y
|
|||
# CONFIG_ARCH_IXP2000 is not set
|
||||
# CONFIG_ARCH_IXP4XX is not set
|
||||
# CONFIG_ARCH_L7200 is not set
|
||||
# CONFIG_ARCH_DOVE is not set
|
||||
# CONFIG_ARCH_KIRKWOOD is not set
|
||||
# CONFIG_ARCH_LOKI is not set
|
||||
# CONFIG_ARCH_MV78XX0 is not set
|
||||
|
|
@ -191,21 +229,23 @@ CONFIG_MMU=y
|
|||
# CONFIG_ARCH_DAVINCI is not set
|
||||
CONFIG_ARCH_OMAP=y
|
||||
# CONFIG_ARCH_BCMRING is not set
|
||||
# CONFIG_ARCH_U8500 is not set
|
||||
|
||||
#
|
||||
# TI OMAP Implementations
|
||||
#
|
||||
CONFIG_ARCH_OMAP_OTG=y
|
||||
# CONFIG_ARCH_OMAP1 is not set
|
||||
# CONFIG_ARCH_OMAP2 is not set
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_ARCH_OMAP2=y
|
||||
CONFIG_ARCH_OMAP3=y
|
||||
# CONFIG_ARCH_OMAP4 is not set
|
||||
CONFIG_ARCH_OMAP4=y
|
||||
|
||||
#
|
||||
# OMAP Feature Selections
|
||||
#
|
||||
# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
|
||||
# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
|
||||
CONFIG_OMAP_DEBUG_DEVICES=y
|
||||
CONFIG_OMAP_DEBUG_LEDS=y
|
||||
CONFIG_OMAP_RESET_CLOCKS=y
|
||||
CONFIG_OMAP_MUX=y
|
||||
CONFIG_OMAP_MUX_DEBUG=y
|
||||
|
|
@ -216,43 +256,66 @@ CONFIG_OMAP_MCBSP=y
|
|||
CONFIG_OMAP_32K_TIMER=y
|
||||
CONFIG_OMAP_32K_TIMER_HZ=128
|
||||
CONFIG_OMAP_DM_TIMER=y
|
||||
# CONFIG_OMAP_LL_DEBUG_UART1 is not set
|
||||
# CONFIG_OMAP_LL_DEBUG_UART2 is not set
|
||||
# CONFIG_OMAP_LL_DEBUG_UART3 is not set
|
||||
CONFIG_OMAP_LL_DEBUG_NONE=y
|
||||
# CONFIG_OMAP_PM_NONE is not set
|
||||
CONFIG_OMAP_PM_NOOP=y
|
||||
CONFIG_ARCH_OMAP34XX=y
|
||||
CONFIG_MACH_OMAP_GENERIC=y
|
||||
|
||||
#
|
||||
# OMAP Core Type
|
||||
#
|
||||
CONFIG_ARCH_OMAP2420=y
|
||||
# CONFIG_ARCH_OMAP2430 is not set
|
||||
CONFIG_ARCH_OMAP3430=y
|
||||
CONFIG_OMAP_PACKAGE_CBB=y
|
||||
CONFIG_OMAP_PACKAGE_CUS=y
|
||||
CONFIG_OMAP_PACKAGE_CBP=y
|
||||
|
||||
#
|
||||
# OMAP Board Type
|
||||
#
|
||||
CONFIG_MACH_OMAP2_TUSB6010=y
|
||||
CONFIG_MACH_OMAP_H4=y
|
||||
CONFIG_MACH_OMAP_APOLLON=y
|
||||
# CONFIG_MACH_OMAP_2430SDP is not set
|
||||
CONFIG_MACH_OMAP3_BEAGLE=y
|
||||
CONFIG_MACH_OMAP_LDP=y
|
||||
CONFIG_MACH_OVERO=y
|
||||
CONFIG_MACH_OMAP3EVM=y
|
||||
CONFIG_MACH_OMAP3517EVM=y
|
||||
CONFIG_MACH_OMAP3_PANDORA=y
|
||||
CONFIG_MACH_OMAP3_TOUCHBOOK=y
|
||||
CONFIG_MACH_OMAP_3430SDP=y
|
||||
CONFIG_MACH_NOKIA_N800=y
|
||||
CONFIG_MACH_NOKIA_N810=y
|
||||
CONFIG_MACH_NOKIA_N810_WIMAX=y
|
||||
CONFIG_MACH_NOKIA_N8X0=y
|
||||
CONFIG_MACH_NOKIA_RX51=y
|
||||
CONFIG_MACH_OMAP_ZOOM2=y
|
||||
CONFIG_MACH_OMAP_ZOOM3=y
|
||||
CONFIG_MACH_CM_T35=y
|
||||
CONFIG_MACH_IGEP0020=y
|
||||
CONFIG_MACH_OMAP_3630SDP=y
|
||||
CONFIG_MACH_OMAP_4430SDP=y
|
||||
# CONFIG_OMAP3_EMU is not set
|
||||
# CONFIG_OMAP3_SDRC_AC_TIMING is not set
|
||||
|
||||
#
|
||||
# Processor Type
|
||||
#
|
||||
CONFIG_CPU_32v6K=y
|
||||
CONFIG_CPU_V6=y
|
||||
# CONFIG_CPU_32v6K is not set
|
||||
CONFIG_CPU_V7=y
|
||||
CONFIG_CPU_32v6=y
|
||||
CONFIG_CPU_32v7=y
|
||||
CONFIG_CPU_ABRT_EV6=y
|
||||
CONFIG_CPU_ABRT_EV7=y
|
||||
CONFIG_CPU_PABRT_V6=y
|
||||
CONFIG_CPU_PABRT_V7=y
|
||||
CONFIG_CPU_CACHE_V6=y
|
||||
CONFIG_CPU_CACHE_V7=y
|
||||
CONFIG_CPU_CACHE_VIPT=y
|
||||
CONFIG_CPU_COPY_V6=y
|
||||
CONFIG_CPU_TLB_V6=y
|
||||
CONFIG_CPU_TLB_V7=y
|
||||
CONFIG_CPU_HAS_ASID=y
|
||||
CONFIG_CPU_CP15=y
|
||||
|
|
@ -268,9 +331,11 @@ CONFIG_ARM_THUMBEE=y
|
|||
# CONFIG_CPU_BPREDICT_DISABLE is not set
|
||||
CONFIG_HAS_TLS_REG=y
|
||||
CONFIG_ARM_L1_CACHE_SHIFT=6
|
||||
# CONFIG_ARM_ERRATA_411920 is not set
|
||||
# CONFIG_ARM_ERRATA_430973 is not set
|
||||
# CONFIG_ARM_ERRATA_458693 is not set
|
||||
# CONFIG_ARM_ERRATA_460075 is not set
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_COMMON_CLKDEV=y
|
||||
|
||||
#
|
||||
|
|
@ -287,6 +352,7 @@ CONFIG_TICK_ONESHOT=y
|
|||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
|
||||
# CONFIG_SMP is not set
|
||||
CONFIG_VMSPLIT_3G=y
|
||||
# CONFIG_VMSPLIT_2G is not set
|
||||
# CONFIG_VMSPLIT_1G is not set
|
||||
|
|
@ -298,6 +364,7 @@ CONFIG_HZ=128
|
|||
# CONFIG_THUMB2_KERNEL is not set
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_OABI_COMPAT=y
|
||||
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
|
||||
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
|
||||
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
|
||||
# CONFIG_HIGHMEM is not set
|
||||
|
|
@ -308,12 +375,10 @@ CONFIG_FLATMEM_MANUAL=y
|
|||
CONFIG_FLATMEM=y
|
||||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
CONFIG_PAGEFLAGS_EXTENDED=y
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=999999
|
||||
# CONFIG_PHYS_ADDR_T_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
CONFIG_VIRT_TO_BUS=y
|
||||
CONFIG_HAVE_MLOCK=y
|
||||
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
|
||||
# CONFIG_KSM is not set
|
||||
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
|
||||
CONFIG_LEDS=y
|
||||
|
|
@ -509,15 +574,18 @@ CONFIG_BT_HCIBPA10X=y
|
|||
# CONFIG_BT_MRVL is not set
|
||||
# CONFIG_AF_RXRPC is not set
|
||||
CONFIG_WIRELESS=y
|
||||
CONFIG_WIRELESS_EXT=y
|
||||
CONFIG_WEXT_CORE=y
|
||||
CONFIG_WEXT_PROC=y
|
||||
CONFIG_WEXT_SPY=y
|
||||
CONFIG_CFG80211=y
|
||||
# CONFIG_NL80211_TESTMODE is not set
|
||||
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
|
||||
# CONFIG_CFG80211_REG_DEBUG is not set
|
||||
CONFIG_CFG80211_DEFAULT_PS=y
|
||||
CONFIG_CFG80211_DEFAULT_PS_VALUE=1
|
||||
# CONFIG_CFG80211_DEBUGFS is not set
|
||||
CONFIG_WIRELESS_OLD_REGULATORY=y
|
||||
CONFIG_WIRELESS_EXT=y
|
||||
CONFIG_CFG80211_WEXT=y
|
||||
CONFIG_WIRELESS_EXT_SYSFS=y
|
||||
CONFIG_LIB80211=y
|
||||
# CONFIG_LIB80211_DEBUG is not set
|
||||
|
|
@ -671,6 +739,7 @@ CONFIG_BLK_DEV=y
|
|||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
|
||||
# CONFIG_BLK_DEV_DRBD is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_UB is not set
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
|
|
@ -681,9 +750,12 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
|
|||
# CONFIG_ATA_OVER_ETH is not set
|
||||
# CONFIG_MG_DISK is not set
|
||||
CONFIG_MISC_DEVICES=y
|
||||
# CONFIG_AD525X_DPOT is not set
|
||||
# CONFIG_ICS932S401 is not set
|
||||
# CONFIG_ENCLOSURE_SERVICES is not set
|
||||
# CONFIG_ISL29003 is not set
|
||||
# CONFIG_DS1682 is not set
|
||||
# CONFIG_TI_DAC7512 is not set
|
||||
# CONFIG_C2PORT is not set
|
||||
|
||||
#
|
||||
|
|
@ -694,6 +766,7 @@ CONFIG_MISC_DEVICES=y
|
|||
CONFIG_EEPROM_LEGACY=y
|
||||
# CONFIG_EEPROM_MAX6875 is not set
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
# CONFIG_IWMC3200TOP is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
|
|
@ -792,28 +865,26 @@ CONFIG_SMSC911X=y
|
|||
CONFIG_NETDEV_1000=y
|
||||
CONFIG_NETDEV_10000=y
|
||||
CONFIG_WLAN=y
|
||||
# CONFIG_WLAN_PRE80211 is not set
|
||||
CONFIG_WLAN_80211=y
|
||||
CONFIG_LIBERTAS=y
|
||||
CONFIG_LIBERTAS_USB=y
|
||||
CONFIG_LIBERTAS_SDIO=y
|
||||
# CONFIG_LIBERTAS_SPI is not set
|
||||
CONFIG_LIBERTAS_DEBUG=y
|
||||
# CONFIG_LIBERTAS_THINFIRM is not set
|
||||
# CONFIG_AT76C50X_USB is not set
|
||||
# CONFIG_USB_ZD1201 is not set
|
||||
# CONFIG_USB_NET_RNDIS_WLAN is not set
|
||||
# CONFIG_RTL8187 is not set
|
||||
# CONFIG_MAC80211_HWSIM is not set
|
||||
# CONFIG_P54_COMMON is not set
|
||||
# CONFIG_ATH_COMMON is not set
|
||||
# CONFIG_HOSTAP is not set
|
||||
# CONFIG_B43 is not set
|
||||
# CONFIG_B43LEGACY is not set
|
||||
# CONFIG_ZD1211RW is not set
|
||||
# CONFIG_HOSTAP is not set
|
||||
# CONFIG_IWM is not set
|
||||
CONFIG_LIBERTAS=y
|
||||
CONFIG_LIBERTAS_USB=y
|
||||
CONFIG_LIBERTAS_SDIO=y
|
||||
# CONFIG_LIBERTAS_SPI is not set
|
||||
CONFIG_LIBERTAS_DEBUG=y
|
||||
# CONFIG_P54_COMMON is not set
|
||||
# CONFIG_RT2X00 is not set
|
||||
# CONFIG_WL12XX is not set
|
||||
# CONFIG_IWM is not set
|
||||
# CONFIG_ZD1211RW is not set
|
||||
|
||||
#
|
||||
# Enable WiMAX (Networking options) to see the WiMAX drivers
|
||||
|
|
@ -861,6 +932,7 @@ CONFIG_USB_NET_ZAURUS=y
|
|||
CONFIG_INPUT=y
|
||||
# CONFIG_INPUT_FF_MEMLESS is not set
|
||||
# CONFIG_INPUT_POLLDEV is not set
|
||||
# CONFIG_INPUT_SPARSEKMAP is not set
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
|
|
@ -889,6 +961,7 @@ CONFIG_KEYBOARD_GPIO=y
|
|||
# CONFIG_KEYBOARD_OPENCORES is not set
|
||||
# CONFIG_KEYBOARD_STOWAWAY is not set
|
||||
# CONFIG_KEYBOARD_SUNKBD is not set
|
||||
# CONFIG_KEYBOARD_OMAP is not set
|
||||
CONFIG_KEYBOARD_TWL4030=y
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
|
|
@ -914,6 +987,7 @@ CONFIG_TOUCHSCREEN_ADS7846=y
|
|||
# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
|
||||
# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
|
||||
# CONFIG_TOUCHSCREEN_AD7879 is not set
|
||||
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
|
||||
# CONFIG_TOUCHSCREEN_EETI is not set
|
||||
# CONFIG_TOUCHSCREEN_FUJITSU is not set
|
||||
# CONFIG_TOUCHSCREEN_GUNZE is not set
|
||||
|
|
@ -948,6 +1022,7 @@ CONFIG_SERIO=y
|
|||
CONFIG_SERIO_SERPORT=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_SERIO_RAW is not set
|
||||
# CONFIG_SERIO_ALTERA_PS2 is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
|
|
@ -986,6 +1061,7 @@ CONFIG_UNIX98_PTYS=y
|
|||
# CONFIG_IPMI_HANDLER is not set
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
|
||||
CONFIG_HW_RANDOM_OMAP=y
|
||||
# CONFIG_R3964 is not set
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
# CONFIG_TCG_TPM is not set
|
||||
|
|
@ -1024,7 +1100,6 @@ CONFIG_I2C_OMAP=y
|
|||
#
|
||||
# Miscellaneous I2C Chip support
|
||||
#
|
||||
# CONFIG_DS1682 is not set
|
||||
# CONFIG_SENSORS_TSL2550 is not set
|
||||
# CONFIG_I2C_DEBUG_CORE is not set
|
||||
# CONFIG_I2C_DEBUG_ALGO is not set
|
||||
|
|
@ -1040,6 +1115,8 @@ CONFIG_SPI_MASTER=y
|
|||
# CONFIG_SPI_BITBANG is not set
|
||||
# CONFIG_SPI_GPIO is not set
|
||||
CONFIG_SPI_OMAP24XX=y
|
||||
# CONFIG_SPI_XILINX is not set
|
||||
# CONFIG_SPI_DESIGNWARE is not set
|
||||
|
||||
#
|
||||
# SPI Protocol Masters
|
||||
|
|
@ -1067,6 +1144,7 @@ CONFIG_GPIO_SYSFS=y
|
|||
# CONFIG_GPIO_PCA953X is not set
|
||||
# CONFIG_GPIO_PCF857X is not set
|
||||
CONFIG_GPIO_TWL4030=y
|
||||
# CONFIG_GPIO_ADP5588 is not set
|
||||
|
||||
#
|
||||
# PCI GPIO expanders:
|
||||
|
|
@ -1141,6 +1219,7 @@ CONFIG_HWMON=y
|
|||
# CONFIG_SENSORS_IT87 is not set
|
||||
# CONFIG_SENSORS_LM63 is not set
|
||||
# CONFIG_SENSORS_LM70 is not set
|
||||
# CONFIG_SENSORS_LM73 is not set
|
||||
# CONFIG_SENSORS_LM75 is not set
|
||||
# CONFIG_SENSORS_LM77 is not set
|
||||
# CONFIG_SENSORS_LM78 is not set
|
||||
|
|
@ -1166,6 +1245,7 @@ CONFIG_HWMON=y
|
|||
# CONFIG_SENSORS_SMSC47M192 is not set
|
||||
# CONFIG_SENSORS_SMSC47B397 is not set
|
||||
# CONFIG_SENSORS_ADS7828 is not set
|
||||
# CONFIG_SENSORS_AMC6821 is not set
|
||||
# CONFIG_SENSORS_THMC50 is not set
|
||||
# CONFIG_SENSORS_TMP401 is not set
|
||||
# CONFIG_SENSORS_TMP421 is not set
|
||||
|
|
@ -1179,6 +1259,7 @@ CONFIG_HWMON=y
|
|||
# CONFIG_SENSORS_W83627HF is not set
|
||||
# CONFIG_SENSORS_W83627EHF is not set
|
||||
# CONFIG_SENSORS_LIS3_SPI is not set
|
||||
# CONFIG_SENSORS_LIS3_I2C is not set
|
||||
# CONFIG_THERMAL is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_WATCHDOG_NOWAYOUT=y
|
||||
|
|
@ -1204,20 +1285,22 @@ CONFIG_SSB_POSSIBLE=y
|
|||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_CORE is not set
|
||||
CONFIG_MFD_CORE=y
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
# CONFIG_MFD_ASIC3 is not set
|
||||
# CONFIG_HTC_EGPIO is not set
|
||||
# CONFIG_HTC_PASIC3 is not set
|
||||
# CONFIG_TPS65010 is not set
|
||||
# CONFIG_MENELAUS is not set
|
||||
CONFIG_TWL4030_CORE=y
|
||||
# CONFIG_TWL4030_POWER is not set
|
||||
# CONFIG_TWL4030_CODEC is not set
|
||||
CONFIG_TWL4030_CODEC=y
|
||||
# CONFIG_MFD_TMIO is not set
|
||||
# CONFIG_MFD_T7L66XB is not set
|
||||
# CONFIG_MFD_TC6387XB is not set
|
||||
# CONFIG_MFD_TC6393XB is not set
|
||||
# CONFIG_PMIC_DA903X is not set
|
||||
# CONFIG_PMIC_ADP5520 is not set
|
||||
# CONFIG_MFD_WM8400 is not set
|
||||
# CONFIG_MFD_WM831X is not set
|
||||
# CONFIG_MFD_WM8350_I2C is not set
|
||||
|
|
@ -1225,6 +1308,8 @@ CONFIG_TWL4030_CORE=y
|
|||
# CONFIG_MFD_MC13783 is not set
|
||||
# CONFIG_AB3100_CORE is not set
|
||||
# CONFIG_EZX_PCAP is not set
|
||||
# CONFIG_MFD_88PM8607 is not set
|
||||
# CONFIG_AB4500_CORE is not set
|
||||
CONFIG_REGULATOR=y
|
||||
# CONFIG_REGULATOR_DEBUG is not set
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
|
|
@ -1232,6 +1317,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
|||
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
|
||||
# CONFIG_REGULATOR_BQ24022 is not set
|
||||
# CONFIG_REGULATOR_MAX1586 is not set
|
||||
# CONFIG_REGULATOR_MAX8660 is not set
|
||||
CONFIG_REGULATOR_TWL4030=y
|
||||
# CONFIG_REGULATOR_LP3971 is not set
|
||||
# CONFIG_REGULATOR_TPS65023 is not set
|
||||
|
|
@ -1267,6 +1353,7 @@ CONFIG_FB_TILEBLITTING=y
|
|||
#
|
||||
# CONFIG_FB_UVESA is not set
|
||||
# CONFIG_FB_S1D13XXX is not set
|
||||
# CONFIG_FB_TMIO is not set
|
||||
# CONFIG_FB_VIRTUAL is not set
|
||||
# CONFIG_FB_METRONOME is not set
|
||||
# CONFIG_FB_MB862XX is not set
|
||||
|
|
@ -1281,6 +1368,7 @@ CONFIG_FB_OMAP_079M3R=y
|
|||
# CONFIG_FB_OMAP_LCD_MIPID is not set
|
||||
# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
|
||||
CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
|
||||
# CONFIG_OMAP2_DSS is not set
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
# CONFIG_LCD_LMS283GF05 is not set
|
||||
|
|
@ -1364,12 +1452,15 @@ CONFIG_SND_USB_AUDIO=y
|
|||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_OMAP_SOC=y
|
||||
CONFIG_SND_OMAP_SOC_MCBSP=y
|
||||
# CONFIG_SND_OMAP_SOC_N810 is not set
|
||||
# CONFIG_SND_OMAP_SOC_OVERO is not set
|
||||
# CONFIG_SND_OMAP_SOC_OMAP3EVM is not set
|
||||
# CONFIG_SND_OMAP_SOC_AM3517EVM is not set
|
||||
# CONFIG_SND_OMAP_SOC_SDP3430 is not set
|
||||
CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y
|
||||
# CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE is not set
|
||||
# CONFIG_SND_OMAP_SOC_ZOOM2 is not set
|
||||
# CONFIG_SND_OMAP_SOC_IGEP0020 is not set
|
||||
CONFIG_SND_SOC_I2C_AND_SPI=y
|
||||
# CONFIG_SND_SOC_ALL_CODECS is not set
|
||||
CONFIG_SND_SOC_TWL4030=y
|
||||
|
|
@ -1418,7 +1509,7 @@ CONFIG_USB_HID=y
|
|||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ARCH_HAS_HCD=y
|
||||
CONFIG_USB_ARCH_HAS_OHCI=y
|
||||
# CONFIG_USB_ARCH_HAS_EHCI is not set
|
||||
CONFIG_USB_ARCH_HAS_EHCI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_DEBUG=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
|
|
@ -1441,6 +1532,7 @@ CONFIG_USB_MON=y
|
|||
# USB Host Controller Drivers
|
||||
#
|
||||
# CONFIG_USB_C67X00_HCD is not set
|
||||
# CONFIG_USB_EHCI_HCD is not set
|
||||
# CONFIG_USB_OXU210HP_HCD is not set
|
||||
# CONFIG_USB_ISP116X_HCD is not set
|
||||
# CONFIG_USB_ISP1760_HCD is not set
|
||||
|
|
@ -1556,16 +1648,18 @@ CONFIG_USB_GADGET_SELECTED=y
|
|||
# CONFIG_USB_GADGET_LANGWELL is not set
|
||||
# CONFIG_USB_GADGET_DUMMY_HCD is not set
|
||||
CONFIG_USB_GADGET_DUALSPEED=y
|
||||
CONFIG_USB_ZERO=y
|
||||
CONFIG_USB_ZERO=m
|
||||
# CONFIG_USB_ZERO_HNPTEST is not set
|
||||
# CONFIG_USB_AUDIO is not set
|
||||
# CONFIG_USB_ETH is not set
|
||||
# CONFIG_USB_GADGETFS is not set
|
||||
# CONFIG_USB_FILE_STORAGE is not set
|
||||
# CONFIG_USB_MASS_STORAGE is not set
|
||||
# CONFIG_USB_G_SERIAL is not set
|
||||
# CONFIG_USB_MIDI_GADGET is not set
|
||||
# CONFIG_USB_G_PRINTER is not set
|
||||
# CONFIG_USB_CDC_COMPOSITE is not set
|
||||
# CONFIG_USB_G_MULTI is not set
|
||||
|
||||
#
|
||||
# OTG and related infrastructure
|
||||
|
|
@ -1573,6 +1667,7 @@ CONFIG_USB_ZERO=y
|
|||
CONFIG_USB_OTG_UTILS=y
|
||||
# CONFIG_USB_GPIO_VBUS is not set
|
||||
# CONFIG_ISP1301_OMAP is not set
|
||||
# CONFIG_USB_ULPI is not set
|
||||
CONFIG_TWL4030_USB=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_MMC=y
|
||||
|
|
@ -1609,7 +1704,9 @@ CONFIG_LEDS_GPIO_PLATFORM=y
|
|||
# CONFIG_LEDS_LP3944 is not set
|
||||
# CONFIG_LEDS_PCA955X is not set
|
||||
# CONFIG_LEDS_DAC124S085 is not set
|
||||
# CONFIG_LEDS_REGULATOR is not set
|
||||
# CONFIG_LEDS_BD2802 is not set
|
||||
# CONFIG_LEDS_LT3593 is not set
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
|
|
@ -1653,6 +1750,7 @@ CONFIG_RTC_INTF_DEV=y
|
|||
# CONFIG_RTC_DRV_PCF8563 is not set
|
||||
# CONFIG_RTC_DRV_PCF8583 is not set
|
||||
# CONFIG_RTC_DRV_M41T80 is not set
|
||||
# CONFIG_RTC_DRV_BQ32K is not set
|
||||
CONFIG_RTC_DRV_TWL4030=y
|
||||
# CONFIG_RTC_DRV_S35390A is not set
|
||||
# CONFIG_RTC_DRV_FM3130 is not set
|
||||
|
|
@ -1683,7 +1781,9 @@ CONFIG_RTC_DRV_TWL4030=y
|
|||
# CONFIG_RTC_DRV_M48T86 is not set
|
||||
# CONFIG_RTC_DRV_M48T35 is not set
|
||||
# CONFIG_RTC_DRV_M48T59 is not set
|
||||
# CONFIG_RTC_DRV_MSM6242 is not set
|
||||
# CONFIG_RTC_DRV_BQ4802 is not set
|
||||
# CONFIG_RTC_DRV_RP5C01 is not set
|
||||
# CONFIG_RTC_DRV_V3020 is not set
|
||||
|
||||
#
|
||||
|
|
@ -1951,6 +2051,7 @@ CONFIG_DEBUG_INFO=y
|
|||
# CONFIG_LKDTM is not set
|
||||
# CONFIG_FAULT_INJECTION is not set
|
||||
# CONFIG_LATENCYTOP is not set
|
||||
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
|
||||
# CONFIG_PAGE_POISONING is not set
|
||||
CONFIG_NOP_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
|
|
@ -1983,7 +2084,9 @@ CONFIG_ARM_UNWIND=y
|
|||
# CONFIG_DEBUG_ERRORS is not set
|
||||
# CONFIG_DEBUG_STACK_USAGE is not set
|
||||
CONFIG_DEBUG_LL=y
|
||||
# CONFIG_EARLY_PRINTK is not set
|
||||
# CONFIG_DEBUG_ICEDCC is not set
|
||||
# CONFIG_OC_ETM is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
|
|
@ -1993,9 +2096,12 @@ CONFIG_SECURITY=y
|
|||
# CONFIG_SECURITYFS is not set
|
||||
# CONFIG_SECURITY_NETWORK is not set
|
||||
# CONFIG_SECURITY_PATH is not set
|
||||
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
|
||||
# CONFIG_SECURITY_ROOTPLUG is not set
|
||||
# CONFIG_SECURITY_TOMOYO is not set
|
||||
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
|
||||
# CONFIG_DEFAULT_SECURITY_SMACK is not set
|
||||
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
|
||||
CONFIG_DEFAULT_SECURITY_DAC=y
|
||||
CONFIG_DEFAULT_SECURITY=""
|
||||
CONFIG_CRYPTO=y
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -187,6 +187,8 @@ CONFIG_ARCH_OMAP3=y
|
|||
#
|
||||
# OMAP Feature Selections
|
||||
#
|
||||
CONFIG_OMAP_SMARTREFLEX=y
|
||||
# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
|
||||
# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
|
||||
# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
|
||||
CONFIG_OMAP_RESET_CLOCKS=y
|
||||
|
|
@ -333,7 +335,7 @@ CONFIG_BINFMT_MISC=y
|
|||
# Power management options
|
||||
#
|
||||
CONFIG_PM=y
|
||||
# CONFIG_PM_DEBUG is not set
|
||||
CONFIG_PM_DEBUG=y
|
||||
CONFIG_PM_SLEEP=y
|
||||
CONFIG_SUSPEND=y
|
||||
CONFIG_SUSPEND_FREEZER=y
|
||||
|
|
@ -1339,7 +1341,7 @@ CONFIG_ENABLE_MUST_CHECK=y
|
|||
CONFIG_FRAME_WARN=1024
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
# CONFIG_DEBUG_SHIRQ is not set
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -199,7 +199,7 @@ CONFIG_ARCH_OMAP4=y
|
|||
#
|
||||
# CONFIG_OMAP_RESET_CLOCKS is not set
|
||||
# CONFIG_OMAP_MUX is not set
|
||||
# CONFIG_OMAP_MCBSP is not set
|
||||
CONFIG_OMAP_MCBSP=y
|
||||
# CONFIG_OMAP_MBOX_FWK is not set
|
||||
# CONFIG_OMAP_MPU_TIMER is not set
|
||||
CONFIG_OMAP_32K_TIMER=y
|
||||
|
|
@ -242,10 +242,13 @@ CONFIG_CPU_CP15_MMU=y
|
|||
# CONFIG_CPU_DCACHE_DISABLE is not set
|
||||
# CONFIG_CPU_BPREDICT_DISABLE is not set
|
||||
CONFIG_HAS_TLS_REG=y
|
||||
CONFIG_OUTER_CACHE=y
|
||||
CONFIG_CACHE_L2X0=y
|
||||
CONFIG_ARM_L1_CACHE_SHIFT=5
|
||||
# CONFIG_ARM_ERRATA_430973 is not set
|
||||
# CONFIG_ARM_ERRATA_458693 is not set
|
||||
# CONFIG_ARM_ERRATA_460075 is not set
|
||||
CONFIG_PL310_ERRATA_588369=y
|
||||
CONFIG_ARM_GIC=y
|
||||
|
||||
#
|
||||
|
|
@ -304,7 +307,7 @@ CONFIG_ALIGNMENT_TRAP=y
|
|||
#
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600000,20M ramdisk_size=20480"
|
||||
CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480"
|
||||
# CONFIG_XIP_KERNEL is not set
|
||||
# CONFIG_KEXEC is not set
|
||||
|
||||
|
|
@ -488,7 +491,8 @@ CONFIG_GPIOLIB=y
|
|||
# CONFIG_POWER_SUPPLY is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_THERMAL is not set
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_OMAP_WATCHDOG=y
|
||||
CONFIG_SSB_POSSIBLE=y
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -1136,7 +1136,7 @@ CONFIG_TWL4030_USB=y
|
|||
# CONFIG_NOP_USB_XCEIV is not set
|
||||
CONFIG_MMC=y
|
||||
# CONFIG_MMC_DEBUG is not set
|
||||
# CONFIG_MMC_UNSAFE_RESUME is not set
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
|
||||
#
|
||||
# MMC/SD/SDIO Card Drivers
|
||||
|
|
@ -1186,7 +1186,7 @@ CONFIG_RTC_INTF_DEV=y
|
|||
# CONFIG_RTC_DRV_PCF8563 is not set
|
||||
# CONFIG_RTC_DRV_PCF8583 is not set
|
||||
# CONFIG_RTC_DRV_M41T80 is not set
|
||||
# CONFIG_RTC_DRV_TWL4030 is not set
|
||||
CONFIG_RTC_DRV_TWL4030=y
|
||||
# CONFIG_RTC_DRV_S35390A is not set
|
||||
# CONFIG_RTC_DRV_FM3130 is not set
|
||||
# CONFIG_RTC_DRV_RX8581 is not set
|
||||
|
|
@ -1416,7 +1416,7 @@ CONFIG_FRAME_WARN=1024
|
|||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
# CONFIG_DEBUG_SHIRQ is not set
|
||||
|
|
|
|||
|
|
@ -1354,7 +1354,7 @@ CONFIG_USB_OTG_UTILS=y
|
|||
# CONFIG_USB_GPIO_VBUS is not set
|
||||
# CONFIG_ISP1301_OMAP is not set
|
||||
CONFIG_TWL4030_USB=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC=m
|
||||
# CONFIG_MMC_DEBUG is not set
|
||||
# CONFIG_MMC_UNSAFE_RESUME is not set
|
||||
|
||||
|
|
@ -1362,7 +1362,7 @@ CONFIG_MMC=y
|
|||
# MMC/SD/SDIO Card Drivers
|
||||
#
|
||||
CONFIG_MMC_BLOCK=m
|
||||
CONFIG_MMC_BLOCK_BOUNCE=y
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
# CONFIG_SDIO_UART is not set
|
||||
# CONFIG_MMC_TEST is not set
|
||||
|
||||
|
|
|
|||
|
|
@ -235,6 +235,234 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
|
|||
#define smp_mb__before_atomic_inc() smp_mb()
|
||||
#define smp_mb__after_atomic_inc() smp_mb()
|
||||
|
||||
#ifndef CONFIG_GENERIC_ATOMIC64
|
||||
typedef struct {
|
||||
u64 __aligned(8) counter;
|
||||
} atomic64_t;
|
||||
|
||||
#define ATOMIC64_INIT(i) { (i) }
|
||||
|
||||
static inline u64 atomic64_read(atomic64_t *v)
|
||||
{
|
||||
u64 result;
|
||||
|
||||
__asm__ __volatile__("@ atomic64_read\n"
|
||||
" ldrexd %0, %H0, [%1]"
|
||||
: "=&r" (result)
|
||||
: "r" (&v->counter)
|
||||
);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline void atomic64_set(atomic64_t *v, u64 i)
|
||||
{
|
||||
u64 tmp;
|
||||
|
||||
__asm__ __volatile__("@ atomic64_set\n"
|
||||
"1: ldrexd %0, %H0, [%1]\n"
|
||||
" strexd %0, %2, %H2, [%1]\n"
|
||||
" teq %0, #0\n"
|
||||
" bne 1b"
|
||||
: "=&r" (tmp)
|
||||
: "r" (&v->counter), "r" (i)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
static inline void atomic64_add(u64 i, atomic64_t *v)
|
||||
{
|
||||
u64 result;
|
||||
unsigned long tmp;
|
||||
|
||||
__asm__ __volatile__("@ atomic64_add\n"
|
||||
"1: ldrexd %0, %H0, [%2]\n"
|
||||
" adds %0, %0, %3\n"
|
||||
" adc %H0, %H0, %H3\n"
|
||||
" strexd %1, %0, %H0, [%2]\n"
|
||||
" teq %1, #0\n"
|
||||
" bne 1b"
|
||||
: "=&r" (result), "=&r" (tmp)
|
||||
: "r" (&v->counter), "r" (i)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
static inline u64 atomic64_add_return(u64 i, atomic64_t *v)
|
||||
{
|
||||
u64 result;
|
||||
unsigned long tmp;
|
||||
|
||||
smp_mb();
|
||||
|
||||
__asm__ __volatile__("@ atomic64_add_return\n"
|
||||
"1: ldrexd %0, %H0, [%2]\n"
|
||||
" adds %0, %0, %3\n"
|
||||
" adc %H0, %H0, %H3\n"
|
||||
" strexd %1, %0, %H0, [%2]\n"
|
||||
" teq %1, #0\n"
|
||||
" bne 1b"
|
||||
: "=&r" (result), "=&r" (tmp)
|
||||
: "r" (&v->counter), "r" (i)
|
||||
: "cc");
|
||||
|
||||
smp_mb();
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline void atomic64_sub(u64 i, atomic64_t *v)
|
||||
{
|
||||
u64 result;
|
||||
unsigned long tmp;
|
||||
|
||||
__asm__ __volatile__("@ atomic64_sub\n"
|
||||
"1: ldrexd %0, %H0, [%2]\n"
|
||||
" subs %0, %0, %3\n"
|
||||
" sbc %H0, %H0, %H3\n"
|
||||
" strexd %1, %0, %H0, [%2]\n"
|
||||
" teq %1, #0\n"
|
||||
" bne 1b"
|
||||
: "=&r" (result), "=&r" (tmp)
|
||||
: "r" (&v->counter), "r" (i)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
static inline u64 atomic64_sub_return(u64 i, atomic64_t *v)
|
||||
{
|
||||
u64 result;
|
||||
unsigned long tmp;
|
||||
|
||||
smp_mb();
|
||||
|
||||
__asm__ __volatile__("@ atomic64_sub_return\n"
|
||||
"1: ldrexd %0, %H0, [%2]\n"
|
||||
" subs %0, %0, %3\n"
|
||||
" sbc %H0, %H0, %H3\n"
|
||||
" strexd %1, %0, %H0, [%2]\n"
|
||||
" teq %1, #0\n"
|
||||
" bne 1b"
|
||||
: "=&r" (result), "=&r" (tmp)
|
||||
: "r" (&v->counter), "r" (i)
|
||||
: "cc");
|
||||
|
||||
smp_mb();
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new)
|
||||
{
|
||||
u64 oldval;
|
||||
unsigned long res;
|
||||
|
||||
smp_mb();
|
||||
|
||||
do {
|
||||
__asm__ __volatile__("@ atomic64_cmpxchg\n"
|
||||
"ldrexd %1, %H1, [%2]\n"
|
||||
"mov %0, #0\n"
|
||||
"teq %1, %3\n"
|
||||
"teqeq %H1, %H3\n"
|
||||
"strexdeq %0, %4, %H4, [%2]"
|
||||
: "=&r" (res), "=&r" (oldval)
|
||||
: "r" (&ptr->counter), "r" (old), "r" (new)
|
||||
: "cc");
|
||||
} while (res);
|
||||
|
||||
smp_mb();
|
||||
|
||||
return oldval;
|
||||
}
|
||||
|
||||
static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new)
|
||||
{
|
||||
u64 result;
|
||||
unsigned long tmp;
|
||||
|
||||
smp_mb();
|
||||
|
||||
__asm__ __volatile__("@ atomic64_xchg\n"
|
||||
"1: ldrexd %0, %H0, [%2]\n"
|
||||
" strexd %1, %3, %H3, [%2]\n"
|
||||
" teq %1, #0\n"
|
||||
" bne 1b"
|
||||
: "=&r" (result), "=&r" (tmp)
|
||||
: "r" (&ptr->counter), "r" (new)
|
||||
: "cc");
|
||||
|
||||
smp_mb();
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline u64 atomic64_dec_if_positive(atomic64_t *v)
|
||||
{
|
||||
u64 result;
|
||||
unsigned long tmp;
|
||||
|
||||
smp_mb();
|
||||
|
||||
__asm__ __volatile__("@ atomic64_dec_if_positive\n"
|
||||
"1: ldrexd %0, %H0, [%2]\n"
|
||||
" subs %0, %0, #1\n"
|
||||
" sbc %H0, %H0, #0\n"
|
||||
" teq %H0, #0\n"
|
||||
" bmi 2f\n"
|
||||
" strexd %1, %0, %H0, [%2]\n"
|
||||
" teq %1, #0\n"
|
||||
" bne 1b\n"
|
||||
"2:"
|
||||
: "=&r" (result), "=&r" (tmp)
|
||||
: "r" (&v->counter)
|
||||
: "cc");
|
||||
|
||||
smp_mb();
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
|
||||
{
|
||||
u64 val;
|
||||
unsigned long tmp;
|
||||
int ret = 1;
|
||||
|
||||
smp_mb();
|
||||
|
||||
__asm__ __volatile__("@ atomic64_add_unless\n"
|
||||
"1: ldrexd %0, %H0, [%3]\n"
|
||||
" teq %0, %4\n"
|
||||
" teqeq %H0, %H4\n"
|
||||
" moveq %1, #0\n"
|
||||
" beq 2f\n"
|
||||
" adds %0, %0, %5\n"
|
||||
" adc %H0, %H0, %H5\n"
|
||||
" strexd %2, %0, %H0, [%3]\n"
|
||||
" teq %2, #0\n"
|
||||
" bne 1b\n"
|
||||
"2:"
|
||||
: "=&r" (val), "=&r" (ret), "=&r" (tmp)
|
||||
: "r" (&v->counter), "r" (u), "r" (a)
|
||||
: "cc");
|
||||
|
||||
if (ret)
|
||||
smp_mb();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
|
||||
#define atomic64_inc(v) atomic64_add(1LL, (v))
|
||||
#define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
|
||||
#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
|
||||
#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
|
||||
#define atomic64_dec(v) atomic64_sub(1LL, (v))
|
||||
#define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
|
||||
#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
|
||||
#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
|
||||
|
||||
#else /* !CONFIG_GENERIC_ATOMIC64 */
|
||||
#include <asm-generic/atomic64.h>
|
||||
#endif
|
||||
#include <asm-generic/atomic-long.h>
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -197,21 +197,6 @@
|
|||
* DMA Cache Coherency
|
||||
* ===================
|
||||
*
|
||||
* dma_inv_range(start, end)
|
||||
*
|
||||
* Invalidate (discard) the specified virtual address range.
|
||||
* May not write back any entries. If 'start' or 'end'
|
||||
* are not cache line aligned, those lines must be written
|
||||
* back.
|
||||
* - start - virtual start address
|
||||
* - end - virtual end address
|
||||
*
|
||||
* dma_clean_range(start, end)
|
||||
*
|
||||
* Clean (write back) the specified virtual address range.
|
||||
* - start - virtual start address
|
||||
* - end - virtual end address
|
||||
*
|
||||
* dma_flush_range(start, end)
|
||||
*
|
||||
* Clean and invalidate the specified virtual address range.
|
||||
|
|
@ -228,8 +213,9 @@ struct cpu_cache_fns {
|
|||
void (*coherent_user_range)(unsigned long, unsigned long);
|
||||
void (*flush_kern_dcache_area)(void *, size_t);
|
||||
|
||||
void (*dma_inv_range)(const void *, const void *);
|
||||
void (*dma_clean_range)(const void *, const void *);
|
||||
void (*dma_map_area)(const void *, size_t, int);
|
||||
void (*dma_unmap_area)(const void *, size_t, int);
|
||||
|
||||
void (*dma_flush_range)(const void *, const void *);
|
||||
};
|
||||
|
||||
|
|
@ -259,8 +245,8 @@ extern struct cpu_cache_fns cpu_cache;
|
|||
* is visible to DMA, or data written by DMA to system memory is
|
||||
* visible to the CPU.
|
||||
*/
|
||||
#define dmac_inv_range cpu_cache.dma_inv_range
|
||||
#define dmac_clean_range cpu_cache.dma_clean_range
|
||||
#define dmac_map_area cpu_cache.dma_map_area
|
||||
#define dmac_unmap_area cpu_cache.dma_unmap_area
|
||||
#define dmac_flush_range cpu_cache.dma_flush_range
|
||||
|
||||
#else
|
||||
|
|
@ -285,12 +271,12 @@ extern void __cpuc_flush_dcache_area(void *, size_t);
|
|||
* is visible to DMA, or data written by DMA to system memory is
|
||||
* visible to the CPU.
|
||||
*/
|
||||
#define dmac_inv_range __glue(_CACHE,_dma_inv_range)
|
||||
#define dmac_clean_range __glue(_CACHE,_dma_clean_range)
|
||||
#define dmac_map_area __glue(_CACHE,_dma_map_area)
|
||||
#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
|
||||
#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
|
||||
|
||||
extern void dmac_inv_range(const void *, const void *);
|
||||
extern void dmac_clean_range(const void *, const void *);
|
||||
extern void dmac_map_area(const void *, size_t, int);
|
||||
extern void dmac_unmap_area(const void *, size_t, int);
|
||||
extern void dmac_flush_range(const void *, const void *);
|
||||
|
||||
#endif
|
||||
|
|
@ -331,12 +317,8 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
|
|||
* processes address space. Really, we want to allow our "user
|
||||
* space" model to handle this.
|
||||
*/
|
||||
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
|
||||
do { \
|
||||
memcpy(dst, src, len); \
|
||||
flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
|
||||
} while (0)
|
||||
|
||||
extern void copy_to_user_page(struct vm_area_struct *, struct page *,
|
||||
unsigned long, void *, const void *, unsigned long);
|
||||
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
|
||||
do { \
|
||||
memcpy(dst, src, len); \
|
||||
|
|
@ -370,17 +352,6 @@ vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
|
|||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
|
||||
unsigned long uaddr, void *kaddr,
|
||||
unsigned long len, int write)
|
||||
{
|
||||
if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
|
||||
unsigned long addr = (unsigned long)kaddr;
|
||||
__cpuc_coherent_kern_range(addr, addr + len);
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef CONFIG_CPU_CACHE_VIPT
|
||||
#define flush_cache_mm(mm) \
|
||||
vivt_flush_cache_mm(mm)
|
||||
|
|
@ -388,15 +359,10 @@ vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
|
|||
vivt_flush_cache_range(vma,start,end)
|
||||
#define flush_cache_page(vma,addr,pfn) \
|
||||
vivt_flush_cache_page(vma,addr,pfn)
|
||||
#define flush_ptrace_access(vma,page,ua,ka,len,write) \
|
||||
vivt_flush_ptrace_access(vma,page,ua,ka,len,write)
|
||||
#else
|
||||
extern void flush_cache_mm(struct mm_struct *mm);
|
||||
extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
|
||||
extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
|
||||
extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
|
||||
unsigned long uaddr, void *kaddr,
|
||||
unsigned long len, int write);
|
||||
#endif
|
||||
|
||||
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
|
||||
|
|
|
|||
|
|
@ -27,4 +27,7 @@ struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
|
|||
void clkdev_add(struct clk_lookup *cl);
|
||||
void clkdev_drop(struct clk_lookup *cl);
|
||||
|
||||
void clkdev_add_table(struct clk_lookup *, size_t);
|
||||
int clk_add_alias(const char *, const char *, char *, struct device *);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -57,18 +57,58 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
|
|||
#endif
|
||||
|
||||
/*
|
||||
* DMA-consistent mapping functions. These allocate/free a region of
|
||||
* uncached, unwrite-buffered mapped memory space for use with DMA
|
||||
* devices. This is the "generic" version. The PCI specific version
|
||||
* is in pci.h
|
||||
* The DMA API is built upon the notion of "buffer ownership". A buffer
|
||||
* is either exclusively owned by the CPU (and therefore may be accessed
|
||||
* by it) or exclusively owned by the DMA device. These helper functions
|
||||
* represent the transitions between these two ownership states.
|
||||
*
|
||||
* Note: Drivers should NOT use this function directly, as it will break
|
||||
* platforms with CONFIG_DMABOUNCE.
|
||||
* Use the driver DMA support - see dma-mapping.h (dma_sync_*)
|
||||
* Note, however, that on later ARMs, this notion does not work due to
|
||||
* speculative prefetches. We model our approach on the assumption that
|
||||
* the CPU does do speculative prefetches, which means we clean caches
|
||||
* before transfers and delay cache invalidation until transfer completion.
|
||||
*
|
||||
* Private support functions: these are not part of the API and are
|
||||
* liable to change. Drivers must not use these.
|
||||
*/
|
||||
extern void dma_cache_maint(const void *kaddr, size_t size, int rw);
|
||||
extern void dma_cache_maint_page(struct page *page, unsigned long offset,
|
||||
size_t size, int rw);
|
||||
static inline void __dma_single_cpu_to_dev(const void *kaddr, size_t size,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
extern void ___dma_single_cpu_to_dev(const void *, size_t,
|
||||
enum dma_data_direction);
|
||||
|
||||
if (!arch_is_coherent())
|
||||
___dma_single_cpu_to_dev(kaddr, size, dir);
|
||||
}
|
||||
|
||||
static inline void __dma_single_dev_to_cpu(const void *kaddr, size_t size,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
extern void ___dma_single_dev_to_cpu(const void *, size_t,
|
||||
enum dma_data_direction);
|
||||
|
||||
if (!arch_is_coherent())
|
||||
___dma_single_dev_to_cpu(kaddr, size, dir);
|
||||
}
|
||||
|
||||
static inline void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
|
||||
size_t size, enum dma_data_direction dir)
|
||||
{
|
||||
extern void ___dma_page_cpu_to_dev(struct page *, unsigned long,
|
||||
size_t, enum dma_data_direction);
|
||||
|
||||
if (!arch_is_coherent())
|
||||
___dma_page_cpu_to_dev(page, off, size, dir);
|
||||
}
|
||||
|
||||
static inline void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
|
||||
size_t size, enum dma_data_direction dir)
|
||||
{
|
||||
extern void ___dma_page_dev_to_cpu(struct page *, unsigned long,
|
||||
size_t, enum dma_data_direction);
|
||||
|
||||
if (!arch_is_coherent())
|
||||
___dma_page_dev_to_cpu(page, off, size, dir);
|
||||
}
|
||||
|
||||
/*
|
||||
* Return whether the given device DMA address mask can be supported
|
||||
|
|
@ -304,8 +344,7 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
|
|||
{
|
||||
BUG_ON(!valid_dma_direction(dir));
|
||||
|
||||
if (!arch_is_coherent())
|
||||
dma_cache_maint(cpu_addr, size, dir);
|
||||
__dma_single_cpu_to_dev(cpu_addr, size, dir);
|
||||
|
||||
return virt_to_dma(dev, cpu_addr);
|
||||
}
|
||||
|
|
@ -329,8 +368,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
|
|||
{
|
||||
BUG_ON(!valid_dma_direction(dir));
|
||||
|
||||
if (!arch_is_coherent())
|
||||
dma_cache_maint_page(page, offset, size, dir);
|
||||
__dma_page_cpu_to_dev(page, offset, size, dir);
|
||||
|
||||
return page_to_dma(dev, page) + offset;
|
||||
}
|
||||
|
|
@ -352,7 +390,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
|
|||
static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
|
||||
size_t size, enum dma_data_direction dir)
|
||||
{
|
||||
/* nothing to do */
|
||||
__dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -372,7 +410,8 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
|
|||
static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
|
||||
size_t size, enum dma_data_direction dir)
|
||||
{
|
||||
/* nothing to do */
|
||||
__dma_page_dev_to_cpu(dma_to_page(dev, handle), handle & ~PAGE_MASK,
|
||||
size, dir);
|
||||
}
|
||||
#endif /* CONFIG_DMABOUNCE */
|
||||
|
||||
|
|
@ -400,7 +439,10 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev,
|
|||
{
|
||||
BUG_ON(!valid_dma_direction(dir));
|
||||
|
||||
dmabounce_sync_for_cpu(dev, handle, offset, size, dir);
|
||||
if (!dmabounce_sync_for_cpu(dev, handle, offset, size, dir))
|
||||
return;
|
||||
|
||||
__dma_single_dev_to_cpu(dma_to_virt(dev, handle) + offset, size, dir);
|
||||
}
|
||||
|
||||
static inline void dma_sync_single_range_for_device(struct device *dev,
|
||||
|
|
@ -412,8 +454,7 @@ static inline void dma_sync_single_range_for_device(struct device *dev,
|
|||
if (!dmabounce_sync_for_device(dev, handle, offset, size, dir))
|
||||
return;
|
||||
|
||||
if (!arch_is_coherent())
|
||||
dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir);
|
||||
__dma_single_cpu_to_dev(dma_to_virt(dev, handle) + offset, size, dir);
|
||||
}
|
||||
|
||||
static inline void dma_sync_single_for_cpu(struct device *dev,
|
||||
|
|
|
|||
|
|
@ -69,9 +69,16 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
|
|||
/*
|
||||
* __arm_ioremap takes CPU physical address.
|
||||
* __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
|
||||
* The _caller variety takes a __builtin_return_address(0) value for
|
||||
* /proc/vmalloc to use - and should only be used in non-inline functions.
|
||||
*/
|
||||
extern void __iomem * __arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
|
||||
extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int);
|
||||
extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
|
||||
size_t, unsigned int, void *);
|
||||
extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
|
||||
void *);
|
||||
|
||||
extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
|
||||
extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
|
||||
extern void __iounmap(volatile void __iomem *addr);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -46,12 +46,4 @@ struct sys_timer {
|
|||
extern struct sys_timer *system_timer;
|
||||
extern void timer_tick(void);
|
||||
|
||||
/*
|
||||
* Kernel time keeping support.
|
||||
*/
|
||||
struct timespec;
|
||||
extern int (*set_rtc)(void);
|
||||
extern void save_time_delta(struct timespec *delta, struct timespec *rtc);
|
||||
extern void restore_time_delta(struct timespec *delta, struct timespec *rtc);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -76,6 +76,17 @@
|
|||
*/
|
||||
#define IOREMAP_MAX_ORDER 24
|
||||
|
||||
/*
|
||||
* Size of DMA-consistent memory region. Must be multiple of 2M,
|
||||
* between 2MB and 14MB inclusive.
|
||||
*/
|
||||
#ifndef CONSISTENT_DMA_SIZE
|
||||
#define CONSISTENT_DMA_SIZE SZ_2M
|
||||
#endif
|
||||
|
||||
#define CONSISTENT_END (0xffe00000UL)
|
||||
#define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE)
|
||||
|
||||
#else /* CONFIG_MMU */
|
||||
|
||||
/*
|
||||
|
|
@ -93,11 +104,11 @@
|
|||
#endif
|
||||
|
||||
#ifndef PHYS_OFFSET
|
||||
#define PHYS_OFFSET (CONFIG_DRAM_BASE)
|
||||
#define PHYS_OFFSET UL(CONFIG_DRAM_BASE)
|
||||
#endif
|
||||
|
||||
#ifndef END_MEM
|
||||
#define END_MEM (CONFIG_DRAM_BASE + CONFIG_DRAM_SIZE)
|
||||
#define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
|
||||
#endif
|
||||
|
||||
#ifndef PAGE_OFFSET
|
||||
|
|
@ -112,14 +123,6 @@
|
|||
|
||||
#endif /* !CONFIG_MMU */
|
||||
|
||||
/*
|
||||
* Size of DMA-consistent memory region. Must be multiple of 2M,
|
||||
* between 2MB and 14MB inclusive.
|
||||
*/
|
||||
#ifndef CONSISTENT_DMA_SIZE
|
||||
#define CONSISTENT_DMA_SIZE SZ_2M
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Physical vs virtual RAM address space conversion. These are
|
||||
* private definitions which should NOT be used outside memory.h
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
typedef struct {
|
||||
#ifdef CONFIG_CPU_HAS_ASID
|
||||
unsigned int id;
|
||||
spinlock_t id_lock;
|
||||
#endif
|
||||
unsigned int kvm_seq;
|
||||
} mm_context_t;
|
||||
|
|
|
|||
|
|
@ -43,12 +43,23 @@ void __check_kvm_seq(struct mm_struct *mm);
|
|||
#define ASID_FIRST_VERSION (1 << ASID_BITS)
|
||||
|
||||
extern unsigned int cpu_last_asid;
|
||||
#ifdef CONFIG_SMP
|
||||
DECLARE_PER_CPU(struct mm_struct *, current_mm);
|
||||
#endif
|
||||
|
||||
void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
|
||||
void __new_context(struct mm_struct *mm);
|
||||
|
||||
static inline void check_context(struct mm_struct *mm)
|
||||
{
|
||||
/*
|
||||
* This code is executed with interrupts enabled. Therefore,
|
||||
* mm->context.id cannot be updated to the latest ASID version
|
||||
* on a different CPU (and condition below not triggered)
|
||||
* without first getting an IPI to reset the context. The
|
||||
* alternative is to take a read_lock on mm->context.id_lock
|
||||
* (after changing its type to rwlock_t).
|
||||
*/
|
||||
if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
|
||||
__new_context(mm);
|
||||
|
||||
|
|
@ -108,6 +119,10 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
|||
__flush_icache_all();
|
||||
#endif
|
||||
if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
|
||||
#ifdef CONFIG_SMP
|
||||
struct mm_struct **crt_mm = &per_cpu(current_mm, cpu);
|
||||
*crt_mm = next;
|
||||
#endif
|
||||
check_context(next);
|
||||
cpu_switch_mm(next->pgd, next);
|
||||
if (cache_is_vivt())
|
||||
|
|
|
|||
|
|
@ -117,11 +117,12 @@
|
|||
#endif
|
||||
|
||||
struct page;
|
||||
struct vm_area_struct;
|
||||
|
||||
struct cpu_user_fns {
|
||||
void (*cpu_clear_user_highpage)(struct page *page, unsigned long vaddr);
|
||||
void (*cpu_copy_user_highpage)(struct page *to, struct page *from,
|
||||
unsigned long vaddr);
|
||||
unsigned long vaddr, struct vm_area_struct *vma);
|
||||
};
|
||||
|
||||
#ifdef MULTI_USER
|
||||
|
|
@ -137,7 +138,7 @@ extern struct cpu_user_fns cpu_user;
|
|||
|
||||
extern void __cpu_clear_user_highpage(struct page *page, unsigned long vaddr);
|
||||
extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
|
||||
unsigned long vaddr);
|
||||
unsigned long vaddr, struct vm_area_struct *vma);
|
||||
#endif
|
||||
|
||||
#define clear_user_highpage(page,vaddr) \
|
||||
|
|
@ -145,7 +146,7 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
|
|||
|
||||
#define __HAVE_ARCH_COPY_USER_HIGHPAGE
|
||||
#define copy_user_highpage(to,from,vaddr,vma) \
|
||||
__cpu_copy_user_highpage(to, from, vaddr)
|
||||
__cpu_copy_user_highpage(to, from, vaddr, vma)
|
||||
|
||||
#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
|
||||
extern void copy_page(void *to, const void *from);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* linux/arch/arm/include/asm/perf_event.h
|
||||
*
|
||||
* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ARM_PERF_EVENT_H__
|
||||
#define __ARM_PERF_EVENT_H__
|
||||
|
||||
/*
|
||||
* NOP: on *most* (read: all supported) ARM platforms, the performance
|
||||
* counter interrupts are regular interrupts and not an NMI. This
|
||||
* means that when we receive the interrupt we can call
|
||||
* perf_event_do_pending() that handles all of the work with
|
||||
* interrupts enabled.
|
||||
*/
|
||||
static inline void
|
||||
set_perf_event_pending(void)
|
||||
{
|
||||
}
|
||||
|
||||
/* ARM performance counters start from 1 (in the cp15 accesses) so use the
|
||||
* same indexes here for consistency. */
|
||||
#define PERF_EVENT_INDEX_OFFSET 1
|
||||
|
||||
#endif /* __ARM_PERF_EVENT_H__ */
|
||||
|
|
@ -86,8 +86,8 @@ extern unsigned int kobjsize(const void *objp);
|
|||
* All 32bit addresses are effectively valid for vmalloc...
|
||||
* Sort of meaningless for non-VM targets.
|
||||
*/
|
||||
#define VMALLOC_START 0
|
||||
#define VMALLOC_END 0xffffffff
|
||||
#define VMALLOC_START 0UL
|
||||
#define VMALLOC_END 0xffffffffUL
|
||||
|
||||
#define FIRST_USER_ADDRESS (0)
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* linux/arch/arm/include/asm/pmu.h
|
||||
*
|
||||
* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ARM_PMU_H__
|
||||
#define __ARM_PMU_H__
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_PMU
|
||||
|
||||
struct pmu_irqs {
|
||||
const int *irqs;
|
||||
int num_irqs;
|
||||
};
|
||||
|
||||
/**
|
||||
* reserve_pmu() - reserve the hardware performance counters
|
||||
*
|
||||
* Reserve the hardware performance counters in the system for exclusive use.
|
||||
* The 'struct pmu_irqs' for the system is returned on success, ERR_PTR()
|
||||
* encoded error on failure.
|
||||
*/
|
||||
extern const struct pmu_irqs *
|
||||
reserve_pmu(void);
|
||||
|
||||
/**
|
||||
* release_pmu() - Relinquish control of the performance counters
|
||||
*
|
||||
* Release the performance counters and allow someone else to use them.
|
||||
* Callers must have disabled the counters and released IRQs before calling
|
||||
* this. The 'struct pmu_irqs' returned from reserve_pmu() must be passed as
|
||||
* a cookie.
|
||||
*/
|
||||
extern int
|
||||
release_pmu(const struct pmu_irqs *irqs);
|
||||
|
||||
/**
|
||||
* init_pmu() - Initialise the PMU.
|
||||
*
|
||||
* Initialise the system ready for PMU enabling. This should typically set the
|
||||
* IRQ affinity and nothing else. The users (oprofile/perf events etc) will do
|
||||
* the actual hardware initialisation.
|
||||
*/
|
||||
extern int
|
||||
init_pmu(void);
|
||||
|
||||
#else /* CONFIG_CPU_HAS_PMU */
|
||||
|
||||
static inline const struct pmu_irqs *
|
||||
reserve_pmu(void)
|
||||
{
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
static inline int
|
||||
release_pmu(const struct pmu_irqs *irqs)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int
|
||||
init_pmu(void)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CPU_HAS_PMU */
|
||||
|
||||
#endif /* __ARM_PMU_H__ */
|
||||
|
|
@ -223,18 +223,6 @@ extern struct meminfo meminfo;
|
|||
#define bank_phys_end(bank) ((bank)->start + (bank)->size)
|
||||
#define bank_phys_size(bank) (bank)->size
|
||||
|
||||
/*
|
||||
* Early command line parameters.
|
||||
*/
|
||||
struct early_params {
|
||||
const char *arg;
|
||||
void (*fn)(char **p);
|
||||
};
|
||||
|
||||
#define __early_param(name,fn) \
|
||||
static struct early_params __early_##fn __used \
|
||||
__attribute__((__section__(".early_param.init"))) = { name, fn }
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -13,4 +13,9 @@ static inline int tlb_ops_need_broadcast(void)
|
|||
return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
|
||||
}
|
||||
|
||||
static inline int cache_ops_need_broadcast(void)
|
||||
{
|
||||
return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -5,6 +5,22 @@
|
|||
#error SMP not supported on pre-ARMv6 CPUs
|
||||
#endif
|
||||
|
||||
static inline void dsb_sev(void)
|
||||
{
|
||||
#if __LINUX_ARM_ARCH__ >= 7
|
||||
__asm__ __volatile__ (
|
||||
"dsb\n"
|
||||
"sev"
|
||||
);
|
||||
#elif defined(CONFIG_CPU_32v6K)
|
||||
__asm__ __volatile__ (
|
||||
"mcr p15, 0, %0, c7, c10, 4\n"
|
||||
"sev"
|
||||
: : "r" (0)
|
||||
);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* ARMv6 Spin-locking.
|
||||
*
|
||||
|
|
@ -69,13 +85,11 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
|
|||
|
||||
__asm__ __volatile__(
|
||||
" str %1, [%0]\n"
|
||||
#ifdef CONFIG_CPU_32v6K
|
||||
" mcr p15, 0, %1, c7, c10, 4\n" /* DSB */
|
||||
" sev"
|
||||
#endif
|
||||
:
|
||||
: "r" (&lock->lock), "r" (0)
|
||||
: "cc");
|
||||
|
||||
dsb_sev();
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -132,13 +146,11 @@ static inline void arch_write_unlock(arch_rwlock_t *rw)
|
|||
|
||||
__asm__ __volatile__(
|
||||
"str %1, [%0]\n"
|
||||
#ifdef CONFIG_CPU_32v6K
|
||||
" mcr p15, 0, %1, c7, c10, 4\n" /* DSB */
|
||||
" sev\n"
|
||||
#endif
|
||||
:
|
||||
: "r" (&rw->lock), "r" (0)
|
||||
: "cc");
|
||||
|
||||
dsb_sev();
|
||||
}
|
||||
|
||||
/* write_can_lock - would write_trylock() succeed? */
|
||||
|
|
@ -188,14 +200,12 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
|
|||
" strex %1, %0, [%2]\n"
|
||||
" teq %1, #0\n"
|
||||
" bne 1b"
|
||||
#ifdef CONFIG_CPU_32v6K
|
||||
"\n cmp %0, #0\n"
|
||||
" mcreq p15, 0, %0, c7, c10, 4\n"
|
||||
" seveq"
|
||||
#endif
|
||||
: "=&r" (tmp), "=&r" (tmp2)
|
||||
: "r" (&rw->lock)
|
||||
: "cc");
|
||||
|
||||
if (tmp == 0)
|
||||
dsb_sev();
|
||||
}
|
||||
|
||||
static inline int arch_read_trylock(arch_rwlock_t *rw)
|
||||
|
|
|
|||
|
|
@ -73,8 +73,7 @@ extern unsigned int mem_fclk_21285;
|
|||
|
||||
struct pt_regs;
|
||||
|
||||
void die(const char *msg, struct pt_regs *regs, int err)
|
||||
__attribute__((noreturn));
|
||||
void die(const char *msg, struct pt_regs *regs, int err);
|
||||
|
||||
struct siginfo;
|
||||
void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
|
||||
|
|
|
|||
|
|
@ -115,7 +115,8 @@ extern void iwmmxt_task_restore(struct thread_info *, void *);
|
|||
extern void iwmmxt_task_release(struct thread_info *);
|
||||
extern void iwmmxt_task_switch(struct thread_info *);
|
||||
|
||||
extern void vfp_sync_state(struct thread_info *thread);
|
||||
extern void vfp_sync_hwstate(struct thread_info *);
|
||||
extern void vfp_flush_hwstate(struct thread_info *);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -529,7 +529,8 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
|
|||
* cache entries for the kernels virtual memory range are written
|
||||
* back to the page.
|
||||
*/
|
||||
extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
|
||||
extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
|
||||
pte_t *ptep);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ obj-y := compat.o elf.o entry-armv.o entry-common.o irq.o \
|
|||
process.o ptrace.o return_address.o setup.o signal.o \
|
||||
sys_arm.o stacktrace.o time.o traps.o
|
||||
|
||||
obj-$(CONFIG_LEDS) += leds.o
|
||||
obj-$(CONFIG_OC_ETM) += etm.o
|
||||
|
||||
obj-$(CONFIG_ISA_DMA_API) += dma.o
|
||||
|
|
@ -46,6 +47,8 @@ obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
|
|||
obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
|
||||
obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
|
||||
obj-$(CONFIG_IWMMXT) += iwmmxt.o
|
||||
obj-$(CONFIG_CPU_HAS_PMU) += pmu.o
|
||||
obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
|
||||
AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
|
||||
|
||||
ifneq ($(CONFIG_ARCH_EBSA110),y)
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
*/
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/memory.h>
|
||||
|
|
@ -112,5 +113,9 @@ int main(void)
|
|||
#ifdef MULTI_PABORT
|
||||
DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort));
|
||||
#endif
|
||||
BLANK();
|
||||
DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
|
||||
DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
|
||||
DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
|
||||
#if defined(CONFIG_CPU_V6)
|
||||
|
||||
.macro addruart, rx
|
||||
.macro addruart, rx, tmp
|
||||
.endm
|
||||
|
||||
.macro senduart, rd, rx
|
||||
|
|
@ -51,7 +51,7 @@
|
|||
|
||||
#elif defined(CONFIG_CPU_V7)
|
||||
|
||||
.macro addruart, rx
|
||||
.macro addruart, rx, tmp
|
||||
.endm
|
||||
|
||||
.macro senduart, rd, rx
|
||||
|
|
@ -71,7 +71,7 @@ wait: mrc p14, 0, pc, c0, c1, 0
|
|||
|
||||
#elif defined(CONFIG_CPU_XSCALE)
|
||||
|
||||
.macro addruart, rx
|
||||
.macro addruart, rx, tmp
|
||||
.endm
|
||||
|
||||
.macro senduart, rd, rx
|
||||
|
|
@ -98,7 +98,7 @@ wait: mrc p14, 0, pc, c0, c1, 0
|
|||
|
||||
#else
|
||||
|
||||
.macro addruart, rx
|
||||
.macro addruart, rx, tmp
|
||||
.endm
|
||||
|
||||
.macro senduart, rd, rx
|
||||
|
|
@ -164,7 +164,7 @@ ENDPROC(printhex2)
|
|||
.ltorg
|
||||
|
||||
ENTRY(printascii)
|
||||
addruart r3
|
||||
addruart r3, r1
|
||||
b 2f
|
||||
1: waituart r2, r3
|
||||
senduart r1, r3
|
||||
|
|
@ -180,7 +180,7 @@ ENTRY(printascii)
|
|||
ENDPROC(printascii)
|
||||
|
||||
ENTRY(printch)
|
||||
addruart r3
|
||||
addruart r3, r1
|
||||
mov r1, r0
|
||||
mov r0, #0
|
||||
b 1b
|
||||
|
|
|
|||
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* LED support code, ripped out of arch/arm/kernel/time.c
|
||||
*
|
||||
* Copyright (C) 1994-2001 Russell King
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/sysdev.h>
|
||||
|
||||
#include <asm/leds.h>
|
||||
|
||||
static void dummy_leds_event(led_event_t evt)
|
||||
{
|
||||
}
|
||||
|
||||
void (*leds_event)(led_event_t) = dummy_leds_event;
|
||||
|
||||
struct leds_evt_name {
|
||||
const char name[8];
|
||||
int on;
|
||||
int off;
|
||||
};
|
||||
|
||||
static const struct leds_evt_name evt_names[] = {
|
||||
{ "amber", led_amber_on, led_amber_off },
|
||||
{ "blue", led_blue_on, led_blue_off },
|
||||
{ "green", led_green_on, led_green_off },
|
||||
{ "red", led_red_on, led_red_off },
|
||||
};
|
||||
|
||||
static ssize_t leds_store(struct sys_device *dev,
|
||||
struct sysdev_attribute *attr,
|
||||
const char *buf, size_t size)
|
||||
{
|
||||
int ret = -EINVAL, len = strcspn(buf, " ");
|
||||
|
||||
if (len > 0 && buf[len] == '\0')
|
||||
len--;
|
||||
|
||||
if (strncmp(buf, "claim", len) == 0) {
|
||||
leds_event(led_claim);
|
||||
ret = size;
|
||||
} else if (strncmp(buf, "release", len) == 0) {
|
||||
leds_event(led_release);
|
||||
ret = size;
|
||||
} else {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(evt_names); i++) {
|
||||
if (strlen(evt_names[i].name) != len ||
|
||||
strncmp(buf, evt_names[i].name, len) != 0)
|
||||
continue;
|
||||
if (strncmp(buf+len, " on", 3) == 0) {
|
||||
leds_event(evt_names[i].on);
|
||||
ret = size;
|
||||
} else if (strncmp(buf+len, " off", 4) == 0) {
|
||||
leds_event(evt_names[i].off);
|
||||
ret = size;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static SYSDEV_ATTR(event, 0200, NULL, leds_store);
|
||||
|
||||
static int leds_suspend(struct sys_device *dev, pm_message_t state)
|
||||
{
|
||||
leds_event(led_stop);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int leds_resume(struct sys_device *dev)
|
||||
{
|
||||
leds_event(led_start);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int leds_shutdown(struct sys_device *dev)
|
||||
{
|
||||
leds_event(led_halted);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sysdev_class leds_sysclass = {
|
||||
.name = "leds",
|
||||
.shutdown = leds_shutdown,
|
||||
.suspend = leds_suspend,
|
||||
.resume = leds_resume,
|
||||
};
|
||||
|
||||
static struct sys_device leds_device = {
|
||||
.id = 0,
|
||||
.cls = &leds_sysclass,
|
||||
};
|
||||
|
||||
static int __init leds_init(void)
|
||||
{
|
||||
int ret;
|
||||
ret = sysdev_class_register(&leds_sysclass);
|
||||
if (ret == 0)
|
||||
ret = sysdev_register(&leds_device);
|
||||
if (ret == 0)
|
||||
ret = sysdev_create_file(&leds_device, &attr_event);
|
||||
return ret;
|
||||
}
|
||||
|
||||
device_initcall(leds_init);
|
||||
|
||||
EXPORT_SYMBOL(leds_event);
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* linux/arch/arm/kernel/pmu.c
|
||||
*
|
||||
* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/pmu.h>
|
||||
|
||||
/*
|
||||
* Define the IRQs for the system. We could use something like a platform
|
||||
* device but that seems fairly heavyweight for this. Also, the performance
|
||||
* counters can't be removed or hotplugged.
|
||||
*
|
||||
* Ordering is important: init_pmu() will use the ordering to set the affinity
|
||||
* to the corresponding core. e.g. the first interrupt will go to cpu 0, the
|
||||
* second goes to cpu 1 etc.
|
||||
*/
|
||||
static const int irqs[] = {
|
||||
#if defined(CONFIG_ARCH_OMAP2)
|
||||
3,
|
||||
#elif defined(CONFIG_ARCH_BCMRING)
|
||||
IRQ_PMUIRQ,
|
||||
#elif defined(CONFIG_MACH_REALVIEW_EB)
|
||||
IRQ_EB11MP_PMU_CPU0,
|
||||
IRQ_EB11MP_PMU_CPU1,
|
||||
IRQ_EB11MP_PMU_CPU2,
|
||||
IRQ_EB11MP_PMU_CPU3,
|
||||
#elif defined(CONFIG_ARCH_OMAP3)
|
||||
INT_34XX_BENCH_MPU_EMUL,
|
||||
#elif defined(CONFIG_ARCH_IOP32X)
|
||||
IRQ_IOP32X_CORE_PMU,
|
||||
#elif defined(CONFIG_ARCH_IOP33X)
|
||||
IRQ_IOP33X_CORE_PMU,
|
||||
#elif defined(CONFIG_ARCH_PXA)
|
||||
IRQ_PMU,
|
||||
#endif
|
||||
};
|
||||
|
||||
static const struct pmu_irqs pmu_irqs = {
|
||||
.irqs = irqs,
|
||||
.num_irqs = ARRAY_SIZE(irqs),
|
||||
};
|
||||
|
||||
static volatile long pmu_lock;
|
||||
|
||||
const struct pmu_irqs *
|
||||
reserve_pmu(void)
|
||||
{
|
||||
return test_and_set_bit_lock(0, &pmu_lock) ? ERR_PTR(-EBUSY) :
|
||||
&pmu_irqs;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(reserve_pmu);
|
||||
|
||||
int
|
||||
release_pmu(const struct pmu_irqs *irqs)
|
||||
{
|
||||
if (WARN_ON(irqs != &pmu_irqs))
|
||||
return -EINVAL;
|
||||
clear_bit_unlock(0, &pmu_lock);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(release_pmu);
|
||||
|
||||
static int
|
||||
set_irq_affinity(int irq,
|
||||
unsigned int cpu)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
int err = irq_set_affinity(irq, cpumask_of(cpu));
|
||||
if (err)
|
||||
pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
|
||||
irq, cpu);
|
||||
return err;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
int
|
||||
init_pmu(void)
|
||||
{
|
||||
int i, err = 0;
|
||||
|
||||
for (i = 0; i < pmu_irqs.num_irqs; ++i) {
|
||||
err = set_irq_affinity(pmu_irqs.irqs[i], i);
|
||||
if (err)
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(init_pmu);
|
||||
|
|
@ -499,10 +499,41 @@ static struct undef_hook thumb_break_hook = {
|
|||
.fn = break_trap,
|
||||
};
|
||||
|
||||
static int thumb2_break_trap(struct pt_regs *regs, unsigned int instr)
|
||||
{
|
||||
unsigned int instr2;
|
||||
void __user *pc;
|
||||
|
||||
/* Check the second half of the instruction. */
|
||||
pc = (void __user *)(instruction_pointer(regs) + 2);
|
||||
|
||||
if (processor_mode(regs) == SVC_MODE) {
|
||||
instr2 = *(u16 *) pc;
|
||||
} else {
|
||||
get_user(instr2, (u16 __user *)pc);
|
||||
}
|
||||
|
||||
if (instr2 == 0xa000) {
|
||||
ptrace_break(current, regs);
|
||||
return 0;
|
||||
} else {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
static struct undef_hook thumb2_break_hook = {
|
||||
.instr_mask = 0xffff,
|
||||
.instr_val = 0xf7f0,
|
||||
.cpsr_mask = PSR_T_BIT,
|
||||
.cpsr_val = PSR_T_BIT,
|
||||
.fn = thumb2_break_trap,
|
||||
};
|
||||
|
||||
static int __init ptrace_break_init(void)
|
||||
{
|
||||
register_undef_hook(&arm_break_hook);
|
||||
register_undef_hook(&thumb_break_hook);
|
||||
register_undef_hook(&thumb2_break_hook);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -669,7 +700,7 @@ static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data)
|
|||
union vfp_state *vfp = &thread->vfpstate;
|
||||
struct user_vfp __user *ufp = data;
|
||||
|
||||
vfp_sync_state(thread);
|
||||
vfp_sync_hwstate(thread);
|
||||
|
||||
/* copy the floating point registers */
|
||||
if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs,
|
||||
|
|
@ -692,7 +723,7 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
|
|||
union vfp_state *vfp = &thread->vfpstate;
|
||||
struct user_vfp __user *ufp = data;
|
||||
|
||||
vfp_sync_state(thread);
|
||||
vfp_sync_hwstate(thread);
|
||||
|
||||
/* copy the floating point registers */
|
||||
if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs,
|
||||
|
|
@ -703,6 +734,8 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
|
|||
if (get_user(vfp->hard.fpscr, &ufp->fpscr))
|
||||
return -EFAULT;
|
||||
|
||||
vfp_flush_hwstate(thread);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -712,26 +745,10 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
|
|||
int ret;
|
||||
|
||||
switch (request) {
|
||||
/*
|
||||
* read word at location "addr" in the child process.
|
||||
*/
|
||||
case PTRACE_PEEKTEXT:
|
||||
case PTRACE_PEEKDATA:
|
||||
ret = generic_ptrace_peekdata(child, addr, data);
|
||||
break;
|
||||
|
||||
case PTRACE_PEEKUSR:
|
||||
ret = ptrace_read_user(child, addr, (unsigned long __user *)data);
|
||||
break;
|
||||
|
||||
/*
|
||||
* write the word at location addr.
|
||||
*/
|
||||
case PTRACE_POKETEXT:
|
||||
case PTRACE_POKEDATA:
|
||||
ret = generic_ptrace_pokedata(child, addr, data);
|
||||
break;
|
||||
|
||||
case PTRACE_POKEUSR:
|
||||
ret = ptrace_write_user(child, addr, data);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/proc_fs.h>
|
||||
|
||||
#include <asm/unified.h>
|
||||
#include <asm/cpu.h>
|
||||
|
|
@ -118,7 +119,7 @@ EXPORT_SYMBOL(elf_platform);
|
|||
|
||||
static const char *cpu_name;
|
||||
static const char *machine_name;
|
||||
static char __initdata command_line[COMMAND_LINE_SIZE];
|
||||
static char __initdata cmd_line[COMMAND_LINE_SIZE];
|
||||
|
||||
static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
|
||||
static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
|
||||
|
|
@ -418,10 +419,11 @@ static int __init arm_add_memory(unsigned long start, unsigned long size)
|
|||
* Pick out the memory size. We look for mem=size@start,
|
||||
* where start and size are "size[KkMm]"
|
||||
*/
|
||||
static void __init early_mem(char **p)
|
||||
static int __init early_mem(char *p)
|
||||
{
|
||||
static int usermem __initdata = 0;
|
||||
unsigned long size, start;
|
||||
char *endp;
|
||||
|
||||
/*
|
||||
* If the user specifies memory size, we
|
||||
|
|
@ -434,52 +436,15 @@ static void __init early_mem(char **p)
|
|||
}
|
||||
|
||||
start = PHYS_OFFSET;
|
||||
size = memparse(*p, p);
|
||||
if (**p == '@')
|
||||
start = memparse(*p + 1, p);
|
||||
size = memparse(p, &endp);
|
||||
if (*endp == '@')
|
||||
start = memparse(endp + 1, NULL);
|
||||
|
||||
arm_add_memory(start, size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
__early_param("mem=", early_mem);
|
||||
|
||||
/*
|
||||
* Initial parsing of the command line.
|
||||
*/
|
||||
static void __init parse_cmdline(char **cmdline_p, char *from)
|
||||
{
|
||||
char c = ' ', *to = command_line;
|
||||
int len = 0;
|
||||
|
||||
for (;;) {
|
||||
if (c == ' ') {
|
||||
extern struct early_params __early_begin, __early_end;
|
||||
struct early_params *p;
|
||||
|
||||
for (p = &__early_begin; p < &__early_end; p++) {
|
||||
int arglen = strlen(p->arg);
|
||||
|
||||
if (memcmp(from, p->arg, arglen) == 0) {
|
||||
if (to != command_line)
|
||||
to -= 1;
|
||||
from += arglen;
|
||||
p->fn(&from);
|
||||
|
||||
while (*from != ' ' && *from != '\0')
|
||||
from++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
c = *from++;
|
||||
if (!c)
|
||||
break;
|
||||
if (COMMAND_LINE_SIZE <= ++len)
|
||||
break;
|
||||
*to++ = c;
|
||||
}
|
||||
*to = '\0';
|
||||
*cmdline_p = command_line;
|
||||
}
|
||||
early_param("mem", early_mem);
|
||||
|
||||
static void __init
|
||||
setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz)
|
||||
|
|
@ -740,9 +705,15 @@ void __init setup_arch(char **cmdline_p)
|
|||
init_mm.end_data = (unsigned long) _edata;
|
||||
init_mm.brk = (unsigned long) _end;
|
||||
|
||||
memcpy(boot_command_line, from, COMMAND_LINE_SIZE);
|
||||
boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
|
||||
parse_cmdline(cmdline_p, from);
|
||||
/* parse_early_param needs a boot_command_line */
|
||||
strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
|
||||
|
||||
/* populate cmd_line too for later use, preserving boot_command_line */
|
||||
strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
|
||||
*cmdline_p = cmd_line;
|
||||
|
||||
parse_early_param();
|
||||
|
||||
paging_init(mdesc);
|
||||
request_standard_resources(&meminfo, mdesc);
|
||||
|
||||
|
|
@ -783,9 +754,21 @@ static int __init topology_init(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(topology_init);
|
||||
|
||||
#ifdef CONFIG_HAVE_PROC_CPU
|
||||
static int __init proc_cpu_init(void)
|
||||
{
|
||||
struct proc_dir_entry *res;
|
||||
|
||||
res = proc_mkdir("cpu", NULL);
|
||||
if (!res)
|
||||
return -ENOMEM;
|
||||
return 0;
|
||||
}
|
||||
fs_initcall(proc_cpu_init);
|
||||
#endif
|
||||
|
||||
static const char *hwcap_str[] = {
|
||||
"swp",
|
||||
"half",
|
||||
|
|
|
|||
|
|
@ -10,11 +10,6 @@
|
|||
*
|
||||
* This file contains the ARM-specific time handling details:
|
||||
* reading the RTC at bootup, etc...
|
||||
*
|
||||
* 1994-07-02 Alan Modra
|
||||
* fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
|
||||
* 1998-12-20 Updated NTP code according to technical memorandum Jan '96
|
||||
* "A Kernel Model for Precision Timekeeping" by Dave Mills
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -77,11 +72,6 @@ unsigned long profile_pc(struct pt_regs *regs)
|
|||
EXPORT_SYMBOL(profile_pc);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* hook for setting the RTC's idea of the current time.
|
||||
*/
|
||||
int (*set_rtc)(void);
|
||||
|
||||
#ifndef CONFIG_GENERIC_TIME
|
||||
static unsigned long dummy_gettimeoffset(void)
|
||||
{
|
||||
|
|
@ -89,140 +79,6 @@ static unsigned long dummy_gettimeoffset(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
static unsigned long next_rtc_update;
|
||||
|
||||
/*
|
||||
* If we have an externally synchronized linux clock, then update
|
||||
* CMOS clock accordingly every ~11 minutes. set_rtc() has to be
|
||||
* called as close as possible to 500 ms before the new second
|
||||
* starts.
|
||||
*/
|
||||
static inline void do_set_rtc(void)
|
||||
{
|
||||
if (!ntp_synced() || set_rtc == NULL)
|
||||
return;
|
||||
|
||||
if (next_rtc_update &&
|
||||
time_before((unsigned long)xtime.tv_sec, next_rtc_update))
|
||||
return;
|
||||
|
||||
if (xtime.tv_nsec < 500000000 - ((unsigned) tick_nsec >> 1) &&
|
||||
xtime.tv_nsec >= 500000000 + ((unsigned) tick_nsec >> 1))
|
||||
return;
|
||||
|
||||
if (set_rtc())
|
||||
/*
|
||||
* rtc update failed. Try again in 60s
|
||||
*/
|
||||
next_rtc_update = xtime.tv_sec + 60;
|
||||
else
|
||||
next_rtc_update = xtime.tv_sec + 660;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LEDS
|
||||
|
||||
static void dummy_leds_event(led_event_t evt)
|
||||
{
|
||||
}
|
||||
|
||||
void (*leds_event)(led_event_t) = dummy_leds_event;
|
||||
|
||||
struct leds_evt_name {
|
||||
const char name[8];
|
||||
int on;
|
||||
int off;
|
||||
};
|
||||
|
||||
static const struct leds_evt_name evt_names[] = {
|
||||
{ "amber", led_amber_on, led_amber_off },
|
||||
{ "blue", led_blue_on, led_blue_off },
|
||||
{ "green", led_green_on, led_green_off },
|
||||
{ "red", led_red_on, led_red_off },
|
||||
};
|
||||
|
||||
static ssize_t leds_store(struct sys_device *dev,
|
||||
struct sysdev_attribute *attr,
|
||||
const char *buf, size_t size)
|
||||
{
|
||||
int ret = -EINVAL, len = strcspn(buf, " ");
|
||||
|
||||
if (len > 0 && buf[len] == '\0')
|
||||
len--;
|
||||
|
||||
if (strncmp(buf, "claim", len) == 0) {
|
||||
leds_event(led_claim);
|
||||
ret = size;
|
||||
} else if (strncmp(buf, "release", len) == 0) {
|
||||
leds_event(led_release);
|
||||
ret = size;
|
||||
} else {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(evt_names); i++) {
|
||||
if (strlen(evt_names[i].name) != len ||
|
||||
strncmp(buf, evt_names[i].name, len) != 0)
|
||||
continue;
|
||||
if (strncmp(buf+len, " on", 3) == 0) {
|
||||
leds_event(evt_names[i].on);
|
||||
ret = size;
|
||||
} else if (strncmp(buf+len, " off", 4) == 0) {
|
||||
leds_event(evt_names[i].off);
|
||||
ret = size;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static SYSDEV_ATTR(event, 0200, NULL, leds_store);
|
||||
|
||||
static int leds_suspend(struct sys_device *dev, pm_message_t state)
|
||||
{
|
||||
leds_event(led_stop);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int leds_resume(struct sys_device *dev)
|
||||
{
|
||||
leds_event(led_start);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int leds_shutdown(struct sys_device *dev)
|
||||
{
|
||||
leds_event(led_halted);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sysdev_class leds_sysclass = {
|
||||
.name = "leds",
|
||||
.shutdown = leds_shutdown,
|
||||
.suspend = leds_suspend,
|
||||
.resume = leds_resume,
|
||||
};
|
||||
|
||||
static struct sys_device leds_device = {
|
||||
.id = 0,
|
||||
.cls = &leds_sysclass,
|
||||
};
|
||||
|
||||
static int __init leds_init(void)
|
||||
{
|
||||
int ret;
|
||||
ret = sysdev_class_register(&leds_sysclass);
|
||||
if (ret == 0)
|
||||
ret = sysdev_register(&leds_device);
|
||||
if (ret == 0)
|
||||
ret = sysdev_create_file(&leds_device, &attr_event);
|
||||
return ret;
|
||||
}
|
||||
|
||||
device_initcall(leds_init);
|
||||
|
||||
EXPORT_SYMBOL(leds_event);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LEDS_TIMER
|
||||
static inline void do_leds(void)
|
||||
{
|
||||
|
|
@ -295,39 +151,6 @@ int do_settimeofday(struct timespec *tv)
|
|||
EXPORT_SYMBOL(do_settimeofday);
|
||||
#endif /* !CONFIG_GENERIC_TIME */
|
||||
|
||||
/**
|
||||
* save_time_delta - Save the offset between system time and RTC time
|
||||
* @delta: pointer to timespec to store delta
|
||||
* @rtc: pointer to timespec for current RTC time
|
||||
*
|
||||
* Return a delta between the system time and the RTC time, such
|
||||
* that system time can be restored later with restore_time_delta()
|
||||
*/
|
||||
void save_time_delta(struct timespec *delta, struct timespec *rtc)
|
||||
{
|
||||
set_normalized_timespec(delta,
|
||||
xtime.tv_sec - rtc->tv_sec,
|
||||
xtime.tv_nsec - rtc->tv_nsec);
|
||||
}
|
||||
EXPORT_SYMBOL(save_time_delta);
|
||||
|
||||
/**
|
||||
* restore_time_delta - Restore the current system time
|
||||
* @delta: delta returned by save_time_delta()
|
||||
* @rtc: pointer to timespec for current RTC time
|
||||
*/
|
||||
void restore_time_delta(struct timespec *delta, struct timespec *rtc)
|
||||
{
|
||||
struct timespec ts;
|
||||
|
||||
set_normalized_timespec(&ts,
|
||||
delta->tv_sec + rtc->tv_sec,
|
||||
delta->tv_nsec + rtc->tv_nsec);
|
||||
|
||||
do_settimeofday(&ts);
|
||||
}
|
||||
EXPORT_SYMBOL(restore_time_delta);
|
||||
|
||||
#ifndef CONFIG_GENERIC_CLOCKEVENTS
|
||||
/*
|
||||
* Kernel system timer support.
|
||||
|
|
@ -336,7 +159,6 @@ void timer_tick(void)
|
|||
{
|
||||
profile_tick(CPU_PROFILING);
|
||||
do_leds();
|
||||
do_set_rtc();
|
||||
write_seqlock(&xtime_lock);
|
||||
do_timer(1);
|
||||
write_sequnlock(&xtime_lock);
|
||||
|
|
|
|||
|
|
@ -12,15 +12,17 @@
|
|||
* 'linux/arch/arm/lib/traps.S'. Mostly a debugging aid, but will probably
|
||||
* kill the offending process.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/personality.h>
|
||||
#include <linux/kallsyms.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/hardirq.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/hardirq.h>
|
||||
#include <linux/kdebug.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kexec.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
|
@ -224,14 +226,21 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
|
|||
#define S_SMP ""
|
||||
#endif
|
||||
|
||||
static void __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs)
|
||||
static int __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs)
|
||||
{
|
||||
struct task_struct *tsk = thread->task;
|
||||
static int die_counter;
|
||||
int ret;
|
||||
|
||||
printk(KERN_EMERG "Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
|
||||
str, err, ++die_counter);
|
||||
sysfs_printk_last_file();
|
||||
|
||||
/* trap and error numbers are mostly meaningless on ARM */
|
||||
ret = notify_die(DIE_OOPS, str, regs, err, tsk->thread.trap_no, SIGSEGV);
|
||||
if (ret == NOTIFY_STOP)
|
||||
return ret;
|
||||
|
||||
print_modules();
|
||||
__show_regs(regs);
|
||||
printk(KERN_EMERG "Process %.*s (pid: %d, stack limit = 0x%p)\n",
|
||||
|
|
@ -243,6 +252,8 @@ static void __die(const char *str, int err, struct thread_info *thread, struct p
|
|||
dump_backtrace(regs, tsk);
|
||||
dump_instr(KERN_EMERG, regs);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
DEFINE_SPINLOCK(die_lock);
|
||||
|
|
@ -250,16 +261,21 @@ DEFINE_SPINLOCK(die_lock);
|
|||
/*
|
||||
* This function is protected against re-entrancy.
|
||||
*/
|
||||
NORET_TYPE void die(const char *str, struct pt_regs *regs, int err)
|
||||
void die(const char *str, struct pt_regs *regs, int err)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
int ret;
|
||||
|
||||
oops_enter();
|
||||
|
||||
spin_lock_irq(&die_lock);
|
||||
console_verbose();
|
||||
bust_spinlocks(1);
|
||||
__die(str, err, thread, regs);
|
||||
ret = __die(str, err, thread, regs);
|
||||
|
||||
if (regs && kexec_should_crash(thread->task))
|
||||
crash_kexec(regs);
|
||||
|
||||
bust_spinlocks(0);
|
||||
add_taint(TAINT_DIE);
|
||||
spin_unlock_irq(&die_lock);
|
||||
|
|
@ -267,11 +283,10 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err)
|
|||
|
||||
if (in_interrupt())
|
||||
panic("Fatal exception in interrupt");
|
||||
|
||||
if (panic_on_oops)
|
||||
panic("Fatal exception");
|
||||
|
||||
do_exit(SIGSEGV);
|
||||
if (ret != NOTIFY_STOP)
|
||||
do_exit(SIGSEGV);
|
||||
}
|
||||
|
||||
void arm_notify_die(const char *str, struct pt_regs *regs,
|
||||
|
|
|
|||
|
|
@ -43,10 +43,6 @@ SECTIONS
|
|||
|
||||
INIT_SETUP(16)
|
||||
|
||||
__early_begin = .;
|
||||
*(.early_param.init)
|
||||
__early_end = .;
|
||||
|
||||
INIT_CALLS
|
||||
CON_INITCALL
|
||||
SECURITY_INITCALL
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
|
||||
#include "hardware.h"
|
||||
.macro addruart,rx
|
||||
.macro addruart, rx, tmp
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ MMU enabled?
|
||||
moveq \rx, #0x80000000 @ physical
|
||||
|
|
|
|||
|
|
@ -89,6 +89,12 @@ config ARCH_AT91CAP9
|
|||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_FB_ATMEL
|
||||
|
||||
config ARCH_AT572D940HF
|
||||
bool "AT572D940HF"
|
||||
select CPU_ARM926T
|
||||
select GENERIC_TIME
|
||||
select GENERIC_CLOCKEVENTS
|
||||
|
||||
config ARCH_AT91X40
|
||||
bool "AT91x40"
|
||||
|
||||
|
|
@ -390,6 +396,23 @@ endif
|
|||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
if ARCH_AT572D940HF
|
||||
|
||||
comment "AT572D940HF Board Type"
|
||||
|
||||
config MACH_AT572D940HFEB
|
||||
bool "AT572D940HF-EK"
|
||||
depends on ARCH_AT572D940HF
|
||||
select HAVE_AT91_DATAFLASH_CARD
|
||||
select HAVE_NAND_ATMEL_BUSWIDTH_16
|
||||
help
|
||||
Select this if you are using Atmel's AT572D940HF-EK evaluation kit.
|
||||
<http://www.atmel.com/products/diopsis/default.asp>
|
||||
|
||||
endif
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
if ARCH_AT91X40
|
||||
|
||||
comment "AT91X40 Board Type"
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devi
|
|||
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
|
||||
|
||||
# AT91RM9200 board-specific support
|
||||
|
|
@ -69,6 +70,9 @@ obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
|
|||
# AT91CAP9 board-specific support
|
||||
obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
|
||||
|
||||
# AT572D940HF board-specific support
|
||||
obj-$(CONFIG_MACH_AT572D940HFEB) += board-at572d940hf_ek.o
|
||||
|
||||
# AT91X40 board-specific support
|
||||
obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,377 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/at572d940hf.c
|
||||
*
|
||||
* Antonio R. Costa <costa.antonior@gmail.com>
|
||||
* Copyright (C) 2008 Atmel
|
||||
*
|
||||
* Copyright (C) 2005 SAN People
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/at572d940hf.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
#include <mach/at91_rstc.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "clock.h"
|
||||
|
||||
static struct map_desc at572d940hf_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = AT91_VA_BASE_SYS,
|
||||
.pfn = __phys_to_pfn(AT91_BASE_SYS),
|
||||
.length = SZ_16K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = AT91_IO_VIRT_BASE - AT572D940HF_SRAM_SIZE,
|
||||
.pfn = __phys_to_pfn(AT572D940HF_SRAM_BASE),
|
||||
.length = AT572D940HF_SRAM_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Clocks
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* The peripheral clocks.
|
||||
*/
|
||||
static struct clk pioA_clk = {
|
||||
.name = "pioA_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_PIOA,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioB_clk = {
|
||||
.name = "pioB_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_PIOB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioC_clk = {
|
||||
.name = "pioC_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_PIOC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk macb_clk = {
|
||||
.name = "macb_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_EMAC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart0_clk = {
|
||||
.name = "usart0_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_US0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart1_clk = {
|
||||
.name = "usart1_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_US1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart2_clk = {
|
||||
.name = "usart2_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_US2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mmc_clk = {
|
||||
.name = "mci_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_MCI,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk udc_clk = {
|
||||
.name = "udc_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_UDP,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi0_clk = {
|
||||
.name = "twi0_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_TWI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi0_clk = {
|
||||
.name = "spi0_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_SPI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi1_clk = {
|
||||
.name = "spi1_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_SPI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc0_clk = {
|
||||
.name = "ssc0_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_SSC0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc1_clk = {
|
||||
.name = "ssc1_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_SSC1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc2_clk = {
|
||||
.name = "ssc2_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_SSC2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tc0_clk = {
|
||||
.name = "tc0_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_TC0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tc1_clk = {
|
||||
.name = "tc1_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_TC1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tc2_clk = {
|
||||
.name = "tc2_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_TC2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ohci_clk = {
|
||||
.name = "ohci_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_UHP,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc3_clk = {
|
||||
.name = "ssc3_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_SSC3,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi1_clk = {
|
||||
.name = "twi1_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_TWI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk can0_clk = {
|
||||
.name = "can0_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_CAN0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk can1_clk = {
|
||||
.name = "can1_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_CAN1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mAgicV_clk = {
|
||||
.name = "mAgicV_clk",
|
||||
.pmc_mask = 1 << AT572D940HF_ID_MSIRQ0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
|
||||
|
||||
static struct clk *periph_clocks[] __initdata = {
|
||||
&pioA_clk,
|
||||
&pioB_clk,
|
||||
&pioC_clk,
|
||||
&macb_clk,
|
||||
&usart0_clk,
|
||||
&usart1_clk,
|
||||
&usart2_clk,
|
||||
&mmc_clk,
|
||||
&udc_clk,
|
||||
&twi0_clk,
|
||||
&spi0_clk,
|
||||
&spi1_clk,
|
||||
&ssc0_clk,
|
||||
&ssc1_clk,
|
||||
&ssc2_clk,
|
||||
&tc0_clk,
|
||||
&tc1_clk,
|
||||
&tc2_clk,
|
||||
&ohci_clk,
|
||||
&ssc3_clk,
|
||||
&twi1_clk,
|
||||
&can0_clk,
|
||||
&can1_clk,
|
||||
&mAgicV_clk,
|
||||
/* irq0 .. irq2 */
|
||||
};
|
||||
|
||||
/*
|
||||
* The five programmable clocks.
|
||||
* You must configure pin multiplexing to bring these signals out.
|
||||
*/
|
||||
static struct clk pck0 = {
|
||||
.name = "pck0",
|
||||
.pmc_mask = AT91_PMC_PCK0,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 0,
|
||||
};
|
||||
static struct clk pck1 = {
|
||||
.name = "pck1",
|
||||
.pmc_mask = AT91_PMC_PCK1,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 1,
|
||||
};
|
||||
static struct clk pck2 = {
|
||||
.name = "pck2",
|
||||
.pmc_mask = AT91_PMC_PCK2,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 2,
|
||||
};
|
||||
static struct clk pck3 = {
|
||||
.name = "pck3",
|
||||
.pmc_mask = AT91_PMC_PCK3,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 3,
|
||||
};
|
||||
|
||||
static struct clk mAgicV_mem_clk = {
|
||||
.name = "mAgicV_mem_clk",
|
||||
.pmc_mask = AT91_PMC_PCK4,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 4,
|
||||
};
|
||||
|
||||
/* HClocks */
|
||||
static struct clk hck0 = {
|
||||
.name = "hck0",
|
||||
.pmc_mask = AT91_PMC_HCK0,
|
||||
.type = CLK_TYPE_SYSTEM,
|
||||
.id = 0,
|
||||
};
|
||||
static struct clk hck1 = {
|
||||
.name = "hck1",
|
||||
.pmc_mask = AT91_PMC_HCK1,
|
||||
.type = CLK_TYPE_SYSTEM,
|
||||
.id = 1,
|
||||
};
|
||||
|
||||
static void __init at572d940hf_register_clocks(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
||||
clk_register(periph_clocks[i]);
|
||||
|
||||
clk_register(&pck0);
|
||||
clk_register(&pck1);
|
||||
clk_register(&pck2);
|
||||
clk_register(&pck3);
|
||||
clk_register(&mAgicV_mem_clk);
|
||||
|
||||
clk_register(&hck0);
|
||||
clk_register(&hck1);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* GPIO
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static struct at91_gpio_bank at572d940hf_gpio[] = {
|
||||
{
|
||||
.id = AT572D940HF_ID_PIOA,
|
||||
.offset = AT91_PIOA,
|
||||
.clock = &pioA_clk,
|
||||
}, {
|
||||
.id = AT572D940HF_ID_PIOB,
|
||||
.offset = AT91_PIOB,
|
||||
.clock = &pioB_clk,
|
||||
}, {
|
||||
.id = AT572D940HF_ID_PIOC,
|
||||
.offset = AT91_PIOC,
|
||||
.clock = &pioC_clk,
|
||||
}
|
||||
};
|
||||
|
||||
static void at572d940hf_reset(void)
|
||||
{
|
||||
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
|
||||
}
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT572D940HF processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
void __init at572d940hf_initialize(unsigned long main_clock)
|
||||
{
|
||||
/* Map peripherals */
|
||||
iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc));
|
||||
|
||||
at91_arch_reset = at572d940hf_reset;
|
||||
at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1)
|
||||
| (1 << AT572D940HF_ID_IRQ2);
|
||||
|
||||
/* Init clock subsystem */
|
||||
at91_clock_init(main_clock);
|
||||
|
||||
/* Register the processor-specific clocks */
|
||||
at572d940hf_register_clocks();
|
||||
|
||||
/* Register GPIO subsystem */
|
||||
at91_gpio_init(at572d940hf_gpio, 3);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Interrupt initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* The default interrupt priority levels (0 = lowest, 7 = highest).
|
||||
*/
|
||||
static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
||||
7, /* Advanced Interrupt Controller */
|
||||
7, /* System Peripherals */
|
||||
0, /* Parallel IO Controller A */
|
||||
0, /* Parallel IO Controller B */
|
||||
0, /* Parallel IO Controller C */
|
||||
3, /* Ethernet */
|
||||
6, /* USART 0 */
|
||||
6, /* USART 1 */
|
||||
6, /* USART 2 */
|
||||
0, /* Multimedia Card Interface */
|
||||
4, /* USB Device Port */
|
||||
0, /* Two-Wire Interface 0 */
|
||||
6, /* Serial Peripheral Interface 0 */
|
||||
6, /* Serial Peripheral Interface 1 */
|
||||
5, /* Serial Synchronous Controller 0 */
|
||||
5, /* Serial Synchronous Controller 1 */
|
||||
5, /* Serial Synchronous Controller 2 */
|
||||
0, /* Timer Counter 0 */
|
||||
0, /* Timer Counter 1 */
|
||||
0, /* Timer Counter 2 */
|
||||
3, /* USB Host port */
|
||||
3, /* Serial Synchronous Controller 3 */
|
||||
0, /* Two-Wire Interface 1 */
|
||||
0, /* CAN Controller 0 */
|
||||
0, /* CAN Controller 1 */
|
||||
0, /* mAgicV HALT line */
|
||||
0, /* mAgicV SIRQ0 line */
|
||||
0, /* mAgicV exception line */
|
||||
0, /* mAgicV end of DMA line */
|
||||
0, /* Advanced Interrupt Controller */
|
||||
0, /* Advanced Interrupt Controller */
|
||||
0, /* Advanced Interrupt Controller */
|
||||
};
|
||||
|
||||
void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS])
|
||||
{
|
||||
if (!priority)
|
||||
priority = at572d940hf_default_irq_priority;
|
||||
|
||||
/* Initialize the AIC interrupt controller */
|
||||
at91_aic_init(priority);
|
||||
|
||||
/* Enable GPIO interrupts */
|
||||
at91_gpio_irq_setup();
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,970 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/at572d940hf_devices.c
|
||||
*
|
||||
* Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
|
||||
* Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
|
||||
* Copyright (C) 2005 David Brownell
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/at572d940hf.h>
|
||||
#include <mach/at572d940hf_matrix.h>
|
||||
#include <mach/at91sam9_smc.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "sam9_smc.h"
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* USB Host
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
|
||||
static u64 ohci_dmamask = DMA_BIT_MASK(32);
|
||||
static struct at91_usbh_data usbh_data;
|
||||
|
||||
static struct resource usbh_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_UHP_BASE,
|
||||
.end = AT572D940HF_UHP_BASE + SZ_1M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_UHP,
|
||||
.end = AT572D940HF_ID_UHP,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_usbh_device = {
|
||||
.name = "at91_ohci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &ohci_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &usbh_data,
|
||||
},
|
||||
.resource = usbh_resources,
|
||||
.num_resources = ARRAY_SIZE(usbh_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_usbh(struct at91_usbh_data *data)
|
||||
{
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
usbh_data = *data;
|
||||
platform_device_register(&at572d940hf_usbh_device);
|
||||
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* USB Device (Gadget)
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifdef CONFIG_USB_GADGET_AT91
|
||||
static struct at91_udc_data udc_data;
|
||||
|
||||
static struct resource udc_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_UDP,
|
||||
.end = AT572D940HF_BASE_UDP + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_UDP,
|
||||
.end = AT572D940HF_ID_UDP,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_udc_device = {
|
||||
.name = "at91_udc",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &udc_data,
|
||||
},
|
||||
.resource = udc_resources,
|
||||
.num_resources = ARRAY_SIZE(udc_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_udc(struct at91_udc_data *data)
|
||||
{
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
if (data->vbus_pin) {
|
||||
at91_set_gpio_input(data->vbus_pin, 0);
|
||||
at91_set_deglitch(data->vbus_pin, 1);
|
||||
}
|
||||
|
||||
/* Pullup pin is handled internally */
|
||||
|
||||
udc_data = *data;
|
||||
platform_device_register(&at572d940hf_udc_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_udc(struct at91_udc_data *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Ethernet
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
|
||||
static u64 eth_dmamask = DMA_BIT_MASK(32);
|
||||
static struct at91_eth_data eth_data;
|
||||
|
||||
static struct resource eth_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_EMAC,
|
||||
.end = AT572D940HF_BASE_EMAC + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_EMAC,
|
||||
.end = AT572D940HF_ID_EMAC,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_eth_device = {
|
||||
.name = "macb",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = ð_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = ð_data,
|
||||
},
|
||||
.resource = eth_resources,
|
||||
.num_resources = ARRAY_SIZE(eth_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_eth(struct at91_eth_data *data)
|
||||
{
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
if (data->phy_irq_pin) {
|
||||
at91_set_gpio_input(data->phy_irq_pin, 0);
|
||||
at91_set_deglitch(data->phy_irq_pin, 1);
|
||||
}
|
||||
|
||||
/* Only RMII is supported */
|
||||
data->is_rmii = 1;
|
||||
|
||||
/* Pins used for RMII */
|
||||
at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXCK_EREFCK */
|
||||
at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
|
||||
at91_set_A_periph(AT91_PIN_PA18, 0); /* ERX0 */
|
||||
at91_set_A_periph(AT91_PIN_PA19, 0); /* ERX1 */
|
||||
at91_set_A_periph(AT91_PIN_PA20, 0); /* ERXER */
|
||||
at91_set_A_periph(AT91_PIN_PA23, 0); /* ETXEN */
|
||||
at91_set_A_periph(AT91_PIN_PA21, 0); /* ETX0 */
|
||||
at91_set_A_periph(AT91_PIN_PA22, 0); /* ETX1 */
|
||||
at91_set_A_periph(AT91_PIN_PA13, 0); /* EMDIO */
|
||||
at91_set_A_periph(AT91_PIN_PA14, 0); /* EMDC */
|
||||
|
||||
eth_data = *data;
|
||||
platform_device_register(&at572d940hf_eth_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_eth(struct at91_eth_data *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* MMC / SD
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
|
||||
static u64 mmc_dmamask = DMA_BIT_MASK(32);
|
||||
static struct at91_mmc_data mmc_data;
|
||||
|
||||
static struct resource mmc_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_MCI,
|
||||
.end = AT572D940HF_BASE_MCI + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_MCI,
|
||||
.end = AT572D940HF_ID_MCI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_mmc_device = {
|
||||
.name = "at91_mci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &mmc_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &mmc_data,
|
||||
},
|
||||
.resource = mmc_resources,
|
||||
.num_resources = ARRAY_SIZE(mmc_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
|
||||
{
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
/* input/irq */
|
||||
if (data->det_pin) {
|
||||
at91_set_gpio_input(data->det_pin, 1);
|
||||
at91_set_deglitch(data->det_pin, 1);
|
||||
}
|
||||
if (data->wp_pin)
|
||||
at91_set_gpio_input(data->wp_pin, 1);
|
||||
if (data->vcc_pin)
|
||||
at91_set_gpio_output(data->vcc_pin, 0);
|
||||
|
||||
/* CLK */
|
||||
at91_set_A_periph(AT91_PIN_PC22, 0);
|
||||
|
||||
/* CMD */
|
||||
at91_set_A_periph(AT91_PIN_PC23, 1);
|
||||
|
||||
/* DAT0, maybe DAT1..DAT3 */
|
||||
at91_set_A_periph(AT91_PIN_PC24, 1);
|
||||
if (data->wire4) {
|
||||
at91_set_A_periph(AT91_PIN_PC25, 1);
|
||||
at91_set_A_periph(AT91_PIN_PC26, 1);
|
||||
at91_set_A_periph(AT91_PIN_PC27, 1);
|
||||
}
|
||||
|
||||
mmc_data = *data;
|
||||
platform_device_register(&at572d940hf_mmc_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* NAND / SmartMedia
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
|
||||
static struct atmel_nand_data nand_data;
|
||||
|
||||
#define NAND_BASE AT91_CHIPSELECT_3
|
||||
|
||||
static struct resource nand_resources[] = {
|
||||
{
|
||||
.start = NAND_BASE,
|
||||
.end = NAND_BASE + SZ_256M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_nand_device = {
|
||||
.name = "atmel_nand",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &nand_data,
|
||||
},
|
||||
.resource = nand_resources,
|
||||
.num_resources = ARRAY_SIZE(nand_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_nand(struct atmel_nand_data *data)
|
||||
{
|
||||
unsigned long csa;
|
||||
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
|
||||
|
||||
/* enable pin */
|
||||
if (data->enable_pin)
|
||||
at91_set_gpio_output(data->enable_pin, 1);
|
||||
|
||||
/* ready/busy pin */
|
||||
if (data->rdy_pin)
|
||||
at91_set_gpio_input(data->rdy_pin, 1);
|
||||
|
||||
/* card detect pin */
|
||||
if (data->det_pin)
|
||||
at91_set_gpio_input(data->det_pin, 1);
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PB28, 0); /* A[22] */
|
||||
at91_set_B_periph(AT91_PIN_PA28, 0); /* NANDOE */
|
||||
at91_set_B_periph(AT91_PIN_PA29, 0); /* NANDWE */
|
||||
|
||||
nand_data = *data;
|
||||
platform_device_register(&at572d940hf_nand_device);
|
||||
}
|
||||
|
||||
#else
|
||||
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* TWI (i2c)
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Prefer the GPIO code since the TWI controller isn't robust
|
||||
* (gets overruns and underruns under load) and can only issue
|
||||
* repeated STARTs in one scenario (the driver doesn't yet handle them).
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
|
||||
|
||||
static struct i2c_gpio_platform_data pdata = {
|
||||
.sda_pin = AT91_PIN_PC7,
|
||||
.sda_is_open_drain = 1,
|
||||
.scl_pin = AT91_PIN_PC8,
|
||||
.scl_is_open_drain = 1,
|
||||
.udelay = 2, /* ~100 kHz */
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_twi_device {
|
||||
.name = "i2c-gpio",
|
||||
.id = -1,
|
||||
.dev.platform_data = &pdata,
|
||||
};
|
||||
|
||||
void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
|
||||
{
|
||||
at91_set_GPIO_periph(AT91_PIN_PC7, 1); /* TWD (SDA) */
|
||||
at91_set_multi_drive(AT91_PIN_PC7, 1);
|
||||
|
||||
at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
|
||||
at91_set_multi_drive(AT91_PIN_PC8, 1);
|
||||
|
||||
i2c_register_board_info(0, devices, nr_devices);
|
||||
platform_device_register(&at572d940hf_twi_device);
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
|
||||
|
||||
static struct resource twi0_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_TWI0,
|
||||
.end = AT572D940HF_BASE_TWI0 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_TWI0,
|
||||
.end = AT572D940HF_ID_TWI0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_twi0_device = {
|
||||
.name = "at91_i2c",
|
||||
.id = 0,
|
||||
.resource = twi0_resources,
|
||||
.num_resources = ARRAY_SIZE(twi0_resources),
|
||||
};
|
||||
|
||||
static struct resource twi1_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_TWI1,
|
||||
.end = AT572D940HF_BASE_TWI1 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_TWI1,
|
||||
.end = AT572D940HF_ID_TWI1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_twi1_device = {
|
||||
.name = "at91_i2c",
|
||||
.id = 1,
|
||||
.resource = twi1_resources,
|
||||
.num_resources = ARRAY_SIZE(twi1_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
|
||||
{
|
||||
/* pins used for TWI0 interface */
|
||||
at91_set_A_periph(AT91_PIN_PC7, 0); /* TWD */
|
||||
at91_set_multi_drive(AT91_PIN_PC7, 1);
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PC8, 0); /* TWCK */
|
||||
at91_set_multi_drive(AT91_PIN_PC8, 1);
|
||||
|
||||
/* pins used for TWI1 interface */
|
||||
at91_set_A_periph(AT91_PIN_PC20, 0); /* TWD */
|
||||
at91_set_multi_drive(AT91_PIN_PC20, 1);
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PC21, 0); /* TWCK */
|
||||
at91_set_multi_drive(AT91_PIN_PC21, 1);
|
||||
|
||||
i2c_register_board_info(0, devices, nr_devices);
|
||||
platform_device_register(&at572d940hf_twi0_device);
|
||||
platform_device_register(&at572d940hf_twi1_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* SPI
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
|
||||
static u64 spi_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct resource spi0_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_SPI0,
|
||||
.end = AT572D940HF_BASE_SPI0 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_SPI0,
|
||||
.end = AT572D940HF_ID_SPI0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_spi0_device = {
|
||||
.name = "atmel_spi",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &spi_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.resource = spi0_resources,
|
||||
.num_resources = ARRAY_SIZE(spi0_resources),
|
||||
};
|
||||
|
||||
static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
|
||||
|
||||
static struct resource spi1_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_SPI1,
|
||||
.end = AT572D940HF_BASE_SPI1 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_SPI1,
|
||||
.end = AT572D940HF_ID_SPI1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_spi1_device = {
|
||||
.name = "atmel_spi",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.dma_mask = &spi_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.resource = spi1_resources,
|
||||
.num_resources = ARRAY_SIZE(spi1_resources),
|
||||
};
|
||||
|
||||
static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 };
|
||||
|
||||
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
|
||||
{
|
||||
int i;
|
||||
unsigned long cs_pin;
|
||||
short enable_spi0 = 0;
|
||||
short enable_spi1 = 0;
|
||||
|
||||
/* Choose SPI chip-selects */
|
||||
for (i = 0; i < nr_devices; i++) {
|
||||
if (devices[i].controller_data)
|
||||
cs_pin = (unsigned long) devices[i].controller_data;
|
||||
else if (devices[i].bus_num == 0)
|
||||
cs_pin = spi0_standard_cs[devices[i].chip_select];
|
||||
else
|
||||
cs_pin = spi1_standard_cs[devices[i].chip_select];
|
||||
|
||||
if (devices[i].bus_num == 0)
|
||||
enable_spi0 = 1;
|
||||
else
|
||||
enable_spi1 = 1;
|
||||
|
||||
/* enable chip-select pin */
|
||||
at91_set_gpio_output(cs_pin, 1);
|
||||
|
||||
/* pass chip-select pin to driver */
|
||||
devices[i].controller_data = (void *) cs_pin;
|
||||
}
|
||||
|
||||
spi_register_board_info(devices, nr_devices);
|
||||
|
||||
/* Configure SPI bus(es) */
|
||||
if (enable_spi0) {
|
||||
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
|
||||
at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
|
||||
at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
|
||||
|
||||
at91_clock_associate("spi0_clk", &at572d940hf_spi0_device.dev, "spi_clk");
|
||||
platform_device_register(&at572d940hf_spi0_device);
|
||||
}
|
||||
if (enable_spi1) {
|
||||
at91_set_A_periph(AT91_PIN_PC0, 0); /* SPI1_MISO */
|
||||
at91_set_A_periph(AT91_PIN_PC1, 0); /* SPI1_MOSI */
|
||||
at91_set_A_periph(AT91_PIN_PC2, 0); /* SPI1_SPCK */
|
||||
|
||||
at91_clock_associate("spi1_clk", &at572d940hf_spi1_device.dev, "spi_clk");
|
||||
platform_device_register(&at572d940hf_spi1_device);
|
||||
}
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Timer/Counter blocks
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifdef CONFIG_ATMEL_TCLIB
|
||||
|
||||
static struct resource tcb_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_TCB,
|
||||
.end = AT572D940HF_BASE_TCB + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_TC0,
|
||||
.end = AT572D940HF_ID_TC0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = AT572D940HF_ID_TC1,
|
||||
.end = AT572D940HF_ID_TC1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
.start = AT572D940HF_ID_TC2,
|
||||
.end = AT572D940HF_ID_TC2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_tcb_device = {
|
||||
.name = "atmel_tcb",
|
||||
.id = 0,
|
||||
.resource = tcb_resources,
|
||||
.num_resources = ARRAY_SIZE(tcb_resources),
|
||||
};
|
||||
|
||||
static void __init at91_add_device_tc(void)
|
||||
{
|
||||
/* this chip has a separate clock and irq for each TC channel */
|
||||
at91_clock_associate("tc0_clk", &at572d940hf_tcb_device.dev, "t0_clk");
|
||||
at91_clock_associate("tc1_clk", &at572d940hf_tcb_device.dev, "t1_clk");
|
||||
at91_clock_associate("tc2_clk", &at572d940hf_tcb_device.dev, "t2_clk");
|
||||
platform_device_register(&at572d940hf_tcb_device);
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_tc(void) { }
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* RTT
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static struct resource rtt_resources[] = {
|
||||
{
|
||||
.start = AT91_BASE_SYS + AT91_RTT,
|
||||
.end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device at572d940hf_rtt_device = {
|
||||
.name = "at91_rtt",
|
||||
.id = 0,
|
||||
.resource = rtt_resources,
|
||||
.num_resources = ARRAY_SIZE(rtt_resources),
|
||||
};
|
||||
|
||||
static void __init at91_add_device_rtt(void)
|
||||
{
|
||||
platform_device_register(&at572d940hf_rtt_device);
|
||||
}
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Watchdog
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
|
||||
static struct platform_device at572d940hf_wdt_device = {
|
||||
.name = "at91_wdt",
|
||||
.id = -1,
|
||||
.num_resources = 0,
|
||||
};
|
||||
|
||||
static void __init at91_add_device_watchdog(void)
|
||||
{
|
||||
platform_device_register(&at572d940hf_wdt_device);
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_watchdog(void) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* UART
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_SERIAL_ATMEL)
|
||||
static struct resource dbgu_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91_VA_BASE_SYS + AT91_DBGU,
|
||||
.end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91_ID_SYS,
|
||||
.end = AT91_ID_SYS,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data dbgu_data = {
|
||||
.use_dma_tx = 0,
|
||||
.use_dma_rx = 0, /* DBGU not capable of receive DMA */
|
||||
.regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
|
||||
};
|
||||
|
||||
static u64 dbgu_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct platform_device at572d940hf_dbgu_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &dbgu_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &dbgu_data,
|
||||
},
|
||||
.resource = dbgu_resources,
|
||||
.num_resources = ARRAY_SIZE(dbgu_resources),
|
||||
};
|
||||
|
||||
static inline void configure_dbgu_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
|
||||
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
|
||||
}
|
||||
|
||||
static struct resource uart0_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_US0,
|
||||
.end = AT572D940HF_BASE_US0 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_US0,
|
||||
.end = AT572D940HF_ID_US0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data uart0_data = {
|
||||
.use_dma_tx = 1,
|
||||
.use_dma_rx = 1,
|
||||
};
|
||||
|
||||
static u64 uart0_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct platform_device at572d940hf_uart0_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.dma_mask = &uart0_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &uart0_data,
|
||||
},
|
||||
.resource = uart0_resources,
|
||||
.num_resources = ARRAY_SIZE(uart0_resources),
|
||||
};
|
||||
|
||||
static inline void configure_usart0_pins(unsigned pins)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PA8, 1); /* TXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
|
||||
|
||||
if (pins & ATMEL_UART_RTS)
|
||||
at91_set_A_periph(AT91_PIN_PA10, 0); /* RTS0 */
|
||||
if (pins & ATMEL_UART_CTS)
|
||||
at91_set_A_periph(AT91_PIN_PA9, 0); /* CTS0 */
|
||||
}
|
||||
|
||||
static struct resource uart1_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_US1,
|
||||
.end = AT572D940HF_BASE_US1 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_US1,
|
||||
.end = AT572D940HF_ID_US1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data uart1_data = {
|
||||
.use_dma_tx = 1,
|
||||
.use_dma_rx = 1,
|
||||
};
|
||||
|
||||
static u64 uart1_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct platform_device at572d940hf_uart1_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.dma_mask = &uart1_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &uart1_data,
|
||||
},
|
||||
.resource = uart1_resources,
|
||||
.num_resources = ARRAY_SIZE(uart1_resources),
|
||||
};
|
||||
|
||||
static inline void configure_usart1_pins(unsigned pins)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PC10, 1); /* TXD1 */
|
||||
at91_set_A_periph(AT91_PIN_PC9 , 0); /* RXD1 */
|
||||
|
||||
if (pins & ATMEL_UART_RTS)
|
||||
at91_set_A_periph(AT91_PIN_PC12, 0); /* RTS1 */
|
||||
if (pins & ATMEL_UART_CTS)
|
||||
at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS1 */
|
||||
}
|
||||
|
||||
static struct resource uart2_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_BASE_US2,
|
||||
.end = AT572D940HF_BASE_US2 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT572D940HF_ID_US2,
|
||||
.end = AT572D940HF_ID_US2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data uart2_data = {
|
||||
.use_dma_tx = 1,
|
||||
.use_dma_rx = 1,
|
||||
};
|
||||
|
||||
static u64 uart2_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct platform_device at572d940hf_uart2_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 3,
|
||||
.dev = {
|
||||
.dma_mask = &uart2_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &uart2_data,
|
||||
},
|
||||
.resource = uart2_resources,
|
||||
.num_resources = ARRAY_SIZE(uart2_resources),
|
||||
};
|
||||
|
||||
static inline void configure_usart2_pins(unsigned pins)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PC15, 1); /* TXD2 */
|
||||
at91_set_A_periph(AT91_PIN_PC14, 0); /* RXD2 */
|
||||
|
||||
if (pins & ATMEL_UART_RTS)
|
||||
at91_set_A_periph(AT91_PIN_PC17, 0); /* RTS2 */
|
||||
if (pins & ATMEL_UART_CTS)
|
||||
at91_set_A_periph(AT91_PIN_PC16, 0); /* CTS2 */
|
||||
}
|
||||
|
||||
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
||||
struct platform_device *atmel_default_console_device; /* the serial console device */
|
||||
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
|
||||
switch (id) {
|
||||
case 0: /* DBGU */
|
||||
pdev = &at572d940hf_dbgu_device;
|
||||
configure_dbgu_pins();
|
||||
at91_clock_associate("mck", &pdev->dev, "usart");
|
||||
break;
|
||||
case AT572D940HF_ID_US0:
|
||||
pdev = &at572d940hf_uart0_device;
|
||||
configure_usart0_pins(pins);
|
||||
at91_clock_associate("usart0_clk", &pdev->dev, "usart");
|
||||
break;
|
||||
case AT572D940HF_ID_US1:
|
||||
pdev = &at572d940hf_uart1_device;
|
||||
configure_usart1_pins(pins);
|
||||
at91_clock_associate("usart1_clk", &pdev->dev, "usart");
|
||||
break;
|
||||
case AT572D940HF_ID_US2:
|
||||
pdev = &at572d940hf_uart2_device;
|
||||
configure_usart2_pins(pins);
|
||||
at91_clock_associate("usart2_clk", &pdev->dev, "usart");
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
pdev->id = portnr; /* update to mapped ID */
|
||||
|
||||
if (portnr < ATMEL_MAX_UART)
|
||||
at91_uarts[portnr] = pdev;
|
||||
}
|
||||
|
||||
void __init at91_set_serial_console(unsigned portnr)
|
||||
{
|
||||
if (portnr < ATMEL_MAX_UART)
|
||||
atmel_default_console_device = at91_uarts[portnr];
|
||||
}
|
||||
|
||||
void __init at91_add_device_serial(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ATMEL_MAX_UART; i++) {
|
||||
if (at91_uarts[i])
|
||||
platform_device_register(at91_uarts[i]);
|
||||
}
|
||||
|
||||
if (!atmel_default_console_device)
|
||||
printk(KERN_INFO "AT91: No default serial console defined.\n");
|
||||
}
|
||||
|
||||
#else
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||
void __init at91_set_serial_console(unsigned portnr) {}
|
||||
void __init at91_add_device_serial(void) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* mAgic
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifdef CONFIG_MAGICV
|
||||
static struct resource mAgic_resources[] = {
|
||||
{
|
||||
.start = AT91_MAGIC_PM_BASE,
|
||||
.end = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = AT91_MAGIC_DM_I_BASE,
|
||||
.end = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = AT91_MAGIC_DM_F_BASE,
|
||||
.end = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = AT91_MAGIC_DM_DB_BASE,
|
||||
.end = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = AT91_MAGIC_REGS_BASE,
|
||||
.end = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = AT91_MAGIC_EXTPAGE_BASE,
|
||||
.end = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = AT572D940HF_ID_MSIRQ0,
|
||||
.end = AT572D940HF_ID_MSIRQ0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = AT572D940HF_ID_MHALT,
|
||||
.end = AT572D940HF_ID_MHALT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = AT572D940HF_ID_MEXC,
|
||||
.end = AT572D940HF_ID_MEXC,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = AT572D940HF_ID_MEDMA,
|
||||
.end = AT572D940HF_ID_MEDMA,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device mAgic_device = {
|
||||
.name = "mAgic",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(mAgic_resources),
|
||||
.resource = mAgic_resources,
|
||||
};
|
||||
|
||||
void __init at91_add_device_mAgic(void)
|
||||
{
|
||||
platform_device_register(&mAgic_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_mAgic(void) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* These devices are always present and don't need any board-specific
|
||||
* setup.
|
||||
*/
|
||||
static int __init at91_add_standard_devices(void)
|
||||
{
|
||||
at91_add_device_rtt();
|
||||
at91_add_device_watchdog();
|
||||
at91_add_device_tc();
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(at91_add_standard_devices);
|
||||
|
|
@ -0,0 +1,328 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-at91/board-at572d940hf_ek.c
|
||||
*
|
||||
* Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
|
||||
* Copyright (C) 2005 SAN People
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/ds1305.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/at91sam9_smc.h>
|
||||
|
||||
#include "sam9_smc.h"
|
||||
#include "generic.h"
|
||||
|
||||
|
||||
static void __init eb_map_io(void)
|
||||
{
|
||||
/* Initialize processor: 12.500 MHz crystal */
|
||||
at572d940hf_initialize(12000000);
|
||||
|
||||
/* DBGU on ttyS0. (Rx & Tx only) */
|
||||
at91_register_uart(0, 0, 0);
|
||||
|
||||
/* USART0 on ttyS1. (Rx & Tx only) */
|
||||
at91_register_uart(AT572D940HF_ID_US0, 1, 0);
|
||||
|
||||
/* USART1 on ttyS2. (Rx & Tx only) */
|
||||
at91_register_uart(AT572D940HF_ID_US1, 2, 0);
|
||||
|
||||
/* USART2 on ttyS3. (Tx & Rx only */
|
||||
at91_register_uart(AT572D940HF_ID_US2, 3, 0);
|
||||
|
||||
/* set serial console to ttyS0 (ie, DBGU) */
|
||||
at91_set_serial_console(0);
|
||||
}
|
||||
|
||||
static void __init eb_init_irq(void)
|
||||
{
|
||||
at572d940hf_init_interrupts(NULL);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* USB Host Port
|
||||
*/
|
||||
static struct at91_usbh_data __initdata eb_usbh_data = {
|
||||
.ports = 2,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* USB Device Port
|
||||
*/
|
||||
static struct at91_udc_data __initdata eb_udc_data = {
|
||||
.vbus_pin = 0, /* no VBUS detection,UDC always on */
|
||||
.pullup_pin = 0, /* pull-up driven by UDC */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* MCI (SD/MMC)
|
||||
*/
|
||||
static struct at91_mmc_data __initdata eb_mmc_data = {
|
||||
.wire4 = 1,
|
||||
/* .det_pin = ... not connected */
|
||||
/* .wp_pin = ... not connected */
|
||||
/* .vcc_pin = ... not connected */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* MACB Ethernet device
|
||||
*/
|
||||
static struct at91_eth_data __initdata eb_eth_data = {
|
||||
.phy_irq_pin = AT91_PIN_PB25,
|
||||
.is_rmii = 1,
|
||||
};
|
||||
|
||||
/*
|
||||
* NOR flash
|
||||
*/
|
||||
|
||||
static struct mtd_partition eb_nor_partitions[] = {
|
||||
{
|
||||
.name = "Raw Environment",
|
||||
.offset = 0,
|
||||
.size = SZ_4M,
|
||||
.mask_flags = 0,
|
||||
},
|
||||
{
|
||||
.name = "OS FS",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = 3 * SZ_1M,
|
||||
.mask_flags = 0,
|
||||
},
|
||||
{
|
||||
.name = "APP FS",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.mask_flags = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static void nor_flash_set_vpp(struct map_info* mi, int i) {
|
||||
};
|
||||
|
||||
static struct physmap_flash_data nor_flash_data = {
|
||||
.width = 4,
|
||||
.parts = eb_nor_partitions,
|
||||
.nr_parts = ARRAY_SIZE(eb_nor_partitions),
|
||||
.set_vpp = nor_flash_set_vpp,
|
||||
};
|
||||
|
||||
static struct resource nor_flash_resources[] = {
|
||||
{
|
||||
.start = AT91_CHIPSELECT_0,
|
||||
.end = AT91_CHIPSELECT_0 + SZ_16M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device nor_flash = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &nor_flash_data,
|
||||
},
|
||||
.resource = nor_flash_resources,
|
||||
.num_resources = ARRAY_SIZE(nor_flash_resources),
|
||||
};
|
||||
|
||||
static struct sam9_smc_config __initdata eb_nor_smc_config = {
|
||||
.ncs_read_setup = 1,
|
||||
.nrd_setup = 1,
|
||||
.ncs_write_setup = 1,
|
||||
.nwe_setup = 1,
|
||||
|
||||
.ncs_read_pulse = 7,
|
||||
.nrd_pulse = 7,
|
||||
.ncs_write_pulse = 7,
|
||||
.nwe_pulse = 7,
|
||||
|
||||
.read_cycle = 9,
|
||||
.write_cycle = 9,
|
||||
|
||||
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_32,
|
||||
.tdf_cycles = 1,
|
||||
};
|
||||
|
||||
static void __init eb_add_device_nor(void)
|
||||
{
|
||||
/* configure chip-select 0 (NOR) */
|
||||
sam9_smc_configure(0, &eb_nor_smc_config);
|
||||
platform_device_register(&nor_flash);
|
||||
}
|
||||
|
||||
/*
|
||||
* NAND flash
|
||||
*/
|
||||
static struct mtd_partition __initdata eb_nand_partition[] = {
|
||||
{
|
||||
.name = "Partition 1",
|
||||
.offset = 0,
|
||||
.size = SZ_16M,
|
||||
},
|
||||
{
|
||||
.name = "Partition 2",
|
||||
.offset = MTDPART_OFS_NXTBLK,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
}
|
||||
};
|
||||
|
||||
static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
|
||||
{
|
||||
*num_partitions = ARRAY_SIZE(eb_nand_partition);
|
||||
return eb_nand_partition;
|
||||
}
|
||||
|
||||
static struct atmel_nand_data __initdata eb_nand_data = {
|
||||
.ale = 22,
|
||||
.cle = 21,
|
||||
/* .det_pin = ... not connected */
|
||||
/* .rdy_pin = AT91_PIN_PC16, */
|
||||
.enable_pin = AT91_PIN_PA15,
|
||||
.partition_info = nand_partitions,
|
||||
#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
|
||||
.bus_width_16 = 1,
|
||||
#else
|
||||
.bus_width_16 = 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct sam9_smc_config __initdata eb_nand_smc_config = {
|
||||
.ncs_read_setup = 0,
|
||||
.nrd_setup = 0,
|
||||
.ncs_write_setup = 1,
|
||||
.nwe_setup = 1,
|
||||
|
||||
.ncs_read_pulse = 3,
|
||||
.nrd_pulse = 3,
|
||||
.ncs_write_pulse = 3,
|
||||
.nwe_pulse = 3,
|
||||
|
||||
.read_cycle = 5,
|
||||
.write_cycle = 5,
|
||||
|
||||
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
|
||||
.tdf_cycles = 12,
|
||||
};
|
||||
|
||||
static void __init eb_add_device_nand(void)
|
||||
{
|
||||
/* setup bus-width (8 or 16) */
|
||||
if (eb_nand_data.bus_width_16)
|
||||
eb_nand_smc_config.mode |= AT91_SMC_DBW_16;
|
||||
else
|
||||
eb_nand_smc_config.mode |= AT91_SMC_DBW_8;
|
||||
|
||||
/* configure chip-select 3 (NAND) */
|
||||
sam9_smc_configure(3, &eb_nand_smc_config);
|
||||
|
||||
at91_add_device_nand(&eb_nand_data);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* SPI devices
|
||||
*/
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = AT572D940HF_ID_IRQ1,
|
||||
.end = AT572D940HF_ID_IRQ1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct ds1305_platform_data ds1306_data = {
|
||||
.is_ds1306 = true,
|
||||
.en_1hz = false,
|
||||
};
|
||||
|
||||
static struct spi_board_info eb_spi_devices[] = {
|
||||
{ /* RTC Dallas DS1306 */
|
||||
.modalias = "rtc-ds1305",
|
||||
.chip_select = 3,
|
||||
.mode = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA,
|
||||
.max_speed_hz = 500000,
|
||||
.bus_num = 0,
|
||||
.irq = AT572D940HF_ID_IRQ1,
|
||||
.platform_data = (void *) &ds1306_data,
|
||||
},
|
||||
#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
|
||||
{ /* Dataflash card */
|
||||
.modalias = "mtd_dataflash",
|
||||
.chip_select = 0,
|
||||
.max_speed_hz = 15 * 1000 * 1000,
|
||||
.bus_num = 0,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static void __init eb_board_init(void)
|
||||
{
|
||||
/* Serial */
|
||||
at91_add_device_serial();
|
||||
/* USB Host */
|
||||
at91_add_device_usbh(&eb_usbh_data);
|
||||
/* USB Device */
|
||||
at91_add_device_udc(&eb_udc_data);
|
||||
/* I2C */
|
||||
at91_add_device_i2c(NULL, 0);
|
||||
/* NOR */
|
||||
eb_add_device_nor();
|
||||
/* NAND */
|
||||
eb_add_device_nand();
|
||||
/* SPI */
|
||||
at91_add_device_spi(eb_spi_devices, ARRAY_SIZE(eb_spi_devices));
|
||||
/* MMC */
|
||||
at91_add_device_mmc(0, &eb_mmc_data);
|
||||
/* Ethernet */
|
||||
at91_add_device_eth(&eb_eth_data);
|
||||
/* mAgic */
|
||||
at91_add_device_mAgic();
|
||||
}
|
||||
|
||||
MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB")
|
||||
/* Maintainer: Atmel <costa.antonior@gmail.com> */
|
||||
.phys_io = AT91_BASE_SYS,
|
||||
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
|
||||
.boot_params = AT91_SDRAM_BASE + 0x100,
|
||||
.timer = &at91sam926x_timer,
|
||||
.map_io = eb_map_io,
|
||||
.init_irq = eb_init_irq,
|
||||
.init_machine = eb_board_init,
|
||||
MACHINE_END
|
||||
|
|
@ -29,6 +29,7 @@
|
|||
#include <mach/cpu.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "generic.h"
|
||||
|
||||
|
||||
/*
|
||||
|
|
@ -628,7 +629,7 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
|
|||
at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
|
||||
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
|
||||
cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
|
||||
cpu_is_at91sam9g10()) {
|
||||
cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
|
||||
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
|
||||
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
|
||||
} else if (cpu_is_at91cap9()) {
|
||||
|
|
@ -711,12 +712,13 @@ int __init at91_clock_init(unsigned long main_clock)
|
|||
/*
|
||||
* USB HS clock init
|
||||
*/
|
||||
if (cpu_has_utmi())
|
||||
if (cpu_has_utmi()) {
|
||||
/*
|
||||
* multiplier is hard-wired to 40
|
||||
* (obtain the USB High Speed 480 MHz when input is 12 MHz)
|
||||
*/
|
||||
utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
|
||||
}
|
||||
|
||||
/*
|
||||
* USB FS clock init
|
||||
|
|
@ -746,7 +748,7 @@ int __init at91_clock_init(unsigned long main_clock)
|
|||
mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
|
||||
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||
} else {
|
||||
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||
}
|
||||
|
||||
/* Register the PMC's standard clocks */
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ struct clk {
|
|||
struct clk *parent;
|
||||
u32 pmc_mask;
|
||||
void (*mode)(struct clk *, int);
|
||||
unsigned id:2; /* PCK0..3, or 32k/main/a/b */
|
||||
unsigned id:3; /* PCK0..4, or 32k/main/a/b */
|
||||
unsigned type; /* clock type */
|
||||
u16 users;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ extern void __init at91sam9rl_initialize(unsigned long main_clock);
|
|||
extern void __init at91sam9g45_initialize(unsigned long main_clock);
|
||||
extern void __init at91x40_initialize(unsigned long main_clock);
|
||||
extern void __init at91cap9_initialize(unsigned long main_clock);
|
||||
extern void __init at572d940hf_initialize(unsigned long main_clock);
|
||||
|
||||
/* Interrupts */
|
||||
extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
|
||||
|
|
@ -27,6 +28,7 @@ extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
|
|||
extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91x40_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91cap9_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at572d940hf_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91_aic_init(unsigned int priority[]);
|
||||
|
||||
/* Timer */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* include/mach/at572d940hf.h
|
||||
*
|
||||
* Antonio R. Costa <costa.antonior@gmail.com>
|
||||
* Copyright (C) 2008 Atmel
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef AT572D940HF_H
|
||||
#define AT572D940HF_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Peripherals */
|
||||
#define AT572D940HF_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT572D940HF_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT572D940HF_ID_PIOC 4 /* Parallel IO Controller C */
|
||||
#define AT572D940HF_ID_EMAC 5 /* MACB ethernet controller */
|
||||
#define AT572D940HF_ID_US0 6 /* USART 0 */
|
||||
#define AT572D940HF_ID_US1 7 /* USART 1 */
|
||||
#define AT572D940HF_ID_US2 8 /* USART 2 */
|
||||
#define AT572D940HF_ID_MCI 9 /* Multimedia Card Interface */
|
||||
#define AT572D940HF_ID_UDP 10 /* USB Device Port */
|
||||
#define AT572D940HF_ID_TWI0 11 /* Two-Wire Interface 0 */
|
||||
#define AT572D940HF_ID_SPI0 12 /* Serial Peripheral Interface 0 */
|
||||
#define AT572D940HF_ID_SPI1 13 /* Serial Peripheral Interface 1 */
|
||||
#define AT572D940HF_ID_SSC0 14 /* Serial Synchronous Controller 0 */
|
||||
#define AT572D940HF_ID_SSC1 15 /* Serial Synchronous Controller 1 */
|
||||
#define AT572D940HF_ID_SSC2 16 /* Serial Synchronous Controller 2 */
|
||||
#define AT572D940HF_ID_TC0 17 /* Timer Counter 0 */
|
||||
#define AT572D940HF_ID_TC1 18 /* Timer Counter 1 */
|
||||
#define AT572D940HF_ID_TC2 19 /* Timer Counter 2 */
|
||||
#define AT572D940HF_ID_UHP 20 /* USB Host port */
|
||||
#define AT572D940HF_ID_SSC3 21 /* Serial Synchronous Controller 3 */
|
||||
#define AT572D940HF_ID_TWI1 22 /* Two-Wire Interface 1 */
|
||||
#define AT572D940HF_ID_CAN0 23 /* CAN Controller 0 */
|
||||
#define AT572D940HF_ID_CAN1 24 /* CAN Controller 1 */
|
||||
#define AT572D940HF_ID_MHALT 25 /* mAgicV HALT line */
|
||||
#define AT572D940HF_ID_MSIRQ0 26 /* mAgicV SIRQ0 line */
|
||||
#define AT572D940HF_ID_MEXC 27 /* mAgicV exception line */
|
||||
#define AT572D940HF_ID_MEDMA 28 /* mAgicV end of DMA line */
|
||||
#define AT572D940HF_ID_IRQ0 29 /* External Interrupt Source (IRQ0) */
|
||||
#define AT572D940HF_ID_IRQ1 30 /* External Interrupt Source (IRQ1) */
|
||||
#define AT572D940HF_ID_IRQ2 31 /* External Interrupt Source (IRQ2) */
|
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT572D940HF_BASE_TCB 0xfffa0000
|
||||
#define AT572D940HF_BASE_TC0 0xfffa0000
|
||||
#define AT572D940HF_BASE_TC1 0xfffa0040
|
||||
#define AT572D940HF_BASE_TC2 0xfffa0080
|
||||
#define AT572D940HF_BASE_UDP 0xfffa4000
|
||||
#define AT572D940HF_BASE_MCI 0xfffa8000
|
||||
#define AT572D940HF_BASE_TWI0 0xfffac000
|
||||
#define AT572D940HF_BASE_US0 0xfffb0000
|
||||
#define AT572D940HF_BASE_US1 0xfffb4000
|
||||
#define AT572D940HF_BASE_US2 0xfffb8000
|
||||
#define AT572D940HF_BASE_SSC0 0xfffbc000
|
||||
#define AT572D940HF_BASE_SSC1 0xfffc0000
|
||||
#define AT572D940HF_BASE_SSC2 0xfffc4000
|
||||
#define AT572D940HF_BASE_SPI0 0xfffc8000
|
||||
#define AT572D940HF_BASE_SPI1 0xfffcc000
|
||||
#define AT572D940HF_BASE_SSC3 0xfffd0000
|
||||
#define AT572D940HF_BASE_TWI1 0xfffd4000
|
||||
#define AT572D940HF_BASE_EMAC 0xfffd8000
|
||||
#define AT572D940HF_BASE_CAN0 0xfffdc000
|
||||
#define AT572D940HF_BASE_CAN1 0xfffe0000
|
||||
#define AT91_BASE_SYS 0xffffea00
|
||||
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
|
||||
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
|
||||
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
|
||||
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
|
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
|
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91_USART0 AT572D940HF_ID_US0
|
||||
#define AT91_USART1 AT572D940HF_ID_US1
|
||||
#define AT91_USART2 AT572D940HF_ID_US2
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT572D940HF_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT572D940HF_SRAM_SIZE (48 * SZ_1K) /* Internal SRAM size (48Kb) */
|
||||
|
||||
#define AT572D940HF_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT572D940HF_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT572D940HF_UHP_BASE 0x00500000 /* USB Host controller */
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* include/mach//at572d940hf_matrix.h
|
||||
*
|
||||
* Antonio R. Costa <costa.antonior@gmail.com>
|
||||
* Copyright (C) 2008 Atmel
|
||||
*
|
||||
* Copyright (C) 2005 SAN People
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef AT572D940HF_MATRIX_H
|
||||
#define AT572D940HF_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
||||
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0x7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_SFR0 (AT91_MATRIX + 0x110) /* Special Function Register 0 */
|
||||
#define AT91_MATRIX_SFR1 (AT91_MATRIX + 0x114) /* Special Function Register 1 */
|
||||
#define AT91_MATRIX_SFR2 (AT91_MATRIX + 0x118) /* Special Function Register 2 */
|
||||
#define AT91_MATRIX_SFR3 (AT91_MATRIX + 0x11C) /* Special Function Register 3 */
|
||||
#define AT91_MATRIX_SFR4 (AT91_MATRIX + 0x120) /* Special Function Register 4 */
|
||||
#define AT91_MATRIX_SFR5 (AT91_MATRIX + 0x124) /* Special Function Register 5 */
|
||||
#define AT91_MATRIX_SFR6 (AT91_MATRIX + 0x128) /* Special Function Register 6 */
|
||||
#define AT91_MATRIX_SFR7 (AT91_MATRIX + 0x12C) /* Special Function Register 7 */
|
||||
#define AT91_MATRIX_SFR8 (AT91_MATRIX + 0x130) /* Special Function Register 8 */
|
||||
#define AT91_MATRIX_SFR9 (AT91_MATRIX + 0x134) /* Special Function Register 9 */
|
||||
#define AT91_MATRIX_SFR10 (AT91_MATRIX + 0x138) /* Special Function Register 10 */
|
||||
#define AT91_MATRIX_SFR11 (AT91_MATRIX + 0x13C) /* Special Function Register 11 */
|
||||
#define AT91_MATRIX_SFR12 (AT91_MATRIX + 0x140) /* Special Function Register 12 */
|
||||
#define AT91_MATRIX_SFR13 (AT91_MATRIX + 0x144) /* Special Function Register 13 */
|
||||
#define AT91_MATRIX_SFR14 (AT91_MATRIX + 0x148) /* Special Function Register 14 */
|
||||
#define AT91_MATRIX_SFR15 (AT91_MATRIX + 0x14C) /* Special Function Register 15 */
|
||||
|
||||
|
||||
/*
|
||||
* The following registers / bits are not defined in the Datasheet (Revision A)
|
||||
*/
|
||||
|
||||
#define AT91_MATRIX_TCR (AT91_MATRIX + 0x100) /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_ITCM_64 (7 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
#define AT91_MATRIX_DTCM_64 (7 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
|
||||
#endif
|
||||
|
|
@ -32,6 +32,7 @@
|
|||
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
|
||||
#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
|
||||
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
|
||||
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
|
||||
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ struct at91_eth_data {
|
|||
extern void __init at91_add_device_eth(struct at91_eth_data *data);
|
||||
|
||||
#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
|
||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
|| defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF)
|
||||
#define eth_platform_data at91_eth_data
|
||||
#endif
|
||||
|
||||
|
|
@ -205,6 +205,9 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
|
|||
extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
|
||||
extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
|
||||
|
||||
/* AT572D940HF DSP */
|
||||
extern void __init at91_add_device_mAgic(void);
|
||||
|
||||
/* FIXME: this needs a better location, but gets stuff building again */
|
||||
extern int at91_suspend_entering_slow_clock(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -33,6 +33,8 @@
|
|||
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
|
||||
#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
|
||||
|
||||
#define ARCH_ID_AT572D940HF 0x0e0303e0
|
||||
|
||||
#define ARCH_ID_AT91M40800 0x14080044
|
||||
#define ARCH_ID_AT91R40807 0x44080746
|
||||
#define ARCH_ID_AT91M40807 0x14080745
|
||||
|
|
@ -141,6 +143,12 @@ static inline unsigned long at91cap9_rev_identify(void)
|
|||
#define cpu_is_at91cap9_revC() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT572D940HF
|
||||
#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
|
||||
#else
|
||||
#define cpu_is_at572d940hf() (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
||||
* definitions may reduce clutter in common drivers.
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/at91_dbgu.h>
|
||||
|
||||
.macro addruart,rx
|
||||
.macro addruart, rx, tmp
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ MMU enabled?
|
||||
ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@
|
|||
#include <mach/at91cap9.h>
|
||||
#elif defined(CONFIG_ARCH_AT91X40)
|
||||
#include <mach/at91x40.h>
|
||||
#elif defined(CONFIG_ARCH_AT572D940HF)
|
||||
#include <mach/at572d940hf.h>
|
||||
#else
|
||||
#error "Unsupported AT91 processor"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -82,6 +82,11 @@
|
|||
#define AT91X40_MASTER_CLOCK 40000000
|
||||
#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK)
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT572D940HF)
|
||||
|
||||
#define AT572D940HF_MASTER_CLOCK 80000000
|
||||
#define CLOCK_TICK_RATE (AT572D940HF_MASTER_CLOCK/16)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -142,8 +142,7 @@ void __init bcmring_amba_init(void)
|
|||
|
||||
chipcHw_busInterfaceClockEnable(bus_clock);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lookups); i++)
|
||||
clkdev_add(&lookups[i]);
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
|
||||
struct amba_device *d = amba_devs[i];
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
|
||||
#include <asm/hardware/clps7111.h>
|
||||
|
||||
.macro addruart,rx
|
||||
.macro addruart, rx, tmp
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ MMU enabled?
|
||||
moveq \rx, #CLPS7111_PHYS_BASE
|
||||
|
|
|
|||
|
|
@ -91,10 +91,14 @@ config MACH_DAVINCI_DM6467_EVM
|
|||
bool "TI DM6467 EVM"
|
||||
default ARCH_DAVINCI_DM646x
|
||||
depends on ARCH_DAVINCI_DM646x
|
||||
select MACH_DAVINCI_DM6467TEVM
|
||||
help
|
||||
Configure this option to specify the whether the board used
|
||||
for development is a DM6467 EVM
|
||||
|
||||
config MACH_DAVINCI_DM6467TEVM
|
||||
bool
|
||||
|
||||
config MACH_DAVINCI_DM365_EVM
|
||||
bool "TI DM365 EVM"
|
||||
default ARCH_DAVINCI_DM365
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
|
|||
obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
|
||||
obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
|
||||
obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
|
||||
obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o
|
||||
obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o
|
||||
obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
|
||||
obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
|
||||
obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
|
||||
|
|
@ -34,3 +34,4 @@ obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
|
|||
# Power Management
|
||||
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
|
||||
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
||||
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@ static __init void da830_evm_usb_init(void)
|
|||
* Set up USB clock/mode in the CFGCHIP2 register.
|
||||
* FYI: CFGCHIP2 is 0x0000ef00 initially.
|
||||
*/
|
||||
cfgchip2 = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG));
|
||||
cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
|
||||
|
||||
/* USB2.0 PHY reference clock is 24 MHz */
|
||||
cfgchip2 &= ~CFGCHIP2_REFFREQ;
|
||||
|
|
@ -139,7 +139,7 @@ static __init void da830_evm_usb_init(void)
|
|||
cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
|
||||
#endif
|
||||
|
||||
__raw_writel(cfgchip2, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG));
|
||||
__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
|
||||
|
||||
/* USB_REFCLKIN is not used. */
|
||||
ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
|
||||
|
|
|
|||
|
|
@ -46,8 +46,20 @@
|
|||
|
||||
static struct mtd_partition da850_evm_norflash_partition[] = {
|
||||
{
|
||||
.name = "NOR filesystem",
|
||||
.name = "bootloaders + env",
|
||||
.offset = 0,
|
||||
.size = SZ_512K,
|
||||
.mask_flags = MTD_WRITEABLE,
|
||||
},
|
||||
{
|
||||
.name = "kernel",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = SZ_2M,
|
||||
.mask_flags = 0,
|
||||
},
|
||||
{
|
||||
.name = "filesystem",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.mask_flags = 0,
|
||||
},
|
||||
|
|
@ -77,6 +89,18 @@ static struct platform_device da850_evm_norflash_device = {
|
|||
.resource = da850_evm_norflash_resource,
|
||||
};
|
||||
|
||||
static struct davinci_pm_config da850_pm_pdata = {
|
||||
.sleepcount = 128,
|
||||
};
|
||||
|
||||
static struct platform_device da850_pm_device = {
|
||||
.name = "pm-davinci",
|
||||
.dev = {
|
||||
.platform_data = &da850_pm_pdata,
|
||||
},
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
|
||||
* (128K blocks). It may be used instead of the (default) SPI flash
|
||||
* to boot, using TI's tools to install the secondary boot loader
|
||||
|
|
@ -119,6 +143,7 @@ static struct davinci_nand_pdata da850_evm_nandflash_data = {
|
|||
.parts = da850_evm_nandflash_partition,
|
||||
.nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.ecc_bits = 4,
|
||||
.options = NAND_USE_FLASH_BBT,
|
||||
};
|
||||
|
||||
|
|
@ -537,7 +562,7 @@ static int __init da850_evm_config_emac(void)
|
|||
if (!machine_is_davinci_da850_evm())
|
||||
return 0;
|
||||
|
||||
cfg_chip3_base = DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG);
|
||||
cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
|
||||
|
||||
val = __raw_readl(cfg_chip3_base);
|
||||
|
||||
|
|
@ -696,6 +721,11 @@ static __init void da850_evm_init(void)
|
|||
if (ret)
|
||||
pr_warning("da850_evm_init: cpuidle registration failed: %d\n",
|
||||
ret);
|
||||
|
||||
ret = da850_register_pm(&da850_pm_device);
|
||||
if (ret)
|
||||
pr_warning("da850_evm_init: suspend registration failed: %d\n",
|
||||
ret);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SERIAL_8250_CONSOLE
|
||||
|
|
|
|||
|
|
@ -111,6 +111,8 @@ static struct platform_device davinci_nand_device = {
|
|||
static struct davinci_i2c_platform_data i2c_pdata = {
|
||||
.bus_freq = 400 /* kHz */,
|
||||
.bus_delay = 0 /* usec */,
|
||||
.sda_pin = 15,
|
||||
.scl_pin = 14,
|
||||
};
|
||||
|
||||
static struct snd_platform_data dm355_evm_snd_data;
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/eeprom.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
|
@ -571,6 +573,24 @@ static void __init dm365_evm_map_io(void)
|
|||
dm365_init();
|
||||
}
|
||||
|
||||
static struct spi_eeprom at25640 = {
|
||||
.byte_len = SZ_64K / 8,
|
||||
.name = "at25640",
|
||||
.page_size = 32,
|
||||
.flags = EE_ADDR2,
|
||||
};
|
||||
|
||||
static struct spi_board_info dm365_evm_spi_info[] __initconst = {
|
||||
{
|
||||
.modalias = "at25",
|
||||
.platform_data = &at25640,
|
||||
.max_speed_hz = 10 * 1000 * 1000,
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.mode = SPI_MODE_0,
|
||||
},
|
||||
};
|
||||
|
||||
static __init void dm365_evm_init(void)
|
||||
{
|
||||
evm_init_i2c();
|
||||
|
|
@ -587,6 +607,9 @@ static __init void dm365_evm_init(void)
|
|||
dm365_init_asp(&dm365_evm_snd_data);
|
||||
dm365_init_rtc();
|
||||
dm365_init_ks(&dm365evm_ks_data);
|
||||
|
||||
dm365_init_spi0(BIT(0), dm365_evm_spi_info,
|
||||
ARRAY_SIZE(dm365_evm_spi_info));
|
||||
}
|
||||
|
||||
static __init void dm365_evm_irq_init(void)
|
||||
|
|
|
|||
|
|
@ -629,6 +629,8 @@ static struct i2c_board_info __initdata i2c_info[] = {
|
|||
static struct davinci_i2c_platform_data i2c_pdata = {
|
||||
.bus_freq = 20 /* kHz */,
|
||||
.bus_delay = 100 /* usec */,
|
||||
.sda_pin = 44,
|
||||
.scl_pin = 43,
|
||||
};
|
||||
|
||||
static void __init evm_init_i2c(void)
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
|
@ -39,54 +40,13 @@
|
|||
#include <mach/serial.h>
|
||||
#include <mach/i2c.h>
|
||||
#include <mach/nand.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/cdce949.h>
|
||||
|
||||
#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
|
||||
defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
|
||||
#define HAS_ATA 1
|
||||
#else
|
||||
#define HAS_ATA 0
|
||||
#endif
|
||||
|
||||
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
|
||||
#include "clock.h"
|
||||
|
||||
#define NAND_BLOCK_SIZE SZ_128K
|
||||
|
||||
/* CPLD Register 0 bits to control ATA */
|
||||
#define DM646X_EVM_ATA_RST BIT(0)
|
||||
#define DM646X_EVM_ATA_PWD BIT(1)
|
||||
|
||||
#define DM646X_EVM_PHY_MASK (0x2)
|
||||
#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
|
||||
|
||||
#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
|
||||
#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
|
||||
#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
|
||||
#define VCH2CLK_SYSCLK8 (BIT(9))
|
||||
#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
|
||||
#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
|
||||
#define VCH3CLK_SYSCLK8 (BIT(13))
|
||||
#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
|
||||
|
||||
#define VIDCH2CLK (BIT(10))
|
||||
#define VIDCH3CLK (BIT(11))
|
||||
#define VIDCH1CLK (BIT(4))
|
||||
#define TVP7002_INPUT (BIT(4))
|
||||
#define TVP5147_INPUT (~BIT(4))
|
||||
#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
|
||||
#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
|
||||
#define TVP5147_CH0 "tvp514x-0"
|
||||
#define TVP5147_CH1 "tvp514x-1"
|
||||
|
||||
static void __iomem *vpif_vidclkctl_reg;
|
||||
static void __iomem *vpif_vsclkdis_reg;
|
||||
/* spin lock for updating above registers */
|
||||
static spinlock_t vpif_reg_lock;
|
||||
|
||||
static struct davinci_uart_config uart_config __initdata = {
|
||||
.enabled_uarts = (1 << 0),
|
||||
};
|
||||
|
||||
/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
|
||||
* and U-Boot environment this avoids dependency on any particular combination
|
||||
* of UBL, U-Boot or flashing tools etc.
|
||||
|
|
@ -120,6 +80,9 @@ static struct davinci_nand_pdata davinci_nand_data = {
|
|||
.options = 0,
|
||||
};
|
||||
|
||||
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
|
||||
|
||||
static struct resource davinci_nand_resources[] = {
|
||||
{
|
||||
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
|
||||
|
|
@ -144,6 +107,17 @@ static struct platform_device davinci_nand_device = {
|
|||
},
|
||||
};
|
||||
|
||||
#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
|
||||
defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
|
||||
#define HAS_ATA 1
|
||||
#else
|
||||
#define HAS_ATA 0
|
||||
#endif
|
||||
|
||||
/* CPLD Register 0 bits to control ATA */
|
||||
#define DM646X_EVM_ATA_RST BIT(0)
|
||||
#define DM646X_EVM_ATA_PWD BIT(1)
|
||||
|
||||
/* CPLD Register 0 Client: used for I/O Control */
|
||||
static int cpld_reg0_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
|
|
@ -417,6 +391,9 @@ static struct i2c_board_info __initdata i2c_info[] = {
|
|||
{
|
||||
I2C_BOARD_INFO("cpld_video", 0x3b),
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("cdce949", 0x6c),
|
||||
},
|
||||
};
|
||||
|
||||
static struct davinci_i2c_platform_data i2c_pdata = {
|
||||
|
|
@ -424,6 +401,30 @@ static struct davinci_i2c_platform_data i2c_pdata = {
|
|||
.bus_delay = 0 /* usec */,
|
||||
};
|
||||
|
||||
#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
|
||||
#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
|
||||
#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
|
||||
#define VCH2CLK_SYSCLK8 (BIT(9))
|
||||
#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
|
||||
#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
|
||||
#define VCH3CLK_SYSCLK8 (BIT(13))
|
||||
#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
|
||||
|
||||
#define VIDCH2CLK (BIT(10))
|
||||
#define VIDCH3CLK (BIT(11))
|
||||
#define VIDCH1CLK (BIT(4))
|
||||
#define TVP7002_INPUT (BIT(4))
|
||||
#define TVP5147_INPUT (~BIT(4))
|
||||
#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
|
||||
#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
|
||||
#define TVP5147_CH0 "tvp514x-0"
|
||||
#define TVP5147_CH1 "tvp514x-1"
|
||||
|
||||
static void __iomem *vpif_vidclkctl_reg;
|
||||
static void __iomem *vpif_vsclkdis_reg;
|
||||
/* spin lock for updating above registers */
|
||||
static spinlock_t vpif_reg_lock;
|
||||
|
||||
static int set_vpif_clock(int mux_mode, int hd)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
|
@ -685,11 +686,44 @@ static void __init evm_init_i2c(void)
|
|||
evm_init_video();
|
||||
}
|
||||
|
||||
#define CDCE949_XIN_RATE 27000000
|
||||
|
||||
/* CDCE949 support - "lpsc" field is overridden to work as clock number */
|
||||
static struct clk cdce_clk_in = {
|
||||
.name = "cdce_xin",
|
||||
.rate = CDCE949_XIN_RATE,
|
||||
};
|
||||
|
||||
static struct clk_lookup cdce_clks[] = {
|
||||
CLK(NULL, "xin", &cdce_clk_in),
|
||||
CLK(NULL, NULL, NULL),
|
||||
};
|
||||
|
||||
static void __init cdce_clk_init(void)
|
||||
{
|
||||
struct clk_lookup *c;
|
||||
struct clk *clk;
|
||||
|
||||
for (c = cdce_clks; c->clk; c++) {
|
||||
clk = c->clk;
|
||||
clkdev_add(c);
|
||||
clk_register(clk);
|
||||
}
|
||||
}
|
||||
|
||||
static void __init davinci_map_io(void)
|
||||
{
|
||||
dm646x_init();
|
||||
cdce_clk_init();
|
||||
}
|
||||
|
||||
static struct davinci_uart_config uart_config __initdata = {
|
||||
.enabled_uarts = (1 << 0),
|
||||
};
|
||||
|
||||
#define DM646X_EVM_PHY_MASK (0x2)
|
||||
#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
|
||||
|
||||
static __init void evm_init(void)
|
||||
{
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
|
|
@ -713,6 +747,17 @@ static __init void davinci_dm646x_evm_irq_init(void)
|
|||
davinci_irq_init();
|
||||
}
|
||||
|
||||
#define DM646X_EVM_REF_FREQ 27000000
|
||||
#define DM6467T_EVM_REF_FREQ 33000000
|
||||
|
||||
void __init dm646x_board_setup_refclk(struct clk *clk)
|
||||
{
|
||||
if (machine_is_davinci_dm6467tevm())
|
||||
clk->rate = DM6467T_EVM_REF_FREQ;
|
||||
else
|
||||
clk->rate = DM646X_EVM_REF_FREQ;
|
||||
}
|
||||
|
||||
MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
|
||||
.phys_io = IO_PHYS,
|
||||
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
|
||||
|
|
@ -723,3 +768,13 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
|
|||
.init_machine = evm_init,
|
||||
MACHINE_END
|
||||
|
||||
MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
|
||||
.phys_io = IO_PHYS,
|
||||
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
|
||||
.boot_params = (0x80000100),
|
||||
.map_io = davinci_map_io,
|
||||
.init_irq = davinci_dm646x_evm_irq_init,
|
||||
.timer = &davinci_timer,
|
||||
.init_machine = evm_init,
|
||||
MACHINE_END
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,293 @@
|
|||
/*
|
||||
* TI CDCE949 clock synthesizer driver
|
||||
*
|
||||
* Note: This implementation assumes an input of 27MHz to the CDCE.
|
||||
* This is by no means constrained by CDCE hardware although the datasheet
|
||||
* does use this as an example for all illustrations and more importantly:
|
||||
* that is the crystal input on boards it is currently used on.
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/i2c.h>
|
||||
|
||||
#include <mach/clock.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
static struct i2c_client *cdce_i2c_client;
|
||||
static DEFINE_MUTEX(cdce_mutex);
|
||||
|
||||
/* CDCE register descriptor */
|
||||
struct cdce_reg {
|
||||
u8 addr;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
/* Per-Output (Y1, Y2 etc.) frequency descriptor */
|
||||
struct cdce_freq {
|
||||
/* Frequency in KHz */
|
||||
unsigned long frequency;
|
||||
/*
|
||||
* List of registers to program to obtain a particular frequency.
|
||||
* 0x0 in register address and value is the end of list marker.
|
||||
*/
|
||||
struct cdce_reg *reglist;
|
||||
};
|
||||
|
||||
#define CDCE_FREQ_TABLE_ENTRY(line, out) \
|
||||
{ \
|
||||
.reglist = cdce_y ##line## _ ##out, \
|
||||
.frequency = out, \
|
||||
}
|
||||
|
||||
/* List of CDCE outputs */
|
||||
struct cdce_output {
|
||||
/* List of frequencies on this output */
|
||||
struct cdce_freq *freq_table;
|
||||
/* Number of possible frequencies */
|
||||
int size;
|
||||
};
|
||||
|
||||
/*
|
||||
* Finding out the values to program into CDCE949 registers for a particular
|
||||
* frequency output is not a simple calculation. Have a look at the datasheet
|
||||
* for the details. There is desktop software available to help users with
|
||||
* the calculations. Here, we just depend on the output of that software
|
||||
* (or hand calculations) instead trying to runtime calculate the register
|
||||
* values and inflicting misery on ourselves.
|
||||
*/
|
||||
static struct cdce_reg cdce_y1_148500[] = {
|
||||
{ 0x13, 0x00 },
|
||||
/* program PLL1_0 multiplier */
|
||||
{ 0x18, 0xaf },
|
||||
{ 0x19, 0x50 },
|
||||
{ 0x1a, 0x02 },
|
||||
{ 0x1b, 0xc9 },
|
||||
/* program PLL1_11 multiplier */
|
||||
{ 0x1c, 0x00 },
|
||||
{ 0x1d, 0x40 },
|
||||
{ 0x1e, 0x02 },
|
||||
{ 0x1f, 0xc9 },
|
||||
/* output state selection */
|
||||
{ 0x15, 0x00 },
|
||||
{ 0x14, 0xef },
|
||||
/* switch MUX to PLL1 output */
|
||||
{ 0x14, 0x6f },
|
||||
{ 0x16, 0x06 },
|
||||
/* set P2DIV divider, P3DIV and input crystal */
|
||||
{ 0x17, 0x06 },
|
||||
{ 0x01, 0x00 },
|
||||
{ 0x05, 0x48 },
|
||||
{ 0x02, 0x80 },
|
||||
/* enable and disable PLL */
|
||||
{ 0x02, 0xbc },
|
||||
{ 0x03, 0x01 },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct cdce_reg cdce_y1_74250[] = {
|
||||
{ 0x13, 0x00 },
|
||||
{ 0x18, 0xaf },
|
||||
{ 0x19, 0x50 },
|
||||
{ 0x1a, 0x02 },
|
||||
{ 0x1b, 0xc9 },
|
||||
{ 0x1c, 0x00 },
|
||||
{ 0x1d, 0x40 },
|
||||
{ 0x1e, 0x02 },
|
||||
{ 0x1f, 0xc9 },
|
||||
/* output state selection */
|
||||
{ 0x15, 0x00 },
|
||||
{ 0x14, 0xef },
|
||||
/* switch MUX to PLL1 output */
|
||||
{ 0x14, 0x6f },
|
||||
{ 0x16, 0x06 },
|
||||
/* set P2DIV divider, P3DIV and input crystal */
|
||||
{ 0x17, 0x06 },
|
||||
{ 0x01, 0x00 },
|
||||
{ 0x05, 0x48 },
|
||||
{ 0x02, 0x80 },
|
||||
/* enable and disable PLL */
|
||||
{ 0x02, 0xbc },
|
||||
{ 0x03, 0x02 },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct cdce_reg cdce_y1_27000[] = {
|
||||
{ 0x13, 0x00 },
|
||||
{ 0x18, 0x00 },
|
||||
{ 0x19, 0x40 },
|
||||
{ 0x1a, 0x02 },
|
||||
{ 0x1b, 0x08 },
|
||||
{ 0x1c, 0x00 },
|
||||
{ 0x1d, 0x40 },
|
||||
{ 0x1e, 0x02 },
|
||||
{ 0x1f, 0x08 },
|
||||
{ 0x15, 0x02 },
|
||||
{ 0x14, 0xed },
|
||||
{ 0x16, 0x01 },
|
||||
{ 0x17, 0x01 },
|
||||
{ 0x01, 0x00 },
|
||||
{ 0x05, 0x50 },
|
||||
{ 0x02, 0xb4 },
|
||||
{ 0x03, 0x01 },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct cdce_freq cdce_y1_freqs[] = {
|
||||
CDCE_FREQ_TABLE_ENTRY(1, 148500),
|
||||
CDCE_FREQ_TABLE_ENTRY(1, 74250),
|
||||
CDCE_FREQ_TABLE_ENTRY(1, 27000),
|
||||
};
|
||||
|
||||
static struct cdce_reg cdce_y5_13500[] = {
|
||||
{ 0x27, 0x08 },
|
||||
{ 0x28, 0x00 },
|
||||
{ 0x29, 0x40 },
|
||||
{ 0x2a, 0x02 },
|
||||
{ 0x2b, 0x08 },
|
||||
{ 0x24, 0x6f },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct cdce_reg cdce_y5_16875[] = {
|
||||
{ 0x27, 0x08 },
|
||||
{ 0x28, 0x9f },
|
||||
{ 0x29, 0xb0 },
|
||||
{ 0x2a, 0x02 },
|
||||
{ 0x2b, 0x89 },
|
||||
{ 0x24, 0x6f },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct cdce_reg cdce_y5_27000[] = {
|
||||
{ 0x27, 0x04 },
|
||||
{ 0x28, 0x00 },
|
||||
{ 0x29, 0x40 },
|
||||
{ 0x2a, 0x02 },
|
||||
{ 0x2b, 0x08 },
|
||||
{ 0x24, 0x6f },
|
||||
{ },
|
||||
};
|
||||
static struct cdce_reg cdce_y5_54000[] = {
|
||||
{ 0x27, 0x04 },
|
||||
{ 0x28, 0xff },
|
||||
{ 0x29, 0x80 },
|
||||
{ 0x2a, 0x02 },
|
||||
{ 0x2b, 0x07 },
|
||||
{ 0x24, 0x6f },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct cdce_reg cdce_y5_81000[] = {
|
||||
{ 0x27, 0x02 },
|
||||
{ 0x28, 0xbf },
|
||||
{ 0x29, 0xa0 },
|
||||
{ 0x2a, 0x03 },
|
||||
{ 0x2b, 0x0a },
|
||||
{ 0x24, 0x6f },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct cdce_freq cdce_y5_freqs[] = {
|
||||
CDCE_FREQ_TABLE_ENTRY(5, 13500),
|
||||
CDCE_FREQ_TABLE_ENTRY(5, 16875),
|
||||
CDCE_FREQ_TABLE_ENTRY(5, 27000),
|
||||
CDCE_FREQ_TABLE_ENTRY(5, 54000),
|
||||
CDCE_FREQ_TABLE_ENTRY(5, 81000),
|
||||
};
|
||||
|
||||
|
||||
static struct cdce_output output_list[] = {
|
||||
[1] = { cdce_y1_freqs, ARRAY_SIZE(cdce_y1_freqs) },
|
||||
[5] = { cdce_y5_freqs, ARRAY_SIZE(cdce_y5_freqs) },
|
||||
};
|
||||
|
||||
int cdce_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
int i, ret = 0;
|
||||
struct cdce_freq *freq_table = output_list[clk->lpsc].freq_table;
|
||||
struct cdce_reg *regs = NULL;
|
||||
|
||||
if (!cdce_i2c_client)
|
||||
return -ENODEV;
|
||||
|
||||
if (!freq_table)
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < output_list[clk->lpsc].size; i++) {
|
||||
if (freq_table[i].frequency == rate / 1000) {
|
||||
regs = freq_table[i].reglist;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!regs)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&cdce_mutex);
|
||||
for (i = 0; regs[i].addr; i++) {
|
||||
ret = i2c_smbus_write_byte_data(cdce_i2c_client,
|
||||
regs[i].addr | 0x80, regs[i].val);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
mutex_unlock(&cdce_mutex);
|
||||
|
||||
if (!ret)
|
||||
clk->rate = rate;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int cdce_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
cdce_i2c_client = client;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devexit cdce_remove(struct i2c_client *client)
|
||||
{
|
||||
cdce_i2c_client = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id cdce_id[] = {
|
||||
{"cdce949", 0},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, cdce_id);
|
||||
|
||||
static struct i2c_driver cdce_driver = {
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "cdce949",
|
||||
},
|
||||
.probe = cdce_probe,
|
||||
.remove = __devexit_p(cdce_remove),
|
||||
.id_table = cdce_id,
|
||||
};
|
||||
|
||||
static int __init cdce_init(void)
|
||||
{
|
||||
return i2c_add_driver(&cdce_driver);
|
||||
}
|
||||
subsys_initcall(cdce_init);
|
||||
|
||||
static void __exit cdce_exit(void)
|
||||
{
|
||||
i2c_del_driver(&cdce_driver);
|
||||
}
|
||||
module_exit(cdce_exit);
|
||||
|
||||
MODULE_AUTHOR("Texas Instruments");
|
||||
MODULE_DESCRIPTION("CDCE949 clock synthesizer driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -49,7 +49,8 @@ static void __clk_disable(struct clk *clk)
|
|||
{
|
||||
if (WARN_ON(clk->usecount == 0))
|
||||
return;
|
||||
if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
|
||||
if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
|
||||
(clk->flags & CLK_PSC))
|
||||
davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
|
||||
if (clk->parent)
|
||||
__clk_disable(clk->parent);
|
||||
|
|
@ -124,9 +125,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
|||
if (clk == NULL || IS_ERR(clk))
|
||||
return ret;
|
||||
|
||||
spin_lock_irqsave(&clockfw_lock, flags);
|
||||
if (clk->set_rate)
|
||||
ret = clk->set_rate(clk, rate);
|
||||
|
||||
spin_lock_irqsave(&clockfw_lock, flags);
|
||||
if (ret == 0) {
|
||||
if (clk->recalc)
|
||||
clk->rate = clk->recalc(clk);
|
||||
|
|
@ -363,6 +365,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
|
|||
{
|
||||
u32 ctrl;
|
||||
unsigned int locktime;
|
||||
unsigned long flags;
|
||||
|
||||
if (pll->base == NULL)
|
||||
return -EINVAL;
|
||||
|
|
@ -376,25 +379,23 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
|
|||
locktime = ((2000 * prediv) / 100);
|
||||
prediv = (prediv - 1) | PLLDIV_EN;
|
||||
} else {
|
||||
locktime = 20;
|
||||
locktime = PLL_LOCK_TIME;
|
||||
}
|
||||
if (postdiv)
|
||||
postdiv = (postdiv - 1) | PLLDIV_EN;
|
||||
if (mult)
|
||||
mult = mult - 1;
|
||||
|
||||
/* Protect against simultaneous calls to PLL setting seqeunce */
|
||||
spin_lock_irqsave(&clockfw_lock, flags);
|
||||
|
||||
ctrl = __raw_readl(pll->base + PLLCTL);
|
||||
|
||||
/* Switch the PLL to bypass mode */
|
||||
ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
|
||||
__raw_writel(ctrl, pll->base + PLLCTL);
|
||||
|
||||
/*
|
||||
* Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
|
||||
* to bypass mode. Delay of 1us ensures we are good for all > 4MHz
|
||||
* OSCIN/CLKIN inputs. Typically the input is ~25MHz.
|
||||
*/
|
||||
udelay(1);
|
||||
udelay(PLL_BYPASS_TIME);
|
||||
|
||||
/* Reset and enable PLL */
|
||||
ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
|
||||
|
|
@ -408,11 +409,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
|
|||
if (pll->flags & PLL_HAS_POSTDIV)
|
||||
__raw_writel(postdiv, pll->base + POSTDIV);
|
||||
|
||||
/*
|
||||
* Wait for PLL to reset properly, OMAP-L138 datasheet says
|
||||
* 'min' time = 125ns
|
||||
*/
|
||||
udelay(1);
|
||||
udelay(PLL_RESET_TIME);
|
||||
|
||||
/* Bring PLL out of reset */
|
||||
ctrl |= PLLCTL_PLLRST;
|
||||
|
|
@ -424,17 +421,20 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
|
|||
ctrl |= PLLCTL_PLLEN;
|
||||
__raw_writel(ctrl, pll->base + PLLCTL);
|
||||
|
||||
spin_unlock_irqrestore(&clockfw_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(davinci_set_pllrate);
|
||||
|
||||
int __init davinci_clk_init(struct davinci_clk *clocks)
|
||||
int __init davinci_clk_init(struct clk_lookup *clocks)
|
||||
{
|
||||
struct davinci_clk *c;
|
||||
struct clk_lookup *c;
|
||||
struct clk *clk;
|
||||
size_t num_clocks = 0;
|
||||
|
||||
for (c = clocks; c->lk.clk; c++) {
|
||||
clk = c->lk.clk;
|
||||
for (c = clocks; c->clk; c++) {
|
||||
clk = c->clk;
|
||||
|
||||
if (!clk->recalc) {
|
||||
|
||||
|
|
@ -457,36 +457,24 @@ int __init davinci_clk_init(struct davinci_clk *clocks)
|
|||
if (clk->lpsc)
|
||||
clk->flags |= CLK_PSC;
|
||||
|
||||
clkdev_add(&c->lk);
|
||||
clk_register(clk);
|
||||
num_clocks++;
|
||||
|
||||
/* Turn on clocks that Linux doesn't otherwise manage */
|
||||
if (clk->flags & ALWAYS_ENABLED)
|
||||
clk_enable(clk);
|
||||
}
|
||||
|
||||
clkdev_add_table(clocks, num_clocks);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PROC_FS
|
||||
#include <linux/proc_fs.h>
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
static void *davinci_ck_start(struct seq_file *m, loff_t *pos)
|
||||
{
|
||||
return *pos < 1 ? (void *)1 : NULL;
|
||||
}
|
||||
|
||||
static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos)
|
||||
{
|
||||
++*pos;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void davinci_ck_stop(struct seq_file *m, void *v)
|
||||
{
|
||||
}
|
||||
|
||||
#define CLKNAME_MAX 10 /* longest clock name */
|
||||
#define NEST_DELTA 2
|
||||
#define NEST_MAX 4
|
||||
|
|
@ -525,41 +513,38 @@ dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
|
|||
|
||||
static int davinci_ck_show(struct seq_file *m, void *v)
|
||||
{
|
||||
/* Show clock tree; we know the main oscillator is first.
|
||||
* We trust nonzero usecounts equate to PSC enables...
|
||||
struct clk *clk;
|
||||
|
||||
/*
|
||||
* Show clock tree; We trust nonzero usecounts equate to PSC enables...
|
||||
*/
|
||||
mutex_lock(&clocks_mutex);
|
||||
if (!list_empty(&clocks))
|
||||
dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
|
||||
list_for_each_entry(clk, &clocks, node)
|
||||
if (!clk->parent)
|
||||
dump_clock(m, 0, clk);
|
||||
mutex_unlock(&clocks_mutex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct seq_operations davinci_ck_op = {
|
||||
.start = davinci_ck_start,
|
||||
.next = davinci_ck_next,
|
||||
.stop = davinci_ck_stop,
|
||||
.show = davinci_ck_show
|
||||
};
|
||||
|
||||
static int davinci_ck_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return seq_open(file, &davinci_ck_op);
|
||||
return single_open(file, davinci_ck_show, NULL);
|
||||
}
|
||||
|
||||
static const struct file_operations proc_davinci_ck_operations = {
|
||||
static const struct file_operations davinci_ck_operations = {
|
||||
.open = davinci_ck_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = seq_release,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int __init davinci_ck_proc_init(void)
|
||||
static int __init davinci_clk_debugfs_init(void)
|
||||
{
|
||||
proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations);
|
||||
debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
|
||||
&davinci_ck_operations);
|
||||
return 0;
|
||||
|
||||
}
|
||||
__initcall(davinci_ck_proc_init);
|
||||
#endif /* CONFIG_DEBUG_PROC_FS */
|
||||
device_initcall(davinci_clk_debugfs_init);
|
||||
#endif /* CONFIG_DEBUG_FS */
|
||||
|
|
|
|||
|
|
@ -12,9 +12,6 @@
|
|||
#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
|
||||
#define __ARCH_ARM_DAVINCI_CLOCK_H
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <asm/clkdev.h>
|
||||
|
||||
#define DAVINCI_PLL1_BASE 0x01c40800
|
||||
#define DAVINCI_PLL2_BASE 0x01c40c00
|
||||
#define MAX_PLL 2
|
||||
|
|
@ -53,6 +50,26 @@
|
|||
#define PLLDIV_EN BIT(15)
|
||||
#define PLLDIV_RATIO_MASK 0x1f
|
||||
|
||||
/*
|
||||
* OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
|
||||
* cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
|
||||
* ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
|
||||
* is ~25MHz. Units are micro seconds.
|
||||
*/
|
||||
#define PLL_BYPASS_TIME 1
|
||||
/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
|
||||
#define PLL_RESET_TIME 1
|
||||
/*
|
||||
* From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
|
||||
* Units are micro seconds.
|
||||
*/
|
||||
#define PLL_LOCK_TIME 20
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <asm/clkdev.h>
|
||||
|
||||
struct pll_data {
|
||||
u32 phys_base;
|
||||
void __iomem *base;
|
||||
|
|
@ -89,23 +106,19 @@ struct clk {
|
|||
#define CLK_PLL BIT(4) /* PLL-derived clock */
|
||||
#define PRE_PLL BIT(5) /* source is before PLL mult/div */
|
||||
|
||||
struct davinci_clk {
|
||||
struct clk_lookup lk;
|
||||
};
|
||||
#define CLK(dev, con, ck) \
|
||||
{ \
|
||||
.dev_id = dev, \
|
||||
.con_id = con, \
|
||||
.clk = ck, \
|
||||
} \
|
||||
|
||||
#define CLK(dev, con, ck) \
|
||||
{ \
|
||||
.lk = { \
|
||||
.dev_id = dev, \
|
||||
.con_id = con, \
|
||||
.clk = ck, \
|
||||
}, \
|
||||
}
|
||||
|
||||
int davinci_clk_init(struct davinci_clk *clocks);
|
||||
int davinci_clk_init(struct clk_lookup *clocks);
|
||||
int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
|
||||
unsigned int mult, unsigned int postdiv);
|
||||
|
||||
extern struct platform_device davinci_wdt_device;
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,13 +11,13 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/davinci_emac.h>
|
||||
|
||||
#include <asm/tlb.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/cputype.h>
|
||||
#include <mach/emac.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <asm/proc-fns.h>
|
||||
|
||||
#include <mach/cpuidle.h>
|
||||
#include <mach/memory.h>
|
||||
|
||||
#define DAVINCI_CPUIDLE_MAX_STATES 2
|
||||
|
||||
|
|
@ -39,10 +40,6 @@ static struct cpuidle_driver davinci_idle_driver = {
|
|||
static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
|
||||
static void __iomem *ddr2_reg_base;
|
||||
|
||||
#define DDR2_SDRCR_OFFSET 0xc
|
||||
#define DDR2_SRPD_BIT BIT(23)
|
||||
#define DDR2_LPMODEN_BIT BIT(31)
|
||||
|
||||
static void davinci_save_ddr_power(int enter, bool pdown)
|
||||
{
|
||||
u32 val;
|
||||
|
|
@ -109,8 +106,6 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
|
|||
int ret;
|
||||
struct cpuidle_device *device;
|
||||
struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
|
||||
struct resource *ddr2_regs;
|
||||
resource_size_t len;
|
||||
|
||||
device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
|
||||
|
||||
|
|
@ -119,28 +114,12 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
|
|||
return -ENOENT;
|
||||
}
|
||||
|
||||
ddr2_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!ddr2_regs) {
|
||||
dev_err(&pdev->dev, "cannot get DDR2 controller register base");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
len = resource_size(ddr2_regs);
|
||||
|
||||
ddr2_regs = request_mem_region(ddr2_regs->start, len, ddr2_regs->name);
|
||||
if (!ddr2_regs)
|
||||
return -EBUSY;
|
||||
|
||||
ddr2_reg_base = ioremap(ddr2_regs->start, len);
|
||||
if (!ddr2_reg_base) {
|
||||
ret = -ENOMEM;
|
||||
goto ioremap_fail;
|
||||
}
|
||||
ddr2_reg_base = pdata->ddr2_ctlr_base;
|
||||
|
||||
ret = cpuidle_register_driver(&davinci_idle_driver);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register driver\n");
|
||||
goto driver_register_fail;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Wait for interrupt state */
|
||||
|
|
@ -167,18 +146,11 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
|
|||
ret = cpuidle_register_device(device);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register device\n");
|
||||
goto device_register_fail;
|
||||
cpuidle_unregister_driver(&davinci_idle_driver);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
device_register_fail:
|
||||
cpuidle_unregister_driver(&davinci_idle_driver);
|
||||
driver_register_fail:
|
||||
iounmap(ddr2_reg_base);
|
||||
ioremap_fail:
|
||||
release_mem_region(ddr2_regs->start, len);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver davinci_cpuidle_driver = {
|
||||
|
|
|
|||
|
|
@ -371,7 +371,7 @@ static struct clk rmii_clk = {
|
|||
.parent = &pll0_sysclk7,
|
||||
};
|
||||
|
||||
static struct davinci_clk da830_clks[] = {
|
||||
static struct clk_lookup da830_clks[] = {
|
||||
CLK(NULL, "ref", &ref_clk),
|
||||
CLK(NULL, "pll0", &pll0_clk),
|
||||
CLK(NULL, "pll0_aux", &pll0_aux_clk),
|
||||
|
|
@ -1208,13 +1208,13 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
|
|||
|
||||
void __init da830_init(void)
|
||||
{
|
||||
da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
|
||||
if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
|
||||
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
|
||||
if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
|
||||
return;
|
||||
|
||||
davinci_soc_info_da830.jtag_id_base =
|
||||
DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
|
||||
davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
|
||||
DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
|
||||
davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
|
||||
|
||||
davinci_common_init(&davinci_soc_info_da830);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include <mach/time.h>
|
||||
#include <mach/da8xx.h>
|
||||
#include <mach/cpufreq.h>
|
||||
#include <mach/pm.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "mux.h"
|
||||
|
|
@ -40,6 +41,7 @@
|
|||
#define DA850_REF_FREQ 24000000
|
||||
|
||||
#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
|
||||
#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
|
||||
#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
|
||||
|
||||
static int da850_set_armrate(struct clk *clk, unsigned long rate);
|
||||
|
|
@ -333,7 +335,7 @@ static struct clk aemif_clk = {
|
|||
.flags = ALWAYS_ENABLED,
|
||||
};
|
||||
|
||||
static struct davinci_clk da850_clks[] = {
|
||||
static struct clk_lookup da850_clks[] = {
|
||||
CLK(NULL, "ref", &ref_clk),
|
||||
CLK(NULL, "pll0", &pll0_clk),
|
||||
CLK(NULL, "pll0_aux", &pll0_aux_clk),
|
||||
|
|
@ -535,6 +537,7 @@ static const struct mux_config da850_pins[] = {
|
|||
MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
|
||||
MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
|
||||
MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
|
||||
MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -770,6 +773,12 @@ static struct map_desc da850_io_desc[] = {
|
|||
.length = DA8XX_CP_INTC_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = SRAM_VIRT,
|
||||
.pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
|
||||
.length = SZ_8K,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
};
|
||||
|
||||
static void __iomem *da850_psc_bases[] = {
|
||||
|
|
@ -825,12 +834,12 @@ static struct davinci_timer_info da850_timer_info = {
|
|||
static void da850_set_async3_src(int pllnum)
|
||||
{
|
||||
struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
|
||||
struct davinci_clk *c;
|
||||
struct clk_lookup *c;
|
||||
unsigned int v;
|
||||
int ret;
|
||||
|
||||
for (c = da850_clks; c->lk.clk; c++) {
|
||||
clk = c->lk.clk;
|
||||
for (c = da850_clks; c->clk; c++) {
|
||||
clk = c->clk;
|
||||
if (clk->flags & DA850_CLK_ASYNC3) {
|
||||
ret = clk_set_parent(clk, newparent);
|
||||
WARN(ret, "DA850: unable to re-parent clock %s",
|
||||
|
|
@ -838,12 +847,12 @@ static void da850_set_async3_src(int pllnum)
|
|||
}
|
||||
}
|
||||
|
||||
v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
|
||||
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
||||
if (pllnum)
|
||||
v |= CFGCHIP3_ASYNC3_CLKSRC;
|
||||
else
|
||||
v &= ~CFGCHIP3_ASYNC3_CLKSRC;
|
||||
__raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
|
||||
__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ
|
||||
|
|
@ -987,7 +996,6 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
|
|||
unsigned int prediv, mult, postdiv;
|
||||
struct da850_opp *opp;
|
||||
struct pll_data *pll = clk->pll_data;
|
||||
unsigned int v;
|
||||
int ret;
|
||||
|
||||
opp = (struct da850_opp *) da850_freq_table[index].index;
|
||||
|
|
@ -995,11 +1003,6 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
|
|||
mult = opp->mult;
|
||||
postdiv = opp->postdiv;
|
||||
|
||||
/* Unlock writing to PLL registers */
|
||||
v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
|
||||
v &= ~CFGCHIP0_PLL_MASTER_LOCK;
|
||||
__raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
|
||||
|
||||
ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
|
||||
if (WARN_ON(ret))
|
||||
return ret;
|
||||
|
|
@ -1028,6 +1031,43 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
|
|||
}
|
||||
#endif
|
||||
|
||||
int da850_register_pm(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct davinci_pm_config *pdata = pdev->dev.platform_data;
|
||||
|
||||
ret = davinci_cfg_reg(DA850_RTC_ALARM);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
|
||||
pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
|
||||
pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
|
||||
|
||||
pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
|
||||
if (!pdata->cpupll_reg_base)
|
||||
return -ENOMEM;
|
||||
|
||||
pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
|
||||
if (!pdata->ddrpll_reg_base) {
|
||||
ret = -ENOMEM;
|
||||
goto no_ddrpll_mem;
|
||||
}
|
||||
|
||||
pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
|
||||
if (!pdata->ddrpsc_reg_base) {
|
||||
ret = -ENOMEM;
|
||||
goto no_ddrpsc_mem;
|
||||
}
|
||||
|
||||
return platform_device_register(pdev);
|
||||
|
||||
no_ddrpsc_mem:
|
||||
iounmap(pdata->ddrpll_reg_base);
|
||||
no_ddrpll_mem:
|
||||
iounmap(pdata->cpupll_reg_base);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct davinci_soc_info davinci_soc_info_da850 = {
|
||||
.io_desc = da850_io_desc,
|
||||
|
|
@ -1049,17 +1089,25 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
|
|||
.gpio_irq = IRQ_DA8XX_GPIO0,
|
||||
.serial_dev = &da8xx_serial_device,
|
||||
.emac_pdata = &da8xx_emac_pdata,
|
||||
.sram_dma = DA8XX_ARM_RAM_BASE,
|
||||
.sram_len = SZ_8K,
|
||||
};
|
||||
|
||||
void __init da850_init(void)
|
||||
{
|
||||
da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
|
||||
if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
|
||||
unsigned int v;
|
||||
|
||||
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
|
||||
if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
|
||||
return;
|
||||
|
||||
da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
|
||||
if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
|
||||
return;
|
||||
|
||||
davinci_soc_info_da850.jtag_id_base =
|
||||
DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
|
||||
davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
|
||||
DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
|
||||
davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
|
||||
|
||||
davinci_common_init(&davinci_soc_info_da850);
|
||||
|
||||
|
|
@ -1071,4 +1119,14 @@ void __init da850_init(void)
|
|||
* be any noticible change even in non-DVFS use cases.
|
||||
*/
|
||||
da850_set_async3_src(1);
|
||||
|
||||
/* Unlock writing to PLL0 registers */
|
||||
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
|
||||
v &= ~CFGCHIP0_PLL_MASTER_LOCK;
|
||||
__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
|
||||
|
||||
/* Unlock writing to PLL1 registers */
|
||||
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
||||
v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
|
||||
__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,8 +24,10 @@
|
|||
#include "clock.h"
|
||||
|
||||
#define DA8XX_TPCC_BASE 0x01c00000
|
||||
#define DA850_TPCC1_BASE 0x01e30000
|
||||
#define DA8XX_TPTC0_BASE 0x01c08000
|
||||
#define DA8XX_TPTC1_BASE 0x01c08400
|
||||
#define DA850_TPTC2_BASE 0x01e38000
|
||||
#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
|
||||
#define DA8XX_I2C0_BASE 0x01c22000
|
||||
#define DA8XX_RTC_BASE 0x01C23000
|
||||
|
|
@ -42,7 +44,8 @@
|
|||
#define DA8XX_MDIO_REG_OFFSET 0x4000
|
||||
#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
|
||||
|
||||
void __iomem *da8xx_syscfg_base;
|
||||
void __iomem *da8xx_syscfg0_base;
|
||||
void __iomem *da8xx_syscfg1_base;
|
||||
|
||||
static struct plat_serial8250_port da8xx_serial_pdata[] = {
|
||||
{
|
||||
|
|
@ -82,11 +85,6 @@ struct platform_device da8xx_serial_device = {
|
|||
},
|
||||
};
|
||||
|
||||
static const s8 da8xx_dma_chan_no_event[] = {
|
||||
20, 21,
|
||||
-1
|
||||
};
|
||||
|
||||
static const s8 da8xx_queue_tc_mapping[][2] = {
|
||||
/* {event queue no, TC no} */
|
||||
{0, 0},
|
||||
|
|
@ -101,20 +99,52 @@ static const s8 da8xx_queue_priority_mapping[][2] = {
|
|||
{-1, -1}
|
||||
};
|
||||
|
||||
static struct edma_soc_info da8xx_edma_info[] = {
|
||||
static const s8 da850_queue_tc_mapping[][2] = {
|
||||
/* {event queue no, TC no} */
|
||||
{0, 0},
|
||||
{-1, -1}
|
||||
};
|
||||
|
||||
static const s8 da850_queue_priority_mapping[][2] = {
|
||||
/* {event queue no, Priority} */
|
||||
{0, 3},
|
||||
{-1, -1}
|
||||
};
|
||||
|
||||
static struct edma_soc_info da830_edma_info[] = {
|
||||
{
|
||||
.n_channel = 32,
|
||||
.n_region = 4,
|
||||
.n_slot = 128,
|
||||
.n_tc = 2,
|
||||
.n_cc = 1,
|
||||
.noevent = da8xx_dma_chan_no_event,
|
||||
.queue_tc_mapping = da8xx_queue_tc_mapping,
|
||||
.queue_priority_mapping = da8xx_queue_priority_mapping,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource da8xx_edma_resources[] = {
|
||||
static struct edma_soc_info da850_edma_info[] = {
|
||||
{
|
||||
.n_channel = 32,
|
||||
.n_region = 4,
|
||||
.n_slot = 128,
|
||||
.n_tc = 2,
|
||||
.n_cc = 1,
|
||||
.queue_tc_mapping = da8xx_queue_tc_mapping,
|
||||
.queue_priority_mapping = da8xx_queue_priority_mapping,
|
||||
},
|
||||
{
|
||||
.n_channel = 32,
|
||||
.n_region = 4,
|
||||
.n_slot = 128,
|
||||
.n_tc = 1,
|
||||
.n_cc = 1,
|
||||
.queue_tc_mapping = da850_queue_tc_mapping,
|
||||
.queue_priority_mapping = da850_queue_priority_mapping,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource da830_edma_resources[] = {
|
||||
{
|
||||
.name = "edma_cc0",
|
||||
.start = DA8XX_TPCC_BASE,
|
||||
|
|
@ -145,19 +175,91 @@ static struct resource da8xx_edma_resources[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct platform_device da8xx_edma_device = {
|
||||
static struct resource da850_edma_resources[] = {
|
||||
{
|
||||
.name = "edma_cc0",
|
||||
.start = DA8XX_TPCC_BASE,
|
||||
.end = DA8XX_TPCC_BASE + SZ_32K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "edma_tc0",
|
||||
.start = DA8XX_TPTC0_BASE,
|
||||
.end = DA8XX_TPTC0_BASE + SZ_1K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "edma_tc1",
|
||||
.start = DA8XX_TPTC1_BASE,
|
||||
.end = DA8XX_TPTC1_BASE + SZ_1K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "edma_cc1",
|
||||
.start = DA850_TPCC1_BASE,
|
||||
.end = DA850_TPCC1_BASE + SZ_32K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "edma_tc2",
|
||||
.start = DA850_TPTC2_BASE,
|
||||
.end = DA850_TPTC2_BASE + SZ_1K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "edma0",
|
||||
.start = IRQ_DA8XX_CCINT0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.name = "edma0_err",
|
||||
.start = IRQ_DA8XX_CCERRINT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.name = "edma1",
|
||||
.start = IRQ_DA850_CCINT1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.name = "edma1_err",
|
||||
.start = IRQ_DA850_CCERRINT1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device da830_edma_device = {
|
||||
.name = "edma",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = da8xx_edma_info,
|
||||
.platform_data = da830_edma_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(da8xx_edma_resources),
|
||||
.resource = da8xx_edma_resources,
|
||||
.num_resources = ARRAY_SIZE(da830_edma_resources),
|
||||
.resource = da830_edma_resources,
|
||||
};
|
||||
|
||||
static struct platform_device da850_edma_device = {
|
||||
.name = "edma",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = da850_edma_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(da850_edma_resources),
|
||||
.resource = da850_edma_resources,
|
||||
};
|
||||
|
||||
int __init da8xx_register_edma(void)
|
||||
{
|
||||
return platform_device_register(&da8xx_edma_device);
|
||||
struct platform_device *pdev;
|
||||
|
||||
if (cpu_is_davinci_da830())
|
||||
pdev = &da830_edma_device;
|
||||
else if (cpu_is_davinci_da850())
|
||||
pdev = &da850_edma_device;
|
||||
else
|
||||
return -ENODEV;
|
||||
|
||||
return platform_device_register(pdev);
|
||||
}
|
||||
|
||||
static struct resource da8xx_i2c_resources0[] = {
|
||||
|
|
@ -495,6 +597,19 @@ int da8xx_register_rtc(void)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void __iomem *da8xx_ddr2_ctlr_base;
|
||||
void __iomem * __init da8xx_get_mem_ctlr(void)
|
||||
{
|
||||
if (da8xx_ddr2_ctlr_base)
|
||||
return da8xx_ddr2_ctlr_base;
|
||||
|
||||
da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
|
||||
if (!da8xx_ddr2_ctlr_base)
|
||||
pr_warning("%s: Unable to map DDR2 controller", __func__);
|
||||
|
||||
return da8xx_ddr2_ctlr_base;
|
||||
}
|
||||
|
||||
static struct resource da8xx_cpuidle_resources[] = {
|
||||
{
|
||||
.start = DA8XX_DDR2_CTL_BASE,
|
||||
|
|
@ -520,6 +635,7 @@ static struct platform_device da8xx_cpuidle_device = {
|
|||
|
||||
int __init da8xx_register_cpuidle(void)
|
||||
{
|
||||
da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
|
||||
|
||||
return platform_device_register(&da8xx_cpuidle_device);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#include <mach/serial.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/asp.h>
|
||||
#include <mach/spi.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "mux.h"
|
||||
|
|
@ -334,7 +335,7 @@ static struct clk usb_clk = {
|
|||
.lpsc = DAVINCI_LPSC_USB,
|
||||
};
|
||||
|
||||
static struct davinci_clk dm355_clks[] = {
|
||||
static struct clk_lookup dm355_clks[] = {
|
||||
CLK(NULL, "ref", &ref_clk),
|
||||
CLK(NULL, "pll1", &pll1_clk),
|
||||
CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
|
||||
|
|
@ -362,9 +363,9 @@ static struct davinci_clk dm355_clks[] = {
|
|||
CLK("davinci-asp.1", NULL, &asp1_clk),
|
||||
CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
|
||||
CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
|
||||
CLK(NULL, "spi0", &spi0_clk),
|
||||
CLK(NULL, "spi1", &spi1_clk),
|
||||
CLK(NULL, "spi2", &spi2_clk),
|
||||
CLK("spi_davinci.0", NULL, &spi0_clk),
|
||||
CLK("spi_davinci.1", NULL, &spi1_clk),
|
||||
CLK("spi_davinci.2", NULL, &spi2_clk),
|
||||
CLK(NULL, "gpio", &gpio_clk),
|
||||
CLK(NULL, "aemif", &aemif_clk),
|
||||
CLK(NULL, "pwm0", &pwm0_clk),
|
||||
|
|
@ -391,24 +392,40 @@ static struct resource dm355_spi0_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM355_SPINT0_1,
|
||||
.start = IRQ_DM355_SPINT0_0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
/* Not yet used, so not included:
|
||||
* IORESOURCE_IRQ:
|
||||
* - IRQ_DM355_SPINT0_0
|
||||
* IORESOURCE_DMA:
|
||||
* - DAVINCI_DMA_SPI_SPIX
|
||||
* - DAVINCI_DMA_SPI_SPIR
|
||||
*/
|
||||
{
|
||||
.start = 17,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = 16,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = EVENTQ_1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct davinci_spi_platform_data dm355_spi0_pdata = {
|
||||
.version = SPI_VERSION_1,
|
||||
.num_chipselect = 2,
|
||||
.clk_internal = 1,
|
||||
.cs_hold = 1,
|
||||
.intr_level = 0,
|
||||
.poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
|
||||
.c2tdelay = 0,
|
||||
.t2cdelay = 0,
|
||||
};
|
||||
static struct platform_device dm355_spi0_device = {
|
||||
.name = "spi_davinci",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &dm355_spi0_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &dm355_spi0_pdata,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(dm355_spi0_resources),
|
||||
.resource = dm355_spi0_resources,
|
||||
|
|
@ -563,13 +580,6 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
|
|||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
static const s8 dma_chan_dm355_no_event[] = {
|
||||
12, 13, 24, 56, 57,
|
||||
58, 59, 60, 61, 62,
|
||||
63,
|
||||
-1
|
||||
};
|
||||
|
||||
static const s8
|
||||
queue_tc_mapping[][2] = {
|
||||
/* {event queue no, TC no} */
|
||||
|
|
@ -593,7 +603,6 @@ static struct edma_soc_info dm355_edma_info[] = {
|
|||
.n_slot = 128,
|
||||
.n_tc = 2,
|
||||
.n_cc = 1,
|
||||
.noevent = dma_chan_dm355_no_event,
|
||||
.queue_tc_mapping = queue_tc_mapping,
|
||||
.queue_priority_mapping = queue_priority_mapping,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
|
|
@ -32,6 +33,8 @@
|
|||
#include <mach/common.h>
|
||||
#include <mach/asp.h>
|
||||
#include <mach/keyscan.h>
|
||||
#include <mach/spi.h>
|
||||
|
||||
|
||||
#include "clock.h"
|
||||
#include "mux.h"
|
||||
|
|
@ -403,7 +406,7 @@ static struct clk mjcp_clk = {
|
|||
.lpsc = DM365_LPSC_MJCP,
|
||||
};
|
||||
|
||||
static struct davinci_clk dm365_clks[] = {
|
||||
static struct clk_lookup dm365_clks[] = {
|
||||
CLK(NULL, "ref", &ref_clk),
|
||||
CLK(NULL, "pll1", &pll1_clk),
|
||||
CLK(NULL, "pll1_aux", &pll1_aux_clk),
|
||||
|
|
@ -455,7 +458,7 @@ static struct davinci_clk dm365_clks[] = {
|
|||
CLK(NULL, "timer3", &timer3_clk),
|
||||
CLK(NULL, "usb", &usb_clk),
|
||||
CLK("davinci_emac.1", NULL, &emac_clk),
|
||||
CLK("voice_codec", NULL, &voicecodec_clk),
|
||||
CLK("davinci_voicecodec", NULL, &voicecodec_clk),
|
||||
CLK("davinci-asp.0", NULL, &asp0_clk),
|
||||
CLK(NULL, "rto", &rto_clk),
|
||||
CLK(NULL, "mjcp", &mjcp_clk),
|
||||
|
|
@ -606,9 +609,78 @@ INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
|
|||
|
||||
EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
|
||||
EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
|
||||
EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
|
||||
EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
|
||||
#endif
|
||||
};
|
||||
|
||||
static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct davinci_spi_platform_data dm365_spi0_pdata = {
|
||||
.version = SPI_VERSION_1,
|
||||
.num_chipselect = 2,
|
||||
.clk_internal = 1,
|
||||
.cs_hold = 1,
|
||||
.intr_level = 0,
|
||||
.poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
|
||||
.c2tdelay = 0,
|
||||
.t2cdelay = 0,
|
||||
};
|
||||
|
||||
static struct resource dm365_spi0_resources[] = {
|
||||
{
|
||||
.start = 0x01c66000,
|
||||
.end = 0x01c667ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_DM365_SPIINT0_0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = 17,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = 16,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = EVENTQ_3,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dm365_spi0_device = {
|
||||
.name = "spi_davinci",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &dm365_spi0_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &dm365_spi0_pdata,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(dm365_spi0_resources),
|
||||
.resource = dm365_spi0_resources,
|
||||
};
|
||||
|
||||
void __init dm365_init_spi0(unsigned chipselect_mask,
|
||||
struct spi_board_info *info, unsigned len)
|
||||
{
|
||||
davinci_cfg_reg(DM365_SPI0_SCLK);
|
||||
davinci_cfg_reg(DM365_SPI0_SDI);
|
||||
davinci_cfg_reg(DM365_SPI0_SDO);
|
||||
|
||||
/* not all slaves will be wired up */
|
||||
if (chipselect_mask & BIT(0))
|
||||
davinci_cfg_reg(DM365_SPI0_SDENA0);
|
||||
if (chipselect_mask & BIT(1))
|
||||
davinci_cfg_reg(DM365_SPI0_SDENA1);
|
||||
|
||||
spi_register_board_info(info, len);
|
||||
|
||||
platform_device_register(&dm365_spi0_device);
|
||||
}
|
||||
|
||||
static struct emac_platform_data dm365_emac_pdata = {
|
||||
.ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
|
||||
.ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
|
||||
|
|
@ -754,7 +826,7 @@ static struct edma_soc_info dm365_edma_info[] = {
|
|||
.n_cc = 1,
|
||||
.queue_tc_mapping = dm365_queue_tc_mapping,
|
||||
.queue_priority_mapping = dm365_queue_priority_mapping,
|
||||
.default_queue = EVENTQ_2,
|
||||
.default_queue = EVENTQ_3,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -835,6 +907,31 @@ static struct platform_device dm365_asp_device = {
|
|||
.resource = dm365_asp_resources,
|
||||
};
|
||||
|
||||
static struct resource dm365_vc_resources[] = {
|
||||
{
|
||||
.start = DAVINCI_DM365_VC_BASE,
|
||||
.end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = DAVINCI_DMA_VC_TX,
|
||||
.end = DAVINCI_DMA_VC_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = DAVINCI_DMA_VC_RX,
|
||||
.end = DAVINCI_DMA_VC_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dm365_vc_device = {
|
||||
.name = "davinci_voicecodec",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(dm365_vc_resources),
|
||||
.resource = dm365_vc_resources,
|
||||
};
|
||||
|
||||
static struct resource dm365_rtc_resources[] = {
|
||||
{
|
||||
.start = DM365_RTC_BASE,
|
||||
|
|
@ -991,6 +1088,14 @@ void __init dm365_init_asp(struct snd_platform_data *pdata)
|
|||
platform_device_register(&dm365_asp_device);
|
||||
}
|
||||
|
||||
void __init dm365_init_vc(struct snd_platform_data *pdata)
|
||||
{
|
||||
davinci_cfg_reg(DM365_EVT2_VC_TX);
|
||||
davinci_cfg_reg(DM365_EVT3_VC_RX);
|
||||
dm365_vc_device.dev.platform_data = pdata;
|
||||
platform_device_register(&dm365_vc_device);
|
||||
}
|
||||
|
||||
void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
|
||||
{
|
||||
dm365_ks_device.dev.platform_data = pdata;
|
||||
|
|
|
|||
|
|
@ -277,7 +277,7 @@ static struct clk timer2_clk = {
|
|||
.usecount = 1, /* REVISIT: why cant' this be disabled? */
|
||||
};
|
||||
|
||||
struct davinci_clk dm644x_clks[] = {
|
||||
struct clk_lookup dm644x_clks[] = {
|
||||
CLK(NULL, "ref", &ref_clk),
|
||||
CLK(NULL, "pll1", &pll1_clk),
|
||||
CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
|
||||
|
|
@ -479,15 +479,6 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
|
|||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
static const s8 dma_chan_dm644x_no_event[] = {
|
||||
0, 1, 12, 13, 14,
|
||||
15, 25, 30, 31, 45,
|
||||
46, 47, 55, 56, 57,
|
||||
58, 59, 60, 61, 62,
|
||||
63,
|
||||
-1
|
||||
};
|
||||
|
||||
static const s8
|
||||
queue_tc_mapping[][2] = {
|
||||
/* {event queue no, TC no} */
|
||||
|
|
@ -511,7 +502,6 @@ static struct edma_soc_info dm644x_edma_info[] = {
|
|||
.n_slot = 128,
|
||||
.n_tc = 2,
|
||||
.n_cc = 1,
|
||||
.noevent = dma_chan_dm644x_no_event,
|
||||
.queue_tc_mapping = queue_tc_mapping,
|
||||
.queue_priority_mapping = queue_priority_mapping,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -42,7 +42,6 @@
|
|||
/*
|
||||
* Device specific clocks
|
||||
*/
|
||||
#define DM646X_REF_FREQ 27000000
|
||||
#define DM646X_AUX_FREQ 24000000
|
||||
|
||||
static struct pll_data pll1_data = {
|
||||
|
|
@ -57,7 +56,6 @@ static struct pll_data pll2_data = {
|
|||
|
||||
static struct clk ref_clk = {
|
||||
.name = "ref_clk",
|
||||
.rate = DM646X_REF_FREQ,
|
||||
};
|
||||
|
||||
static struct clk aux_clkin = {
|
||||
|
|
@ -313,7 +311,7 @@ static struct clk vpif1_clk = {
|
|||
.flags = ALWAYS_ENABLED,
|
||||
};
|
||||
|
||||
struct davinci_clk dm646x_clks[] = {
|
||||
struct clk_lookup dm646x_clks[] = {
|
||||
CLK(NULL, "ref", &ref_clk),
|
||||
CLK(NULL, "aux", &aux_clkin),
|
||||
CLK(NULL, "pll1", &pll1_clk),
|
||||
|
|
@ -513,14 +511,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
|
|||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
static const s8 dma_chan_dm646x_no_event[] = {
|
||||
0, 1, 2, 3, 13,
|
||||
14, 15, 24, 25, 26,
|
||||
27, 30, 31, 54, 55,
|
||||
56,
|
||||
-1
|
||||
};
|
||||
|
||||
/* Four Transfer Controllers on DM646x */
|
||||
static const s8
|
||||
dm646x_queue_tc_mapping[][2] = {
|
||||
|
|
@ -549,7 +539,6 @@ static struct edma_soc_info dm646x_edma_info[] = {
|
|||
.n_slot = 512,
|
||||
.n_tc = 4,
|
||||
.n_cc = 1,
|
||||
.noevent = dma_chan_dm646x_no_event,
|
||||
.queue_tc_mapping = dm646x_queue_tc_mapping,
|
||||
.queue_priority_mapping = dm646x_queue_priority_mapping,
|
||||
},
|
||||
|
|
@ -925,6 +914,7 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
|
|||
|
||||
void __init dm646x_init(void)
|
||||
{
|
||||
dm646x_board_setup_refclk(&ref_clk);
|
||||
davinci_common_init(&davinci_soc_info_dm646x);
|
||||
}
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue