KVM: PPC: e500: don't use MAS0 as intermediate storage.
This avoids races. It also means that we use the shadow TLB way, rather than the hardware hint -- if this is a problem, we could do a tlbsx before inserting a TLB0 entry. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -112,13 +112,18 @@ static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode)
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/*
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/*
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* writing shadow tlb entry to host TLB
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* writing shadow tlb entry to host TLB
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*/
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*/
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static inline void __write_host_tlbe(struct tlbe *stlbe)
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static inline void __write_host_tlbe(struct tlbe *stlbe, uint32_t mas0)
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{
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{
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unsigned long flags;
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local_irq_save(flags);
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mtspr(SPRN_MAS0, mas0);
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mtspr(SPRN_MAS1, stlbe->mas1);
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mtspr(SPRN_MAS1, stlbe->mas1);
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mtspr(SPRN_MAS2, stlbe->mas2);
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mtspr(SPRN_MAS2, stlbe->mas2);
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mtspr(SPRN_MAS3, stlbe->mas3);
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mtspr(SPRN_MAS3, stlbe->mas3);
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mtspr(SPRN_MAS7, stlbe->mas7);
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mtspr(SPRN_MAS7, stlbe->mas7);
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__asm__ __volatile__ ("tlbwe\n" : : );
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asm volatile("isync; tlbwe" : : : "memory");
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local_irq_restore(flags);
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}
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}
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static inline void write_host_tlbe(struct kvmppc_vcpu_e500 *vcpu_e500,
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static inline void write_host_tlbe(struct kvmppc_vcpu_e500 *vcpu_e500,
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@ -126,20 +131,15 @@ static inline void write_host_tlbe(struct kvmppc_vcpu_e500 *vcpu_e500,
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{
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{
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struct tlbe *stlbe = &vcpu_e500->shadow_tlb[tlbsel][esel];
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struct tlbe *stlbe = &vcpu_e500->shadow_tlb[tlbsel][esel];
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local_irq_disable();
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if (tlbsel == 0) {
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if (tlbsel == 0) {
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__write_host_tlbe(stlbe);
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__write_host_tlbe(stlbe,
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MAS0_TLBSEL(0) |
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MAS0_ESEL(esel & (KVM_E500_TLB0_WAY_NUM - 1)));
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} else {
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} else {
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unsigned register mas0;
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__write_host_tlbe(stlbe,
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MAS0_TLBSEL(1) |
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mas0 = mfspr(SPRN_MAS0);
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MAS0_ESEL(to_htlb1_esel(esel)));
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mtspr(SPRN_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(to_htlb1_esel(esel)));
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__write_host_tlbe(stlbe);
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mtspr(SPRN_MAS0, mas0);
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}
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}
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local_irq_enable();
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}
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}
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void kvmppc_e500_tlb_load(struct kvm_vcpu *vcpu, int cpu)
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void kvmppc_e500_tlb_load(struct kvm_vcpu *vcpu, int cpu)
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