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davinci: Move pinmux setup info to SoC infrastructure 

The pinmux register base and setup can be different for different
SoCs so move the pinmux reg base, pinmux table (and its size) to
the SoC infrastructure.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Mark A. Greer 2009-04-15 12:39:48 -07:00 committed by Kevin Hilman
parent d81d188caf
commit 0e585952ac
6 changed files with 25 additions and 26 deletions
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6
arch/arm/mach-davinci/dm355.c
View File

@ -436,6 +436,7 @@ void __init dm355_init_spi0(unsigned chipselect_mask,
* reg offset mask mode
*/
static const struct mux_config dm355_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
@ -466,6 +467,7 @@ INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
#endif
};
/*----------------------------------------------------------------------*/
@ -558,12 +560,14 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
.cpu_clks = dm355_clks,
.psc_bases = dm355_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
.pinmux_pins = dm355_pins,
.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
};
void __init dm355_init(void)
{
davinci_common_init(&davinci_soc_info_dm355);
davinci_mux_register(dm355_pins, ARRAY_SIZE(dm355_pins));;
}
static int __init dm355_init_devices(void)

6
arch/arm/mach-davinci/dm644x.c
View File

@ -346,6 +346,7 @@ static struct platform_device dm644x_emac_device = {
* reg offset mask mode
*/
static const struct mux_config dm644x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
@ -386,6 +387,7 @@ MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
#endif
};
/*----------------------------------------------------------------------*/
@ -498,12 +500,14 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
.cpu_clks = dm644x_clks,
.psc_bases = dm644x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
.pinmux_pins = dm644x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
};
void __init dm644x_init(void)
{
davinci_common_init(&davinci_soc_info_dm644x);
davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins));
}
static int __init dm644x_init_devices(void)

6
arch/arm/mach-davinci/dm646x.c
View File

@ -327,6 +327,7 @@ static struct platform_device dm646x_emac_device = {
* reg offset mask mode
*/
static const struct mux_config dm646x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
@ -354,6 +355,7 @@ MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
#endif
};
/*----------------------------------------------------------------------*/
@ -478,12 +480,14 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
.cpu_clks = dm646x_clks,
.psc_bases = dm646x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
.pinmux_pins = dm646x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
};
void __init dm646x_init(void)
{
davinci_common_init(&davinci_soc_info_dm646x);
davinci_mux_register(dm646x_pins, ARRAY_SIZE(dm646x_pins));
}
static int __init dm646x_init_devices(void)

3
arch/arm/mach-davinci/include/mach/common.h
View File

@ -36,6 +36,9 @@ struct davinci_soc_info {
struct davinci_clk *cpu_clks;
void __iomem **psc_bases;
unsigned long psc_bases_num;
void __iomem *pinmux_base;
const struct mux_config *pinmux_pins;
unsigned long pinmux_pins_num;
};
extern struct davinci_soc_info davinci_soc_info;

6
arch/arm/mach-davinci/include/mach/mux.h
View File

@ -168,15 +168,9 @@ enum davinci_dm355_index {
#ifdef CONFIG_DAVINCI_MUX
/* setup pin muxing */
extern void davinci_mux_init(void);
extern int davinci_mux_register(const struct mux_config *pins,
unsigned long size);
extern int davinci_cfg_reg(unsigned long reg_cfg);
#else
/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
static inline void davinci_mux_init(void) {}
static inline int davinci_mux_register(const struct mux_config *pins,
unsigned long size) { return 0; }
static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
#endif

24
arch/arm/mach-davinci/mux.c
View File

@ -21,18 +21,7 @@
#include <mach/hardware.h>
#include <mach/mux.h>
static const struct mux_config *mux_table;
static unsigned long pin_table_sz;
int __init davinci_mux_register(const struct mux_config *pins,
unsigned long size)
{
mux_table = pins;
pin_table_sz = size;
return 0;
}
#include <mach/common.h>
/*
* Sets the DAVINCI MUX register based on the table
@ -40,23 +29,24 @@ int __init davinci_mux_register(const struct mux_config *pins,
int __init_or_module davinci_cfg_reg(const unsigned long index)
{
static DEFINE_SPINLOCK(mux_spin_lock);
void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
struct davinci_soc_info *soc_info = &davinci_soc_info;
void __iomem *base = soc_info->pinmux_base;
unsigned long flags;
const struct mux_config *cfg;
unsigned int reg_orig = 0, reg = 0;
unsigned int mask, warn = 0;
if (!mux_table)
if (!soc_info->pinmux_pins)
BUG();
if (index >= pin_table_sz) {
if (index >= soc_info->pinmux_pins_num) {
printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
index, pin_table_sz);
index, soc_info->pinmux_pins_num);
dump_stack();
return -ENODEV;
}
cfg = &mux_table[index];
cfg = &soc_info->pinmux_pins[index];
if (cfg->name == NULL) {
printk(KERN_ERR "No entry for the specified index\n");