MIPS: TXx9: Add TX4939 SoC support
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/pci/pci-tx4939.c create mode 100644 arch/mips/txx9/generic/irq_tx4939.c create mode 100644 arch/mips/txx9/generic/setup_tx4939.c create mode 100644 include/asm-mips/txx9/tx4939.h
This commit is contained in:
Atsushi Nemoto
Ralf Baechle
parent
ae027ead87
commit
0dcdbe6add
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@ -45,6 +45,7 @@ obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
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obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o
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obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
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obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
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obj-$(CONFIG_SOC_TX4939) += pci-tx4939.o
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obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
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obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
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obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
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@ -0,0 +1,109 @@
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/*
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* linux/arch/mips/pci/pci-tx4939.c
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*
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* Based on linux/arch/mips/txx9/rbtx4939/setup.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* Copyright 2001, 2003-2005 MontaVista Software Inc.
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/tx4939.h>
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int __init tx4939_report_pciclk(void)
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{
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int pciclk = 0;
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pr_info("PCIC --%s PCICLK:",
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(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66) ?
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" PCI66" : "");
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if (__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_PCICLKEN_ALL) {
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pciclk = txx9_master_clock * 20 / 6;
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if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
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pciclk /= 2;
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printk(KERN_CONT "Internal(%u.%uMHz)",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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} else {
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printk(KERN_CONT "External");
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pciclk = -1;
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}
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printk(KERN_CONT "\n");
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return pciclk;
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}
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void __init tx4939_report_pci1clk(void)
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{
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unsigned int pciclk = txx9_master_clock * 20 / 6;
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pr_info("PCIC1 -- PCICLK:%u.%uMHz\n",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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}
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int __init tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
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{
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if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) {
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switch (slot) {
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case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
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if (__raw_readq(&tx4939_ccfgptr->pcfg) &
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TX4939_PCFG_ET0MODE)
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return TXX9_IRQ_BASE + TX4939_IR_ETH(0);
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break;
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case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
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if (__raw_readq(&tx4939_ccfgptr->pcfg) &
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TX4939_PCFG_ET1MODE)
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return TXX9_IRQ_BASE + TX4939_IR_ETH(1);
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break;
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}
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return 0;
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}
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return -1;
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}
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int __init tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq = tx4939_pcic1_map_irq(dev, slot);
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if (irq >= 0)
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return irq;
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irq = pin;
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/* IRQ rotation */
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irq--; /* 0-3 */
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irq = (irq + 33 - slot) % 4;
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irq++; /* 1-4 */
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switch (irq) {
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case 1:
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irq = TXX9_IRQ_BASE + TX4939_IR_INTA;
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break;
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case 2:
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irq = TXX9_IRQ_BASE + TX4939_IR_INTB;
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break;
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case 3:
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irq = TXX9_IRQ_BASE + TX4939_IR_INTC;
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break;
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case 4:
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irq = TXX9_IRQ_BASE + TX4939_IR_INTD;
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break;
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}
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return irq;
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}
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void __init tx4939_setup_pcierr_irq(void)
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{
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if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR,
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tx4927_pcierr_interrupt,
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IRQF_DISABLED, "PCI error",
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(void *)TX4939_PCIC_REG))
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pr_warning("Failed to request irq for PCIERR\n");
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}
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@ -71,6 +71,13 @@ config SOC_TX4938
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select PCI_TX4927
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select GPIO_TXX9
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config SOC_TX4939
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bool
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select CEVT_TXX9
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select HAS_TXX9_SERIAL
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select HW_HAS_PCI
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select PCI_TX4927
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config TOSHIBA_FPCIB0
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bool "FPCIB0 Backplane Support"
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depends on PCI && MACH_TXX9
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@ -7,6 +7,7 @@ obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o
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obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
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obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
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obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
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obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
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obj-$(CONFIG_SPI) += spi_eeprom.o
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@ -0,0 +1,215 @@
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/*
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* TX4939 irq routines
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* Based on linux/arch/mips/kernel/irq_txx9.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* Copyright 2001, 2003-2005 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ahennessy@mvista.com
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* source@mvista.com
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* Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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/*
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* TX4939 defines 64 IRQs.
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* Similer to irq_txx9.c but different register layouts.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <asm/irq_cpu.h>
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#include <asm/txx9irq.h>
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#include <asm/txx9/tx4939.h>
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/* IRCER : Int. Control Enable */
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#define TXx9_IRCER_ICE 0x00000001
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/* IRCR : Int. Control */
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#define TXx9_IRCR_LOW 0x00000000
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#define TXx9_IRCR_HIGH 0x00000001
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#define TXx9_IRCR_DOWN 0x00000002
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#define TXx9_IRCR_UP 0x00000003
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#define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
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/* IRSCR : Int. Status Control */
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#define TXx9_IRSCR_EIClrE 0x00000100
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#define TXx9_IRSCR_EIClr_MASK 0x0000000f
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/* IRCSR : Int. Current Status */
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#define TXx9_IRCSR_IF 0x00010000
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#define irc_dlevel 0
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#define irc_elevel 1
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static struct {
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unsigned char level;
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unsigned char mode;
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} tx4939irq[TX4939_NUM_IR] __read_mostly;
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static void tx4939_irq_unmask(unsigned int irq)
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{
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unsigned int irq_nr = irq - TXX9_IRQ_BASE;
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u32 __iomem *lvlp;
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int ofs;
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if (irq_nr < 32) {
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irq_nr--;
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lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
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} else {
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irq_nr -= 32;
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lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
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}
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ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
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__raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
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| (tx4939irq[irq_nr].level << ofs),
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lvlp);
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}
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static inline void tx4939_irq_mask(unsigned int irq)
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{
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unsigned int irq_nr = irq - TXX9_IRQ_BASE;
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u32 __iomem *lvlp;
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int ofs;
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if (irq_nr < 32) {
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irq_nr--;
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lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
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} else {
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irq_nr -= 32;
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lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
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}
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ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
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__raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
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| (irc_dlevel << ofs),
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lvlp);
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mmiowb();
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}
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static void tx4939_irq_mask_ack(unsigned int irq)
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{
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unsigned int irq_nr = irq - TXX9_IRQ_BASE;
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tx4939_irq_mask(irq);
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if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) {
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irq_nr--;
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/* clear edge detection */
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__raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf))
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<< (irq_nr & 0x10),
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&tx4939_ircptr->edc.r);
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}
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}
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static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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unsigned int irq_nr = irq - TXX9_IRQ_BASE;
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u32 cr;
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u32 __iomem *crp;
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int ofs;
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int mode;
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if (flow_type & IRQF_TRIGGER_PROBE)
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return 0;
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switch (flow_type & IRQF_TRIGGER_MASK) {
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case IRQF_TRIGGER_RISING:
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mode = TXx9_IRCR_UP;
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break;
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case IRQF_TRIGGER_FALLING:
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mode = TXx9_IRCR_DOWN;
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break;
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case IRQF_TRIGGER_HIGH:
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mode = TXx9_IRCR_HIGH;
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break;
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case IRQF_TRIGGER_LOW:
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mode = TXx9_IRCR_LOW;
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break;
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default:
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return -EINVAL;
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}
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if (irq_nr < 32) {
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irq_nr--;
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crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r;
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} else {
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irq_nr -= 32;
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crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r;
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}
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ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2;
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cr = __raw_readl(crp);
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cr &= ~(0x3 << ofs);
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cr |= (mode & 0x3) << ofs;
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__raw_writel(cr, crp);
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tx4939irq[irq_nr].mode = mode;
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return 0;
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}
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static struct irq_chip tx4939_irq_chip = {
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.name = "TX4939",
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.ack = tx4939_irq_mask_ack,
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.mask = tx4939_irq_mask,
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.mask_ack = tx4939_irq_mask_ack,
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.unmask = tx4939_irq_unmask,
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.set_type = tx4939_irq_set_type,
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};
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static int tx4939_irq_set_pri(int irc_irq, int new_pri)
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{
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int old_pri;
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if ((unsigned int)irc_irq >= TX4939_NUM_IR)
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return 0;
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old_pri = tx4939irq[irc_irq].level;
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tx4939irq[irc_irq].level = new_pri;
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return old_pri;
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}
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void __init tx4939_irq_init(void)
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{
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int i;
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mips_cpu_irq_init();
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/* disable interrupt control */
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__raw_writel(0, &tx4939_ircptr->den.r);
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__raw_writel(0, &tx4939_ircptr->maskint.r);
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__raw_writel(0, &tx4939_ircptr->maskext.r);
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/* irq_base + 0 is not used */
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for (i = 1; i < TX4939_NUM_IR; i++) {
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tx4939irq[i].level = 4; /* middle level */
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tx4939irq[i].mode = TXx9_IRCR_LOW;
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set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
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&tx4939_irq_chip, handle_level_irq);
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}
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/* mask all IRC interrupts */
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__raw_writel(0, &tx4939_ircptr->msk.r);
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for (i = 0; i < 16; i++)
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__raw_writel(0, &tx4939_ircptr->lvl[i].r);
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/* setup IRC interrupt mode (Low Active) */
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for (i = 0; i < 2; i++)
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__raw_writel(0, &tx4939_ircptr->dm[i].r);
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for (i = 0; i < 2; i++)
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__raw_writel(0, &tx4939_ircptr->dm2[i].r);
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/* enable interrupt control */
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__raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
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__raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
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set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
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handle_simple_irq);
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/* raise priority for errors, timers, sio */
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tx4939_irq_set_pri(TX4939_IR_WTOERR, 7);
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tx4939_irq_set_pri(TX4939_IR_PCIERR, 7);
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tx4939_irq_set_pri(TX4939_IR_PCIPME, 7);
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for (i = 0; i < TX4939_NUM_IR_TMR; i++)
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tx4939_irq_set_pri(TX4939_IR_TMR(i), 6);
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for (i = 0; i < TX4939_NUM_IR_SIO; i++)
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tx4939_irq_set_pri(TX4939_IR_SIO(i), 5);
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}
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int tx4939_irq(void)
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{
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u32 csr = __raw_readl(&tx4939_ircptr->cs.r);
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if (likely(!(csr & TXx9_IRCSR_IF)))
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return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1));
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return -1;
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}
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@ -0,0 +1,460 @@
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/*
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* TX4939 setup routines
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* Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* 2003-2005 (c) MontaVista Software, Inc.
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* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/notifier.h>
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#include <linux/sysdev.h>
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#include <linux/ethtool.h>
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#include <linux/param.h>
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#include <linux/ptrace.h>
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#include <linux/mtd/physmap.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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#include <asm/traps.h>
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#include <asm/txx9irq.h>
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#include <asm/txx9tmr.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/tx4939.h>
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static void __init tx4939_wdr_init(void)
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{
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/* report watchdog reset status */
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if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
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pr_warning("Watchdog reset detected at 0x%lx\n",
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read_c0_errorepc());
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/* clear WatchDogReset (W1C) */
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tx4939_ccfg_set(TX4939_CCFG_WDRST);
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/* do reset on watchdog */
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tx4939_ccfg_set(TX4939_CCFG_WR);
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}
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void __init tx4939_wdt_init(void)
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{
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txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
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}
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static void tx4939_machine_restart(char *command)
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{
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local_irq_disable();
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pr_emerg("Rebooting (with %s watchdog reset)...\n",
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(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
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"external" : "internal");
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/* clear watchdog status */
|
||||
tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
|
||||
txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
|
||||
while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
|
||||
;
|
||||
mdelay(10);
|
||||
if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
|
||||
pr_emerg("Rebooting (with internal watchdog reset)...\n");
|
||||
/* External WDRST failed. Do internal watchdog reset */
|
||||
tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
|
||||
}
|
||||
/* fallback */
|
||||
(*_machine_halt)();
|
||||
}
|
||||
|
||||
void show_registers(struct pt_regs *regs);
|
||||
static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
|
||||
{
|
||||
int data = regs->cp0_cause & 4;
|
||||
console_verbose();
|
||||
pr_err("%cBE exception at %#lx\n",
|
||||
data ? 'D' : 'I', regs->cp0_epc);
|
||||
pr_err("ccfg:%llx, toea:%llx\n",
|
||||
(unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
|
||||
(unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
|
||||
#ifdef CONFIG_PCI
|
||||
tx4927_report_pcic_status();
|
||||
#endif
|
||||
show_registers(regs);
|
||||
panic("BusError!");
|
||||
}
|
||||
static void __init tx4939_be_init(void)
|
||||
{
|
||||
board_be_handler = tx4939_be_handler;
|
||||
}
|
||||
|
||||
static struct resource tx4939_sdram_resource[4];
|
||||
static struct resource tx4939_sram_resource;
|
||||
#define TX4939_SRAM_SIZE 0x800
|
||||
|
||||
void __init tx4939_add_memory_regions(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long start, size;
|
||||
u64 win;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
|
||||
continue;
|
||||
win = ____raw_readq(&tx4939_ddrcptr->win[i]);
|
||||
start = (unsigned long)(win >> 48);
|
||||
size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
|
||||
add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
|
||||
}
|
||||
}
|
||||
|
||||
void __init tx4939_setup(void)
|
||||
{
|
||||
int i;
|
||||
__u32 divmode;
|
||||
__u64 pcfg;
|
||||
int cpuclk = 0;
|
||||
|
||||
txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
|
||||
TX4939_REG_SIZE);
|
||||
set_c0_config(TX49_CONF_CWFON);
|
||||
|
||||
/* SDRAMC,EBUSC are configured by PROM */
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (!(TX4939_EBUSC_CR(i) & 0x8))
|
||||
continue; /* disabled */
|
||||
txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
|
||||
txx9_ce_res[i].end =
|
||||
txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
|
||||
request_resource(&iomem_resource, &txx9_ce_res[i]);
|
||||
}
|
||||
|
||||
/* clocks */
|
||||
if (txx9_master_clock) {
|
||||
/* calculate cpu_clock from master_clock */
|
||||
divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
|
||||
TX4939_CCFG_MULCLK_MASK;
|
||||
cpuclk = txx9_master_clock * 20 / 2;
|
||||
switch (divmode) {
|
||||
case TX4939_CCFG_MULCLK_8:
|
||||
cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
|
||||
case TX4939_CCFG_MULCLK_9:
|
||||
cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
|
||||
case TX4939_CCFG_MULCLK_10:
|
||||
cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
|
||||
case TX4939_CCFG_MULCLK_11:
|
||||
cpuclk = cpuclk / 6 * 11; break;
|
||||
case TX4939_CCFG_MULCLK_12:
|
||||
cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
|
||||
case TX4939_CCFG_MULCLK_13:
|
||||
cpuclk = cpuclk / 6 * 13; break;
|
||||
case TX4939_CCFG_MULCLK_14:
|
||||
cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
|
||||
case TX4939_CCFG_MULCLK_15:
|
||||
cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
|
||||
}
|
||||
txx9_cpu_clock = cpuclk;
|
||||
} else {
|
||||
if (txx9_cpu_clock == 0)
|
||||
txx9_cpu_clock = 400000000; /* 400MHz */
|
||||
/* calculate master_clock from cpu_clock */
|
||||
cpuclk = txx9_cpu_clock;
|
||||
divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
|
||||
TX4939_CCFG_MULCLK_MASK;
|
||||
switch (divmode) {
|
||||
case TX4939_CCFG_MULCLK_8:
|
||||
txx9_master_clock = cpuclk * 6 / 8; break;
|
||||
case TX4939_CCFG_MULCLK_9:
|
||||
txx9_master_clock = cpuclk * 6 / 9; break;
|
||||
case TX4939_CCFG_MULCLK_10:
|
||||
txx9_master_clock = cpuclk * 6 / 10; break;
|
||||
case TX4939_CCFG_MULCLK_11:
|
||||
txx9_master_clock = cpuclk * 6 / 11; break;
|
||||
case TX4939_CCFG_MULCLK_12:
|
||||
txx9_master_clock = cpuclk * 6 / 12; break;
|
||||
case TX4939_CCFG_MULCLK_13:
|
||||
txx9_master_clock = cpuclk * 6 / 13; break;
|
||||
case TX4939_CCFG_MULCLK_14:
|
||||
txx9_master_clock = cpuclk * 6 / 14; break;
|
||||
case TX4939_CCFG_MULCLK_15:
|
||||
txx9_master_clock = cpuclk * 6 / 15; break;
|
||||
}
|
||||
txx9_master_clock /= 10; /* * 2 / 20 */
|
||||
}
|
||||
/* calculate gbus_clock from cpu_clock */
|
||||
divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
|
||||
TX4939_CCFG_YDIVMODE_MASK;
|
||||
txx9_gbus_clock = txx9_cpu_clock;
|
||||
switch (divmode) {
|
||||
case TX4939_CCFG_YDIVMODE_2:
|
||||
txx9_gbus_clock /= 2; break;
|
||||
case TX4939_CCFG_YDIVMODE_3:
|
||||
txx9_gbus_clock /= 3; break;
|
||||
case TX4939_CCFG_YDIVMODE_5:
|
||||
txx9_gbus_clock /= 5; break;
|
||||
case TX4939_CCFG_YDIVMODE_6:
|
||||
txx9_gbus_clock /= 6; break;
|
||||
}
|
||||
/* change default value to udelay/mdelay take reasonable time */
|
||||
loops_per_jiffy = txx9_cpu_clock / HZ / 2;
|
||||
|
||||
/* CCFG */
|
||||
tx4939_wdr_init();
|
||||
/* clear BusErrorOnWrite flag (W1C) */
|
||||
tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
|
||||
/* enable Timeout BusError */
|
||||
if (txx9_ccfg_toeon)
|
||||
tx4939_ccfg_set(TX4939_CCFG_TOE);
|
||||
|
||||
/* DMA selection */
|
||||
txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
|
||||
|
||||
/* Use external clock for external arbiter */
|
||||
if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
|
||||
txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
|
||||
|
||||
pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
|
||||
txx9_pcode_str,
|
||||
(cpuclk + 500000) / 1000000,
|
||||
(txx9_master_clock + 500000) / 1000000,
|
||||
(txx9_gbus_clock + 500000) / 1000000,
|
||||
(__u32)____raw_readq(&tx4939_ccfgptr->crir),
|
||||
(unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
|
||||
(unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
|
||||
|
||||
pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
|
||||
(__u32)____raw_readq(&tx4939_ddrcptr->winen));
|
||||
for (i = 0; i < 4; i++) {
|
||||
__u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
|
||||
if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
|
||||
continue; /* disabled */
|
||||
printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
|
||||
tx4939_sdram_resource[i].name = "DDR SDRAM";
|
||||
tx4939_sdram_resource[i].start =
|
||||
(unsigned long)(win >> 48) << 20;
|
||||
tx4939_sdram_resource[i].end =
|
||||
((((unsigned long)(win >> 32) & 0xffff) + 1) <<
|
||||
20) - 1;
|
||||
tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
|
||||
request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
|
||||
}
|
||||
printk(KERN_CONT "\n");
|
||||
|
||||
/* SRAM */
|
||||
if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
|
||||
unsigned int size = TX4939_SRAM_SIZE;
|
||||
tx4939_sram_resource.name = "SRAM";
|
||||
tx4939_sram_resource.start =
|
||||
(____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
|
||||
& ~(size - 1);
|
||||
tx4939_sram_resource.end =
|
||||
tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
|
||||
tx4939_sram_resource.flags = IORESOURCE_MEM;
|
||||
request_resource(&iomem_resource, &tx4939_sram_resource);
|
||||
}
|
||||
|
||||
/* TMR */
|
||||
/* disable all timers */
|
||||
for (i = 0; i < TX4939_NR_TMR; i++)
|
||||
txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
|
||||
|
||||
/* DMA */
|
||||
for (i = 0; i < 2; i++)
|
||||
____raw_writeq(TX4938_DMA_MCR_MSTEN,
|
||||
(void __iomem *)(TX4939_DMA_REG(i) + 0x50));
|
||||
|
||||
/* set PCIC1 reset (required to prevent hangup on BIST) */
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
|
||||
pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
|
||||
if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
|
||||
mdelay(1); /* at least 128 cpu clock */
|
||||
/* clear PCIC1 reset */
|
||||
txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
|
||||
} else {
|
||||
pr_info("%s: stop PCIC1\n", txx9_pcode_str);
|
||||
/* stop PCIC1 */
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
|
||||
}
|
||||
if (!(pcfg & TX4939_PCFG_ET0MODE)) {
|
||||
pr_info("%s: stop ETH0\n", txx9_pcode_str);
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
|
||||
}
|
||||
if (!(pcfg & TX4939_PCFG_ET1MODE)) {
|
||||
pr_info("%s: stop ETH1\n", txx9_pcode_str);
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
|
||||
}
|
||||
|
||||
_machine_restart = tx4939_machine_restart;
|
||||
board_be_init = tx4939_be_init;
|
||||
}
|
||||
|
||||
void __init tx4939_time_init(unsigned int tmrnr)
|
||||
{
|
||||
if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
|
||||
txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
|
||||
TXX9_IMCLK);
|
||||
}
|
||||
|
||||
void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
|
||||
{
|
||||
int i;
|
||||
unsigned int ch_mask = 0;
|
||||
__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
|
||||
|
||||
cts_mask |= ~1; /* only SIO0 have RTS/CTS */
|
||||
if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
|
||||
cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
|
||||
if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
|
||||
ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
|
||||
if (pcfg & TX4939_PCFG_SIO3MODE)
|
||||
ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
|
||||
for (i = 0; i < 4; i++) {
|
||||
if ((1 << i) & ch_mask)
|
||||
continue;
|
||||
txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4939_IR_SIO(i),
|
||||
i, sclk, (1 << i) & cts_mask);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
|
||||
static int tx4939_get_eth_speed(struct net_device *dev)
|
||||
{
|
||||
struct ethtool_cmd cmd = { ETHTOOL_GSET };
|
||||
int speed = 100; /* default 100Mbps */
|
||||
int err;
|
||||
if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings)
|
||||
return speed;
|
||||
err = dev->ethtool_ops->get_settings(dev, &cmd);
|
||||
if (err < 0)
|
||||
return speed;
|
||||
speed = cmd.speed == SPEED_100 ? 100 : 10;
|
||||
return speed;
|
||||
}
|
||||
static int tx4939_netdev_event(struct notifier_block *this,
|
||||
unsigned long event,
|
||||
void *ptr)
|
||||
{
|
||||
struct net_device *dev = ptr;
|
||||
if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
|
||||
__u64 bit = 0;
|
||||
if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
|
||||
bit = TX4939_PCFG_SPEED0;
|
||||
else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
|
||||
bit = TX4939_PCFG_SPEED1;
|
||||
if (bit) {
|
||||
int speed = tx4939_get_eth_speed(dev);
|
||||
if (speed == 100)
|
||||
txx9_set64(&tx4939_ccfgptr->pcfg, bit);
|
||||
else
|
||||
txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
|
||||
}
|
||||
}
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block tx4939_netdev_notifier = {
|
||||
.notifier_call = tx4939_netdev_event,
|
||||
.priority = 1,
|
||||
};
|
||||
|
||||
void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
|
||||
{
|
||||
u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
|
||||
|
||||
if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
|
||||
txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
|
||||
if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
|
||||
txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
|
||||
register_netdevice_notifier(&tx4939_netdev_notifier);
|
||||
}
|
||||
#else
|
||||
void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
void __init tx4939_mtd_init(int ch)
|
||||
{
|
||||
struct physmap_flash_data pdata = {
|
||||
.width = TX4939_EBUSC_WIDTH(ch) / 8,
|
||||
};
|
||||
unsigned long start = txx9_ce_res[ch].start;
|
||||
unsigned long size = txx9_ce_res[ch].end - start + 1;
|
||||
|
||||
if (!(TX4939_EBUSC_CR(ch) & 0x8))
|
||||
return; /* disabled */
|
||||
txx9_physmap_flash_init(ch, start, size, &pdata);
|
||||
}
|
||||
|
||||
static void __init tx4939_stop_unused_modules(void)
|
||||
{
|
||||
__u64 pcfg, rst = 0, ckd = 0;
|
||||
char buf[128];
|
||||
|
||||
buf[0] = '\0';
|
||||
local_irq_disable();
|
||||
pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
|
||||
if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
|
||||
TX4939_PCFG_I2SMODE_ACLC) {
|
||||
rst |= TX4939_CLKCTR_ACLRST;
|
||||
ckd |= TX4939_CLKCTR_ACLCKD;
|
||||
strcat(buf, " ACLC");
|
||||
}
|
||||
if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
|
||||
TX4939_PCFG_I2SMODE_I2S &&
|
||||
(pcfg & TX4939_PCFG_I2SMODE_MASK) !=
|
||||
TX4939_PCFG_I2SMODE_I2S_ALT) {
|
||||
rst |= TX4939_CLKCTR_I2SRST;
|
||||
ckd |= TX4939_CLKCTR_I2SCKD;
|
||||
strcat(buf, " I2S");
|
||||
}
|
||||
if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
|
||||
rst |= TX4939_CLKCTR_ATA0RST;
|
||||
ckd |= TX4939_CLKCTR_ATA0CKD;
|
||||
strcat(buf, " ATA0");
|
||||
}
|
||||
if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
|
||||
rst |= TX4939_CLKCTR_ATA1RST;
|
||||
ckd |= TX4939_CLKCTR_ATA1CKD;
|
||||
strcat(buf, " ATA1");
|
||||
}
|
||||
if (pcfg & TX4939_PCFG_SPIMODE) {
|
||||
rst |= TX4939_CLKCTR_SPIRST;
|
||||
ckd |= TX4939_CLKCTR_SPICKD;
|
||||
strcat(buf, " SPI");
|
||||
}
|
||||
if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
|
||||
rst |= TX4939_CLKCTR_VPCRST;
|
||||
ckd |= TX4939_CLKCTR_VPCCKD;
|
||||
strcat(buf, " VPC");
|
||||
}
|
||||
if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
|
||||
rst |= TX4939_CLKCTR_SIO2RST;
|
||||
ckd |= TX4939_CLKCTR_SIO2CKD;
|
||||
strcat(buf, " SIO2");
|
||||
}
|
||||
if (pcfg & TX4939_PCFG_SIO3MODE) {
|
||||
rst |= TX4939_CLKCTR_SIO3RST;
|
||||
ckd |= TX4939_CLKCTR_SIO3CKD;
|
||||
strcat(buf, " SIO3");
|
||||
}
|
||||
if (rst | ckd) {
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, rst);
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
|
||||
}
|
||||
local_irq_enable();
|
||||
if (buf[0])
|
||||
pr_info("%s: stop%s\n", txx9_pcode_str, buf);
|
||||
}
|
||||
|
||||
static int __init tx4939_late_init(void)
|
||||
{
|
||||
if (txx9_pcode != 0x4939)
|
||||
return -ENODEV;
|
||||
tx4939_stop_unused_modules();
|
||||
return 0;
|
||||
}
|
||||
late_initcall(tx4939_late_init);
|
||||
|
|
@ -0,0 +1,544 @@
|
|||
/*
|
||||
* Definitions for TX4939
|
||||
*
|
||||
* Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#ifndef __ASM_TXX9_TX4939_H
|
||||
#define __ASM_TXX9_TX4939_H
|
||||
|
||||
/* some controllers are compatible with 4927/4938 */
|
||||
#include <asm/txx9/tx4938.h>
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
|
||||
#else
|
||||
#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
|
||||
#endif
|
||||
#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
|
||||
|
||||
#define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
|
||||
#define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000)
|
||||
#define TX4939_SRAMC_REG (TX4939_REG_BASE + 0x6000)
|
||||
#define TX4939_CRYPTO_REG (TX4939_REG_BASE + 0x6800)
|
||||
#define TX4939_PCIC1_REG (TX4939_REG_BASE + 0x7000)
|
||||
#define TX4939_DDRC_REG (TX4939_REG_BASE + 0x8000)
|
||||
#define TX4939_EBUSC_REG (TX4939_REG_BASE + 0x9000)
|
||||
#define TX4939_VPC_REG (TX4939_REG_BASE + 0xa000)
|
||||
#define TX4939_DMA_REG(ch) (TX4939_REG_BASE + 0xb000 + (ch) * 0x800)
|
||||
#define TX4939_PCIC_REG (TX4939_REG_BASE + 0xd000)
|
||||
#define TX4939_CCFG_REG (TX4939_REG_BASE + 0xe000)
|
||||
#define TX4939_IRC_REG (TX4939_REG_BASE + 0xe800)
|
||||
#define TX4939_NR_TMR 6 /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */
|
||||
#define TX4939_TMR_REG(ch) \
|
||||
(TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100)
|
||||
#define TX4939_NR_SIO 4 /* 0xf300, 0xf400, 0xf380, 0xf480 */
|
||||
#define TX4939_SIO_REG(ch) \
|
||||
(TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6))
|
||||
#define TX4939_ACLC_REG (TX4939_REG_BASE + 0xf700)
|
||||
#define TX4939_SPI_REG (TX4939_REG_BASE + 0xf800)
|
||||
#define TX4939_I2C_REG (TX4939_REG_BASE + 0xf900)
|
||||
#define TX4939_I2S_REG (TX4939_REG_BASE + 0xfa00)
|
||||
#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00)
|
||||
#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00)
|
||||
|
||||
struct tx4939_le_reg {
|
||||
__u32 r;
|
||||
__u32 unused;
|
||||
};
|
||||
|
||||
struct tx4939_ddrc_reg {
|
||||
struct tx4939_le_reg ctl[47];
|
||||
__u64 unused0[17];
|
||||
__u64 winen;
|
||||
__u64 win[4];
|
||||
};
|
||||
|
||||
struct tx4939_ccfg_reg {
|
||||
__u64 ccfg;
|
||||
__u64 crir;
|
||||
__u64 pcfg;
|
||||
__u64 toea;
|
||||
__u64 clkctr;
|
||||
__u64 unused0;
|
||||
__u64 garbc;
|
||||
__u64 unused1[2];
|
||||
__u64 ramp;
|
||||
__u64 unused2[2];
|
||||
__u64 dskwctrl;
|
||||
__u64 mclkosc;
|
||||
__u64 mclkctl;
|
||||
__u64 unused3[17];
|
||||
struct {
|
||||
__u64 mr;
|
||||
__u64 dr;
|
||||
} gpio[2];
|
||||
};
|
||||
|
||||
struct tx4939_irc_reg {
|
||||
struct tx4939_le_reg den;
|
||||
struct tx4939_le_reg scipb;
|
||||
struct tx4939_le_reg dm[2];
|
||||
struct tx4939_le_reg lvl[16];
|
||||
struct tx4939_le_reg msk;
|
||||
struct tx4939_le_reg edc;
|
||||
struct tx4939_le_reg pnd0;
|
||||
struct tx4939_le_reg cs;
|
||||
struct tx4939_le_reg pnd1;
|
||||
struct tx4939_le_reg dm2[2];
|
||||
struct tx4939_le_reg dbr[2];
|
||||
struct tx4939_le_reg dben;
|
||||
struct tx4939_le_reg unused0[2];
|
||||
struct tx4939_le_reg flag[2];
|
||||
struct tx4939_le_reg pol;
|
||||
struct tx4939_le_reg cnt;
|
||||
struct tx4939_le_reg maskint;
|
||||
struct tx4939_le_reg maskext;
|
||||
};
|
||||
|
||||
struct tx4939_rtc_reg {
|
||||
__u32 ctl;
|
||||
__u32 adr;
|
||||
__u32 dat;
|
||||
__u32 tbc;
|
||||
};
|
||||
|
||||
struct tx4939_crypto_reg {
|
||||
struct tx4939_le_reg csr;
|
||||
struct tx4939_le_reg idesptr;
|
||||
struct tx4939_le_reg cdesptr;
|
||||
struct tx4939_le_reg buserr;
|
||||
struct tx4939_le_reg cip_tout;
|
||||
struct tx4939_le_reg cir;
|
||||
union {
|
||||
struct {
|
||||
struct tx4939_le_reg data[8];
|
||||
struct tx4939_le_reg ctrl;
|
||||
} gen;
|
||||
struct {
|
||||
struct {
|
||||
struct tx4939_le_reg l;
|
||||
struct tx4939_le_reg u;
|
||||
} key[3], ini;
|
||||
struct tx4939_le_reg ctrl;
|
||||
} des;
|
||||
struct {
|
||||
struct tx4939_le_reg key[4];
|
||||
struct tx4939_le_reg ini[4];
|
||||
struct tx4939_le_reg ctrl;
|
||||
} aes;
|
||||
struct {
|
||||
struct {
|
||||
struct tx4939_le_reg l;
|
||||
struct tx4939_le_reg u;
|
||||
} cnt;
|
||||
struct tx4939_le_reg ini[5];
|
||||
struct tx4939_le_reg unused;
|
||||
struct tx4939_le_reg ctrl;
|
||||
} hash;
|
||||
} cdr;
|
||||
struct tx4939_le_reg unused0[7];
|
||||
struct tx4939_le_reg rcsr;
|
||||
struct tx4939_le_reg rpr;
|
||||
__u64 rdr;
|
||||
__u64 ror[3];
|
||||
struct tx4939_le_reg unused1[2];
|
||||
struct tx4939_le_reg xorslr;
|
||||
struct tx4939_le_reg xorsur;
|
||||
};
|
||||
|
||||
struct tx4939_crypto_desc {
|
||||
__u32 src;
|
||||
__u32 dst;
|
||||
__u32 next;
|
||||
__u32 ctrl;
|
||||
__u32 index;
|
||||
__u32 xor;
|
||||
};
|
||||
|
||||
struct tx4939_vpc_reg {
|
||||
struct tx4939_le_reg csr;
|
||||
struct {
|
||||
struct tx4939_le_reg ctrlA;
|
||||
struct tx4939_le_reg ctrlB;
|
||||
struct tx4939_le_reg idesptr;
|
||||
struct tx4939_le_reg cdesptr;
|
||||
} port[3];
|
||||
struct tx4939_le_reg buserr;
|
||||
};
|
||||
|
||||
struct tx4939_vpc_desc {
|
||||
__u32 src;
|
||||
__u32 next;
|
||||
__u32 ctrl1;
|
||||
__u32 ctrl2;
|
||||
};
|
||||
|
||||
/*
|
||||
* IRC
|
||||
*/
|
||||
#define TX4939_IR_NONE 0
|
||||
#define TX4939_IR_DDR 1
|
||||
#define TX4939_IR_WTOERR 2
|
||||
#define TX4939_NUM_IR_INT 3
|
||||
#define TX4939_IR_INT(n) (3 + (n))
|
||||
#define TX4939_NUM_IR_ETH 2
|
||||
#define TX4939_IR_ETH(n) ((n) ? 43 : 6)
|
||||
#define TX4939_IR_VIDEO 7
|
||||
#define TX4939_IR_CIR 8
|
||||
#define TX4939_NUM_IR_SIO 4
|
||||
#define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */
|
||||
#define TX4939_NUM_IR_DMA 4
|
||||
#define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
|
||||
#define TX4939_IR_IRC 14
|
||||
#define TX4939_IR_PDMAC 15
|
||||
#define TX4939_NUM_IR_TMR 6
|
||||
#define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
|
||||
#define TX4939_NUM_IR_ATA 2
|
||||
#define TX4939_IR_ATA(n) (19 + (n))
|
||||
#define TX4939_IR_ACLC 21
|
||||
#define TX4939_IR_CIPHER 26
|
||||
#define TX4939_IR_INTA 27
|
||||
#define TX4939_IR_INTB 28
|
||||
#define TX4939_IR_INTC 29
|
||||
#define TX4939_IR_INTD 30
|
||||
#define TX4939_IR_I2C 33
|
||||
#define TX4939_IR_SPI 34
|
||||
#define TX4939_IR_PCIC 35
|
||||
#define TX4939_IR_PCIC1 36
|
||||
#define TX4939_IR_PCIERR 37
|
||||
#define TX4939_IR_PCIPME 38
|
||||
#define TX4939_IR_NDFMC 39
|
||||
#define TX4939_IR_ACLCPME 40
|
||||
#define TX4939_IR_RTC 41
|
||||
#define TX4939_IR_RND 42
|
||||
#define TX4939_IR_I2S 47
|
||||
#define TX4939_NUM_IR 64
|
||||
|
||||
#define TX4939_IRC_INT 2 /* IP[2] in Status register */
|
||||
|
||||
/*
|
||||
* CCFG
|
||||
*/
|
||||
/* CCFG : Chip Configuration */
|
||||
#define TX4939_CCFG_PCIBOOT 0x0000040000000000ULL
|
||||
#define TX4939_CCFG_WDRST 0x0000020000000000ULL
|
||||
#define TX4939_CCFG_WDREXEN 0x0000010000000000ULL
|
||||
#define TX4939_CCFG_BCFG_MASK 0x000000ff00000000ULL
|
||||
#define TX4939_CCFG_GTOT_MASK 0x06000000
|
||||
#define TX4939_CCFG_GTOT_4096 0x06000000
|
||||
#define TX4939_CCFG_GTOT_2048 0x04000000
|
||||
#define TX4939_CCFG_GTOT_1024 0x02000000
|
||||
#define TX4939_CCFG_GTOT_512 0x00000000
|
||||
#define TX4939_CCFG_TINTDIS 0x01000000
|
||||
#define TX4939_CCFG_PCI66 0x00800000
|
||||
#define TX4939_CCFG_PCIMODE 0x00400000
|
||||
#define TX4939_CCFG_SSCG 0x00100000
|
||||
#define TX4939_CCFG_MULCLK_MASK 0x000e0000
|
||||
#define TX4939_CCFG_MULCLK_8 (0x7 << 17)
|
||||
#define TX4939_CCFG_MULCLK_9 (0x0 << 17)
|
||||
#define TX4939_CCFG_MULCLK_10 (0x1 << 17)
|
||||
#define TX4939_CCFG_MULCLK_11 (0x2 << 17)
|
||||
#define TX4939_CCFG_MULCLK_12 (0x3 << 17)
|
||||
#define TX4939_CCFG_MULCLK_13 (0x4 << 17)
|
||||
#define TX4939_CCFG_MULCLK_14 (0x5 << 17)
|
||||
#define TX4939_CCFG_MULCLK_15 (0x6 << 17)
|
||||
#define TX4939_CCFG_BEOW 0x00010000
|
||||
#define TX4939_CCFG_WR 0x00008000
|
||||
#define TX4939_CCFG_TOE 0x00004000
|
||||
#define TX4939_CCFG_PCIARB 0x00002000
|
||||
#define TX4939_CCFG_YDIVMODE_MASK 0x00001c00
|
||||
#define TX4939_CCFG_YDIVMODE_2 (0x0 << 10)
|
||||
#define TX4939_CCFG_YDIVMODE_3 (0x1 << 10)
|
||||
#define TX4939_CCFG_YDIVMODE_5 (0x6 << 10)
|
||||
#define TX4939_CCFG_YDIVMODE_6 (0x7 << 10)
|
||||
#define TX4939_CCFG_PTSEL 0x00000200
|
||||
#define TX4939_CCFG_BESEL 0x00000100
|
||||
#define TX4939_CCFG_SYSSP_MASK 0x000000c0
|
||||
#define TX4939_CCFG_ACKSEL 0x00000020
|
||||
#define TX4939_CCFG_ROMW 0x00000010
|
||||
#define TX4939_CCFG_ENDIAN 0x00000004
|
||||
#define TX4939_CCFG_ARMODE 0x00000002
|
||||
#define TX4939_CCFG_ACEHOLD 0x00000001
|
||||
|
||||
/* PCFG : Pin Configuration */
|
||||
#define TX4939_PCFG_SIO2MODE_MASK 0xc000000000000000ULL
|
||||
#define TX4939_PCFG_SIO2MODE_GPIO 0x8000000000000000ULL
|
||||
#define TX4939_PCFG_SIO2MODE_SIO2 0x4000000000000000ULL
|
||||
#define TX4939_PCFG_SIO2MODE_SIO0 0x0000000000000000ULL
|
||||
#define TX4939_PCFG_SPIMODE 0x2000000000000000ULL
|
||||
#define TX4939_PCFG_I2CMODE 0x1000000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL
|
||||
#define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL
|
||||
#define TX4939_PCFG_DMASEL3 0x0004000000000000ULL
|
||||
#define TX4939_PCFG_DMASEL3_SIO0 0x0004000000000000ULL
|
||||
#define TX4939_PCFG_DMASEL3_NDFC 0x0000000000000000ULL
|
||||
#define TX4939_PCFG_VSSMODE 0x0000200000000000ULL
|
||||
#define TX4939_PCFG_VPSMODE 0x0000100000000000ULL
|
||||
#define TX4939_PCFG_ET1MODE 0x0000080000000000ULL
|
||||
#define TX4939_PCFG_ET0MODE 0x0000040000000000ULL
|
||||
#define TX4939_PCFG_ATA1MODE 0x0000020000000000ULL
|
||||
#define TX4939_PCFG_ATA0MODE 0x0000010000000000ULL
|
||||
#define TX4939_PCFG_BP_PLL 0x0000000100000000ULL
|
||||
|
||||
#define TX4939_PCFG_SYSCLKEN 0x08000000
|
||||
#define TX4939_PCFG_PCICLKEN_ALL 0x000f0000
|
||||
#define TX4939_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
|
||||
#define TX4939_PCFG_SPEED1 0x00002000
|
||||
#define TX4939_PCFG_SPEED0 0x00001000
|
||||
#define TX4939_PCFG_ITMODE 0x00000300
|
||||
#define TX4939_PCFG_DMASEL_ALL (0x00000007 | TX4939_PCFG_DMASEL3)
|
||||
#define TX4939_PCFG_DMASEL2 0x00000004
|
||||
#define TX4939_PCFG_DMASEL2_DRQ2 0x00000000
|
||||
#define TX4939_PCFG_DMASEL2_SIO0 0x00000004
|
||||
#define TX4939_PCFG_DMASEL1 0x00000002
|
||||
#define TX4939_PCFG_DMASEL1_DRQ1 0x00000000
|
||||
#define TX4939_PCFG_DMASEL0 0x00000001
|
||||
#define TX4939_PCFG_DMASEL0_DRQ0 0x00000000
|
||||
|
||||
/* CLKCTR : Clock Control */
|
||||
#define TX4939_CLKCTR_IOSCKD 0x8000000000000000ULL
|
||||
#define TX4939_CLKCTR_SYSCKD 0x4000000000000000ULL
|
||||
#define TX4939_CLKCTR_TM5CKD 0x2000000000000000ULL
|
||||
#define TX4939_CLKCTR_TM4CKD 0x1000000000000000ULL
|
||||
#define TX4939_CLKCTR_TM3CKD 0x0800000000000000ULL
|
||||
#define TX4939_CLKCTR_CIRCKD 0x0400000000000000ULL
|
||||
#define TX4939_CLKCTR_SIO3CKD 0x0200000000000000ULL
|
||||
#define TX4939_CLKCTR_SIO2CKD 0x0100000000000000ULL
|
||||
#define TX4939_CLKCTR_SIO1CKD 0x0080000000000000ULL
|
||||
#define TX4939_CLKCTR_VPCCKD 0x0040000000000000ULL
|
||||
#define TX4939_CLKCTR_EPCICKD 0x0020000000000000ULL
|
||||
#define TX4939_CLKCTR_ETH1CKD 0x0008000000000000ULL
|
||||
#define TX4939_CLKCTR_ATA1CKD 0x0004000000000000ULL
|
||||
#define TX4939_CLKCTR_BROMCKD 0x0002000000000000ULL
|
||||
#define TX4939_CLKCTR_NDCCKD 0x0001000000000000ULL
|
||||
#define TX4939_CLKCTR_I2CCKD 0x0000800000000000ULL
|
||||
#define TX4939_CLKCTR_ETH0CKD 0x0000400000000000ULL
|
||||
#define TX4939_CLKCTR_SPICKD 0x0000200000000000ULL
|
||||
#define TX4939_CLKCTR_SRAMCKD 0x0000100000000000ULL
|
||||
#define TX4939_CLKCTR_PCI1CKD 0x0000080000000000ULL
|
||||
#define TX4939_CLKCTR_DMA1CKD 0x0000040000000000ULL
|
||||
#define TX4939_CLKCTR_ACLCKD 0x0000020000000000ULL
|
||||
#define TX4939_CLKCTR_ATA0CKD 0x0000010000000000ULL
|
||||
#define TX4939_CLKCTR_DMA0CKD 0x0000008000000000ULL
|
||||
#define TX4939_CLKCTR_PCICCKD 0x0000004000000000ULL
|
||||
#define TX4939_CLKCTR_I2SCKD 0x0000002000000000ULL
|
||||
#define TX4939_CLKCTR_TM0CKD 0x0000001000000000ULL
|
||||
#define TX4939_CLKCTR_TM1CKD 0x0000000800000000ULL
|
||||
#define TX4939_CLKCTR_TM2CKD 0x0000000400000000ULL
|
||||
#define TX4939_CLKCTR_SIO0CKD 0x0000000200000000ULL
|
||||
#define TX4939_CLKCTR_CYPCKD 0x0000000100000000ULL
|
||||
#define TX4939_CLKCTR_IOSRST 0x80000000
|
||||
#define TX4939_CLKCTR_SYSRST 0x40000000
|
||||
#define TX4939_CLKCTR_TM5RST 0x20000000
|
||||
#define TX4939_CLKCTR_TM4RST 0x10000000
|
||||
#define TX4939_CLKCTR_TM3RST 0x08000000
|
||||
#define TX4939_CLKCTR_CIRRST 0x04000000
|
||||
#define TX4939_CLKCTR_SIO3RST 0x02000000
|
||||
#define TX4939_CLKCTR_SIO2RST 0x01000000
|
||||
#define TX4939_CLKCTR_SIO1RST 0x00800000
|
||||
#define TX4939_CLKCTR_VPCRST 0x00400000
|
||||
#define TX4939_CLKCTR_EPCIRST 0x00200000
|
||||
#define TX4939_CLKCTR_ETH1RST 0x00080000
|
||||
#define TX4939_CLKCTR_ATA1RST 0x00040000
|
||||
#define TX4939_CLKCTR_BROMRST 0x00020000
|
||||
#define TX4939_CLKCTR_NDCRST 0x00010000
|
||||
#define TX4939_CLKCTR_I2CRST 0x00008000
|
||||
#define TX4939_CLKCTR_ETH0RST 0x00004000
|
||||
#define TX4939_CLKCTR_SPIRST 0x00002000
|
||||
#define TX4939_CLKCTR_SRAMRST 0x00001000
|
||||
#define TX4939_CLKCTR_PCI1RST 0x00000800
|
||||
#define TX4939_CLKCTR_DMA1RST 0x00000400
|
||||
#define TX4939_CLKCTR_ACLRST 0x00000200
|
||||
#define TX4939_CLKCTR_ATA0RST 0x00000100
|
||||
#define TX4939_CLKCTR_DMA0RST 0x00000080
|
||||
#define TX4939_CLKCTR_PCICRST 0x00000040
|
||||
#define TX4939_CLKCTR_I2SRST 0x00000020
|
||||
#define TX4939_CLKCTR_TM0RST 0x00000010
|
||||
#define TX4939_CLKCTR_TM1RST 0x00000008
|
||||
#define TX4939_CLKCTR_TM2RST 0x00000004
|
||||
#define TX4939_CLKCTR_SIO0RST 0x00000002
|
||||
#define TX4939_CLKCTR_CYPRST 0x00000001
|
||||
|
||||
/*
|
||||
* RTC
|
||||
*/
|
||||
#define TX4939_RTCCTL_ALME 0x00000080
|
||||
#define TX4939_RTCCTL_ALMD 0x00000040
|
||||
#define TX4939_RTCCTL_BUSY 0x00000020
|
||||
|
||||
#define TX4939_RTCCTL_COMMAND 0x00000007
|
||||
#define TX4939_RTCCTL_COMMAND_NOP 0x00000000
|
||||
#define TX4939_RTCCTL_COMMAND_GETTIME 0x00000001
|
||||
#define TX4939_RTCCTL_COMMAND_SETTIME 0x00000002
|
||||
#define TX4939_RTCCTL_COMMAND_GETALARM 0x00000003
|
||||
#define TX4939_RTCCTL_COMMAND_SETALARM 0x00000004
|
||||
|
||||
#define TX4939_RTCTBC_PM 0x00000080
|
||||
#define TX4939_RTCTBC_COMP 0x0000007f
|
||||
|
||||
#define TX4939_RTC_REG_RAMSIZE 0x00000100
|
||||
#define TX4939_RTC_REG_RWBSIZE 0x00000006
|
||||
|
||||
/*
|
||||
* CRYPTO
|
||||
*/
|
||||
#define TX4939_CRYPTO_CSR_SAESO 0x08000000
|
||||
#define TX4939_CRYPTO_CSR_SAESI 0x04000000
|
||||
#define TX4939_CRYPTO_CSR_SDESO 0x02000000
|
||||
#define TX4939_CRYPTO_CSR_SDESI 0x01000000
|
||||
#define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000
|
||||
#define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20)
|
||||
#define TX4939_CRYPTO_CSR_TOINT 0x00080000
|
||||
#define TX4939_CRYPTO_CSR_DCINT 0x00040000
|
||||
#define TX4939_CRYPTO_CSR_GBINT 0x00010000
|
||||
#define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000
|
||||
#define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13)
|
||||
#define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800
|
||||
#define TX4939_CRYPTO_CSR_CSWAP_NONE 0x00000000
|
||||
#define TX4939_CRYPTO_CSR_CSWAP_IN 0x00000800
|
||||
#define TX4939_CRYPTO_CSR_CSWAP_OUT 0x00001000
|
||||
#define TX4939_CRYPTO_CSR_CSWAP_BOTH 0x00001800
|
||||
#define TX4939_CRYPTO_CSR_CDIV_MASK 0x00000600
|
||||
#define TX4939_CRYPTO_CSR_CDIV_DIV2 0x00000000
|
||||
#define TX4939_CRYPTO_CSR_CDIV_DIV1 0x00000200
|
||||
#define TX4939_CRYPTO_CSR_CDIV_DIV2ALT 0x00000400
|
||||
#define TX4939_CRYPTO_CSR_CDIV_DIV1ALT 0x00000600
|
||||
#define TX4939_CRYPTO_CSR_PDINT_MASK 0x000000c0
|
||||
#define TX4939_CRYPTO_CSR_PDINT_ALL 0x00000000
|
||||
#define TX4939_CRYPTO_CSR_PDINT_END 0x00000040
|
||||
#define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080
|
||||
#define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0
|
||||
#define TX4939_CRYPTO_CSR_GINTE 0x00000008
|
||||
#define TX4939_CRYPTO_CSR_RSTD 0x00000004
|
||||
#define TX4939_CRYPTO_CSR_RSTC 0x00000002
|
||||
#define TX4939_CRYPTO_CSR_ENCR 0x00000001
|
||||
|
||||
/* bits for tx4939_crypto_reg.cdr.gen.ctrl */
|
||||
#define TX4939_CRYPTO_CTX_ENGINE_MASK 0x00000003
|
||||
#define TX4939_CRYPTO_CTX_ENGINE_DES 0x00000000
|
||||
#define TX4939_CRYPTO_CTX_ENGINE_AES 0x00000001
|
||||
#define TX4939_CRYPTO_CTX_ENGINE_MD5 0x00000002
|
||||
#define TX4939_CRYPTO_CTX_ENGINE_SHA1 0x00000003
|
||||
#define TX4939_CRYPTO_CTX_TDMS 0x00000010
|
||||
#define TX4939_CRYPTO_CTX_CMS 0x00000020
|
||||
#define TX4939_CRYPTO_CTX_DMS 0x00000040
|
||||
#define TX4939_CRYPTO_CTX_UPDATE 0x00000080
|
||||
|
||||
/* bits for tx4939_crypto_desc.ctrl */
|
||||
#define TX4939_CRYPTO_DESC_OB_CNT_MASK 0xffe00000
|
||||
#define TX4939_CRYPTO_DESC_OB_CNT(cnt) ((cnt) << 21)
|
||||
#define TX4939_CRYPTO_DESC_IB_CNT_MASK 0x001ffc00
|
||||
#define TX4939_CRYPTO_DESC_IB_CNT(cnt) ((cnt) << 10)
|
||||
#define TX4939_CRYPTO_DESC_START 0x00000200
|
||||
#define TX4939_CRYPTO_DESC_END 0x00000100
|
||||
#define TX4939_CRYPTO_DESC_XOR 0x00000010
|
||||
#define TX4939_CRYPTO_DESC_LAST 0x00000008
|
||||
#define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006
|
||||
#define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000
|
||||
#define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002
|
||||
#define TX4939_CRYPTO_DESC_ERR_DIGEST 0x00000004
|
||||
#define TX4939_CRYPTO_DESC_OWN 0x00000001
|
||||
|
||||
/* bits for tx4939_crypto_desc.index */
|
||||
#define TX4939_CRYPTO_DESC_HASH_IDX_MASK 0x00000070
|
||||
#define TX4939_CRYPTO_DESC_HASH_IDX(idx) ((idx) << 4)
|
||||
#define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK 0x00000007
|
||||
#define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx) ((idx) << 0)
|
||||
|
||||
#define TX4939_CRYPTO_NR_SET 6
|
||||
|
||||
#define TX4939_CRYPTO_RCSR_INTE 0x00000008
|
||||
#define TX4939_CRYPTO_RCSR_RST 0x00000004
|
||||
#define TX4939_CRYPTO_RCSR_FIN 0x00000002
|
||||
#define TX4939_CRYPTO_RCSR_ST 0x00000001
|
||||
|
||||
/*
|
||||
* VPC
|
||||
*/
|
||||
#define TX4939_VPC_CSR_GBINT 0x00010000
|
||||
#define TX4939_VPC_CSR_SWAPO 0x00000020
|
||||
#define TX4939_VPC_CSR_SWAPI 0x00000010
|
||||
#define TX4939_VPC_CSR_GINTE 0x00000008
|
||||
#define TX4939_VPC_CSR_RSTD 0x00000004
|
||||
#define TX4939_VPC_CSR_RSTVPC 0x00000002
|
||||
|
||||
#define TX4939_VPC_CTRLA_VDPSN 0x00000200
|
||||
#define TX4939_VPC_CTRLA_PBUSY 0x00000100
|
||||
#define TX4939_VPC_CTRLA_DCINT 0x00000080
|
||||
#define TX4939_VPC_CTRLA_UOINT 0x00000040
|
||||
#define TX4939_VPC_CTRLA_PDINT_MASK 0x00000030
|
||||
#define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000
|
||||
#define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010
|
||||
#define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030
|
||||
#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
|
||||
#define TX4939_VPC_CTRLA_VDMODE 0x00000004
|
||||
#define TX4939_VPC_CTRLA_VDFOR 0x00000002
|
||||
#define TX4939_VPC_CTRLA_ENVPC 0x00000001
|
||||
|
||||
/* bits for tx4939_vpc_desc.ctrl1 */
|
||||
#define TX4939_VPC_DESC_CTRL1_ERR_MASK 0x00000006
|
||||
#define TX4939_VPC_DESC_CTRL1_OWN 0x00000001
|
||||
|
||||
#define tx4939_ddrcptr ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG)
|
||||
#define tx4939_ebuscptr tx4938_ebuscptr
|
||||
#define tx4939_ircptr \
|
||||
((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG)
|
||||
#define tx4939_pcicptr tx4938_pcicptr
|
||||
#define tx4939_pcic1ptr tx4938_pcic1ptr
|
||||
#define tx4939_ccfgptr \
|
||||
((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG)
|
||||
#define tx4939_sramcptr tx4938_sramcptr
|
||||
#define tx4939_rtcptr \
|
||||
((struct tx4939_rtc_reg __iomem *)TX4939_RTC_REG)
|
||||
#define tx4939_cryptoptr \
|
||||
((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG)
|
||||
#define tx4939_vpcptr ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG)
|
||||
|
||||
#define TX4939_REV_MAJ_MIN() \
|
||||
((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff)
|
||||
#define TX4939_REV_PCODE() \
|
||||
((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16)
|
||||
#define TX4939_CCFG_BCFG() \
|
||||
((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
|
||||
>> 32))
|
||||
|
||||
#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
|
||||
#define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits)
|
||||
#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
|
||||
|
||||
#define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
|
||||
#define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
|
||||
#define TX4939_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
|
||||
#define TX4939_EBUSC_WIDTH(ch) \
|
||||
(16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
|
||||
|
||||
/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */
|
||||
#define TX4939_SCLK0(mst) \
|
||||
((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
|
||||
|
||||
void tx4939_wdt_init(void);
|
||||
void tx4939_add_memory_regions(void);
|
||||
void tx4939_setup(void);
|
||||
void tx4939_time_init(unsigned int tmrnr);
|
||||
void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask);
|
||||
void tx4939_spi_init(int busid);
|
||||
void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
|
||||
int tx4939_report_pciclk(void);
|
||||
void tx4939_report_pci1clk(void);
|
||||
struct pci_dev;
|
||||
int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
|
||||
int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
|
||||
void tx4939_setup_pcierr_irq(void);
|
||||
void tx4939_irq_init(void);
|
||||
int tx4939_irq(void);
|
||||
void tx4939_mtd_init(int ch);
|
||||
|
||||
#endif /* __ASM_TXX9_TX4939_H */
|
||||
Reference in New Issue