[PATCH] EDAC: drivers for Intel i82860, i82875
Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Alan Cox
Linus Torvalds
parent
806c35f505
commit
0d88a10e56
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@ -0,0 +1,299 @@
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/*
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* Intel 82860 Memory Controller kernel module
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* (C) 2005 Red Hat (http://www.redhat.com)
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* Written by Ben Woodard <woodard@redhat.com>
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* shamelessly copied from and based upon the edac_i82875 driver
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* by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include "edac_mc.h"
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#ifndef PCI_DEVICE_ID_INTEL_82860_0
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#define PCI_DEVICE_ID_INTEL_82860_0 0x2531
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#endif /* PCI_DEVICE_ID_INTEL_82860_0 */
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#define I82860_MCHCFG 0x50
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#define I82860_GBA 0x60
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#define I82860_GBA_MASK 0x7FF
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#define I82860_GBA_SHIFT 24
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#define I82860_ERRSTS 0xC8
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#define I82860_EAP 0xE4
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#define I82860_DERRCTL_STS 0xE2
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enum i82860_chips {
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I82860 = 0,
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};
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struct i82860_dev_info {
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const char *ctl_name;
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};
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struct i82860_error_info {
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u16 errsts;
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u32 eap;
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u16 derrsyn;
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u16 errsts2;
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};
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static const struct i82860_dev_info i82860_devs[] = {
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[I82860] = {
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.ctl_name = "i82860"},
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};
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static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code
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has already registered driver */
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static int i82860_registered = 1;
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static void i82860_get_error_info (struct mem_ctl_info *mci,
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struct i82860_error_info *info)
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{
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/*
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* This is a mess because there is no atomic way to read all the
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* registers at once and the registers can transition from CE being
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* overwritten by UE.
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*/
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pci_read_config_word(mci->pdev, I82860_ERRSTS, &info->errsts);
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pci_read_config_dword(mci->pdev, I82860_EAP, &info->eap);
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pci_read_config_word(mci->pdev, I82860_DERRCTL_STS, &info->derrsyn);
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pci_read_config_word(mci->pdev, I82860_ERRSTS, &info->errsts2);
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pci_write_bits16(mci->pdev, I82860_ERRSTS, 0x0003, 0x0003);
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/*
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* If the error is the same for both reads then the first set of reads
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* is valid. If there is a change then there is a CE no info and the
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* second set of reads is valid and should be UE info.
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*/
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if (!(info->errsts2 & 0x0003))
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return;
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if ((info->errsts ^ info->errsts2) & 0x0003) {
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pci_read_config_dword(mci->pdev, I82860_EAP, &info->eap);
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pci_read_config_word(mci->pdev, I82860_DERRCTL_STS,
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&info->derrsyn);
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}
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}
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static int i82860_process_error_info (struct mem_ctl_info *mci,
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struct i82860_error_info *info, int handle_errors)
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{
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int row;
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if (!(info->errsts2 & 0x0003))
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return 0;
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if (!handle_errors)
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return 1;
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if ((info->errsts ^ info->errsts2) & 0x0003) {
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edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
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info->errsts = info->errsts2;
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}
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info->eap >>= PAGE_SHIFT;
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row = edac_mc_find_csrow_by_page(mci, info->eap);
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if (info->errsts & 0x0002)
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edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
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else
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edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
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0, "i82860 UE");
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return 1;
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}
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static void i82860_check(struct mem_ctl_info *mci)
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{
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struct i82860_error_info info;
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debugf1("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
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i82860_get_error_info(mci, &info);
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i82860_process_error_info(mci, &info, 1);
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}
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static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
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{
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int rc = -ENODEV;
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int index;
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struct mem_ctl_info *mci = NULL;
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unsigned long last_cumul_size;
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u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
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/* RDRAM has channels but these don't map onto the abstractions that
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edac uses.
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The device groups from the GRA registers seem to map reasonably
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well onto the notion of a chip select row.
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There are 16 GRA registers and since the name is associated with
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the channel and the GRA registers map to physical devices so we are
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going to make 1 channel for group.
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*/
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mci = edac_mc_alloc(0, 16, 1);
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if (!mci)
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return -ENOMEM;
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debugf3("MC: " __FILE__ ": %s(): init mci\n", __func__);
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mci->pdev = pdev;
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mci->mtype_cap = MEM_FLAG_DDR;
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
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/* I"m not sure about this but I think that all RDRAM is SECDED */
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mci->edac_cap = EDAC_FLAG_SECDED;
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/* adjust FLAGS */
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mci->mod_name = BS_MOD_STR;
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mci->mod_ver = "$Revision: 1.1.2.6 $";
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mci->ctl_name = i82860_devs[dev_idx].ctl_name;
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mci->edac_check = i82860_check;
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mci->ctl_page_to_phys = NULL;
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pci_read_config_word(mci->pdev, I82860_MCHCFG, &mchcfg_ddim);
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mchcfg_ddim = mchcfg_ddim & 0x180;
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/*
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* The group row boundary (GRA) reg values are boundary address
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* for each DRAM row with a granularity of 16MB. GRA regs are
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* cumulative; therefore GRA15 will contain the total memory contained
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* in all eight rows.
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*/
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for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
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u16 value;
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u32 cumul_size;
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struct csrow_info *csrow = &mci->csrows[index];
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pci_read_config_word(mci->pdev, I82860_GBA + index * 2,
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&value);
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cumul_size = (value & I82860_GBA_MASK) <<
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(I82860_GBA_SHIFT - PAGE_SHIFT);
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debugf3("MC: " __FILE__ ": %s(): (%d) cumul_size 0x%x\n",
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__func__, index, cumul_size);
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if (cumul_size == last_cumul_size)
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continue; /* not populated */
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csrow->first_page = last_cumul_size;
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csrow->last_page = cumul_size - 1;
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csrow->nr_pages = cumul_size - last_cumul_size;
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last_cumul_size = cumul_size;
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csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
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csrow->mtype = MEM_RMBS;
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csrow->dtype = DEV_UNKNOWN;
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csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
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}
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/* clear counters */
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pci_write_bits16(mci->pdev, I82860_ERRSTS, 0x0003, 0x0003);
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if (edac_mc_add_mc(mci)) {
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debugf3("MC: " __FILE__
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": %s(): failed edac_mc_add_mc()\n",
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__func__);
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edac_mc_free(mci);
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} else {
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/* get this far and it's successful */
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debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
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rc = 0;
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}
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return rc;
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}
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/* returns count (>= 0), or negative on error */
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static int __devinit i82860_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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int rc;
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debugf0("MC: " __FILE__ ": %s()\n", __func__);
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printk(KERN_INFO "i82860 init one\n");
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if(pci_enable_device(pdev) < 0)
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return -EIO;
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rc = i82860_probe1(pdev, ent->driver_data);
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if(rc == 0)
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mci_pdev = pci_dev_get(pdev);
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return rc;
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}
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static void __devexit i82860_remove_one(struct pci_dev *pdev)
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{
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struct mem_ctl_info *mci;
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debugf0(__FILE__ ": %s()\n", __func__);
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mci = edac_mc_find_mci_by_pdev(pdev);
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if ((mci != NULL) && (edac_mc_del_mc(mci) == 0))
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edac_mc_free(mci);
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}
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static const struct pci_device_id i82860_pci_tbl[] __devinitdata = {
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{PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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I82860},
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{0,} /* 0 terminated list. */
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};
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MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
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static struct pci_driver i82860_driver = {
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.name = BS_MOD_STR,
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.probe = i82860_init_one,
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.remove = __devexit_p(i82860_remove_one),
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.id_table = i82860_pci_tbl,
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};
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int __init i82860_init(void)
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{
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int pci_rc;
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debugf3("MC: " __FILE__ ": %s()\n", __func__);
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if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
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return pci_rc;
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if (!mci_pdev) {
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i82860_registered = 0;
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mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82860_0, NULL);
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if (mci_pdev == NULL) {
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debugf0("860 pci_get_device fail\n");
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return -ENODEV;
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}
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pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
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if (pci_rc < 0) {
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debugf0("860 init fail\n");
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pci_dev_put(mci_pdev);
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return -ENODEV;
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}
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}
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return 0;
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}
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static void __exit i82860_exit(void)
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{
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debugf3("MC: " __FILE__ ": %s()\n", __func__);
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pci_unregister_driver(&i82860_driver);
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if (!i82860_registered) {
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i82860_remove_one(mci_pdev);
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pci_dev_put(mci_pdev);
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}
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}
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module_init(i82860_init);
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module_exit(i82860_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR
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("Red Hat Inc. (http://www.redhat.com.com) Ben Woodard <woodard@redhat.com>");
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MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
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@ -0,0 +1,532 @@
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/*
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* Intel D82875P Memory Controller kernel module
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* (C) 2003 Linux Networx (http://lnxi.com)
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* Written by Thayne Harbaugh
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* Contributors:
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* Wang Zhenyu at intel.com
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*
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* $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
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*
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* Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include "edac_mc.h"
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#ifndef PCI_DEVICE_ID_INTEL_82875_0
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#define PCI_DEVICE_ID_INTEL_82875_0 0x2578
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#endif /* PCI_DEVICE_ID_INTEL_82875_0 */
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#ifndef PCI_DEVICE_ID_INTEL_82875_6
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#define PCI_DEVICE_ID_INTEL_82875_6 0x257e
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#endif /* PCI_DEVICE_ID_INTEL_82875_6 */
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/* four csrows in dual channel, eight in single channel */
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#define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
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/* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
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#define I82875P_EAP 0x58 /* Error Address Pointer (32b)
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*
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* 31:12 block address
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* 11:0 reserved
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*/
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#define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
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*
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* 7:0 DRAM ECC Syndrome
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*/
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#define I82875P_DES 0x5d /* DRAM Error Status (8b)
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*
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* 7:1 reserved
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* 0 Error channel 0/1
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*/
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#define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
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*
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* 15:10 reserved
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* 9 non-DRAM lock error (ndlock)
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* 8 Sftwr Generated SMI
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* 7 ECC UE
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* 6 reserved
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* 5 MCH detects unimplemented cycle
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* 4 AGP access outside GA
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* 3 Invalid AGP access
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* 2 Invalid GA translation table
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* 1 Unsupported AGP command
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* 0 ECC CE
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*/
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#define I82875P_ERRCMD 0xca /* Error Command (16b)
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*
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* 15:10 reserved
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* 9 SERR on non-DRAM lock
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* 8 SERR on ECC UE
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* 7 SERR on ECC CE
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* 6 target abort on high exception
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* 5 detect unimplemented cyc
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* 4 AGP access outside of GA
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* 3 SERR on invalid AGP access
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* 2 invalid translation table
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* 1 SERR on unsupported AGP command
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* 0 reserved
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*/
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/* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
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#define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
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*
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* 15:10 reserved
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* 9 fast back-to-back - ro 0
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* 8 SERR enable - ro 0
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* 7 addr/data stepping - ro 0
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* 6 parity err enable - ro 0
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* 5 VGA palette snoop - ro 0
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* 4 mem wr & invalidate - ro 0
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* 3 special cycle - ro 0
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* 2 bus master - ro 0
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* 1 mem access dev6 - 0(dis),1(en)
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* 0 IO access dev3 - 0(dis),1(en)
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*/
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#define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
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*
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* 31:12 mem base addr [31:12]
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* 11:4 address mask - ro 0
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* 3 prefetchable - ro 0(non),1(pre)
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* 2:1 mem type - ro 0
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* 0 mem space - ro 0
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*/
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/* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
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#define I82875P_DRB_SHIFT 26 /* 64MiB grain */
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#define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
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*
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* 7 reserved
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* 6:0 64MiB row boundary addr
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*/
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#define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
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*
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* 7 reserved
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* 6:4 row attr row 1
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* 3 reserved
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* 2:0 row attr row 0
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*
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* 000 = 4KiB
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* 001 = 8KiB
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* 010 = 16KiB
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* 011 = 32KiB
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*/
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#define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
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*
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* 31:30 reserved
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* 29 init complete
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* 28:23 reserved
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* 22:21 nr chan 00=1,01=2
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* 20 reserved
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* 19:18 Data Integ Mode 00=none,01=ecc
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* 17:11 reserved
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* 10:8 refresh mode
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* 7 reserved
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* 6:4 mode select
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* 3:2 reserved
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* 1:0 DRAM type 01=DDR
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*/
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enum i82875p_chips {
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I82875P = 0,
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};
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struct i82875p_pvt {
|
||||
struct pci_dev *ovrfl_pdev;
|
||||
void *ovrfl_window;
|
||||
};
|
||||
|
||||
|
||||
struct i82875p_dev_info {
|
||||
const char *ctl_name;
|
||||
};
|
||||
|
||||
|
||||
struct i82875p_error_info {
|
||||
u16 errsts;
|
||||
u32 eap;
|
||||
u8 des;
|
||||
u8 derrsyn;
|
||||
u16 errsts2;
|
||||
};
|
||||
|
||||
|
||||
static const struct i82875p_dev_info i82875p_devs[] = {
|
||||
[I82875P] = {
|
||||
.ctl_name = "i82875p"},
|
||||
};
|
||||
|
||||
static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code
|
||||
has already registered driver */
|
||||
static int i82875p_registered = 1;
|
||||
|
||||
static void i82875p_get_error_info (struct mem_ctl_info *mci,
|
||||
struct i82875p_error_info *info)
|
||||
{
|
||||
/*
|
||||
* This is a mess because there is no atomic way to read all the
|
||||
* registers at once and the registers can transition from CE being
|
||||
* overwritten by UE.
|
||||
*/
|
||||
pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts);
|
||||
pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
|
||||
pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
|
||||
pci_read_config_byte(mci->pdev, I82875P_DERRSYN, &info->derrsyn);
|
||||
pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts2);
|
||||
|
||||
pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);
|
||||
|
||||
/*
|
||||
* If the error is the same then we can for both reads then
|
||||
* the first set of reads is valid. If there is a change then
|
||||
* there is a CE no info and the second set of reads is valid
|
||||
* and should be UE info.
|
||||
*/
|
||||
if (!(info->errsts2 & 0x0081))
|
||||
return;
|
||||
if ((info->errsts ^ info->errsts2) & 0x0081) {
|
||||
pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
|
||||
pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
|
||||
pci_read_config_byte(mci->pdev, I82875P_DERRSYN,
|
||||
&info->derrsyn);
|
||||
}
|
||||
}
|
||||
|
||||
static int i82875p_process_error_info (struct mem_ctl_info *mci,
|
||||
struct i82875p_error_info *info, int handle_errors)
|
||||
{
|
||||
int row, multi_chan;
|
||||
|
||||
multi_chan = mci->csrows[0].nr_channels - 1;
|
||||
|
||||
if (!(info->errsts2 & 0x0081))
|
||||
return 0;
|
||||
|
||||
if (!handle_errors)
|
||||
return 1;
|
||||
|
||||
if ((info->errsts ^ info->errsts2) & 0x0081) {
|
||||
edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
|
||||
info->errsts = info->errsts2;
|
||||
}
|
||||
|
||||
info->eap >>= PAGE_SHIFT;
|
||||
row = edac_mc_find_csrow_by_page(mci, info->eap);
|
||||
|
||||
if (info->errsts & 0x0080)
|
||||
edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
|
||||
else
|
||||
edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
|
||||
multi_chan ? (info->des & 0x1) : 0,
|
||||
"i82875p CE");
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
static void i82875p_check(struct mem_ctl_info *mci)
|
||||
{
|
||||
struct i82875p_error_info info;
|
||||
|
||||
debugf1("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
|
||||
i82875p_get_error_info(mci, &info);
|
||||
i82875p_process_error_info(mci, &info, 1);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_PROC_FS
|
||||
extern int pci_proc_attach_device(struct pci_dev *);
|
||||
#endif
|
||||
|
||||
static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
int index;
|
||||
struct mem_ctl_info *mci = NULL;
|
||||
struct i82875p_pvt *pvt = NULL;
|
||||
unsigned long last_cumul_size;
|
||||
struct pci_dev *ovrfl_pdev;
|
||||
void __iomem *ovrfl_window = NULL;
|
||||
|
||||
u32 drc;
|
||||
u32 drc_chan; /* Number of channels 0=1chan,1=2chan */
|
||||
u32 nr_chans;
|
||||
u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
|
||||
|
||||
debugf0("MC: " __FILE__ ": %s()\n", __func__);
|
||||
|
||||
ovrfl_pdev = pci_find_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
|
||||
|
||||
if (!ovrfl_pdev) {
|
||||
/*
|
||||
* Intel tells BIOS developers to hide device 6 which
|
||||
* configures the overflow device access containing
|
||||
* the DRBs - this is where we expose device 6.
|
||||
* http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
|
||||
*/
|
||||
pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
|
||||
ovrfl_pdev =
|
||||
pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
|
||||
if (!ovrfl_pdev)
|
||||
goto fail;
|
||||
}
|
||||
#ifdef CONFIG_PROC_FS
|
||||
if (!ovrfl_pdev->procent && pci_proc_attach_device(ovrfl_pdev)) {
|
||||
printk(KERN_ERR "MC: " __FILE__
|
||||
": %s(): Failed to attach overflow device\n",
|
||||
__func__);
|
||||
goto fail;
|
||||
}
|
||||
#endif /* CONFIG_PROC_FS */
|
||||
if (pci_enable_device(ovrfl_pdev)) {
|
||||
printk(KERN_ERR "MC: " __FILE__
|
||||
": %s(): Failed to enable overflow device\n",
|
||||
__func__);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (pci_request_regions(ovrfl_pdev, pci_name(ovrfl_pdev))) {
|
||||
#ifdef CORRECT_BIOS
|
||||
goto fail;
|
||||
#endif
|
||||
}
|
||||
/* cache is irrelevant for PCI bus reads/writes */
|
||||
ovrfl_window = ioremap_nocache(pci_resource_start(ovrfl_pdev, 0),
|
||||
pci_resource_len(ovrfl_pdev, 0));
|
||||
|
||||
if (!ovrfl_window) {
|
||||
printk(KERN_ERR "MC: " __FILE__
|
||||
": %s(): Failed to ioremap bar6\n", __func__);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* need to find out the number of channels */
|
||||
drc = readl(ovrfl_window + I82875P_DRC);
|
||||
drc_chan = ((drc >> 21) & 0x1);
|
||||
nr_chans = drc_chan + 1;
|
||||
drc_ddim = (drc >> 18) & 0x1;
|
||||
|
||||
mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
|
||||
nr_chans);
|
||||
|
||||
if (!mci) {
|
||||
rc = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s(): init mci\n", __func__);
|
||||
|
||||
mci->pdev = pdev;
|
||||
mci->mtype_cap = MEM_FLAG_DDR;
|
||||
|
||||
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
|
||||
mci->edac_cap = EDAC_FLAG_UNKNOWN;
|
||||
/* adjust FLAGS */
|
||||
|
||||
mci->mod_name = BS_MOD_STR;
|
||||
mci->mod_ver = "$Revision: 1.5.2.11 $";
|
||||
mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
|
||||
mci->edac_check = i82875p_check;
|
||||
mci->ctl_page_to_phys = NULL;
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s(): init pvt\n", __func__);
|
||||
|
||||
pvt = (struct i82875p_pvt *) mci->pvt_info;
|
||||
pvt->ovrfl_pdev = ovrfl_pdev;
|
||||
pvt->ovrfl_window = ovrfl_window;
|
||||
|
||||
/*
|
||||
* The dram row boundary (DRB) reg values are boundary address
|
||||
* for each DRAM row with a granularity of 32 or 64MB (single/dual
|
||||
* channel operation). DRB regs are cumulative; therefore DRB7 will
|
||||
* contain the total memory contained in all eight rows.
|
||||
*/
|
||||
for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
|
||||
u8 value;
|
||||
u32 cumul_size;
|
||||
struct csrow_info *csrow = &mci->csrows[index];
|
||||
|
||||
value = readb(ovrfl_window + I82875P_DRB + index);
|
||||
cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
|
||||
debugf3("MC: " __FILE__ ": %s(): (%d) cumul_size 0x%x\n",
|
||||
__func__, index, cumul_size);
|
||||
if (cumul_size == last_cumul_size)
|
||||
continue; /* not populated */
|
||||
|
||||
csrow->first_page = last_cumul_size;
|
||||
csrow->last_page = cumul_size - 1;
|
||||
csrow->nr_pages = cumul_size - last_cumul_size;
|
||||
last_cumul_size = cumul_size;
|
||||
csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
|
||||
csrow->mtype = MEM_DDR;
|
||||
csrow->dtype = DEV_UNKNOWN;
|
||||
csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
|
||||
}
|
||||
|
||||
/* clear counters */
|
||||
pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);
|
||||
|
||||
if (edac_mc_add_mc(mci)) {
|
||||
debugf3("MC: " __FILE__
|
||||
": %s(): failed edac_mc_add_mc()\n", __func__);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* get this far and it's successful */
|
||||
debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (mci)
|
||||
edac_mc_free(mci);
|
||||
|
||||
if (ovrfl_window)
|
||||
iounmap(ovrfl_window);
|
||||
|
||||
if (ovrfl_pdev) {
|
||||
pci_release_regions(ovrfl_pdev);
|
||||
pci_disable_device(ovrfl_pdev);
|
||||
}
|
||||
|
||||
/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
/* returns count (>= 0), or negative on error */
|
||||
static int __devinit i82875p_init_one(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
int rc;
|
||||
|
||||
debugf0("MC: " __FILE__ ": %s()\n", __func__);
|
||||
|
||||
printk(KERN_INFO "i82875p init one\n");
|
||||
if(pci_enable_device(pdev) < 0)
|
||||
return -EIO;
|
||||
rc = i82875p_probe1(pdev, ent->driver_data);
|
||||
if (mci_pdev == NULL)
|
||||
mci_pdev = pci_dev_get(pdev);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
static void __devexit i82875p_remove_one(struct pci_dev *pdev)
|
||||
{
|
||||
struct mem_ctl_info *mci;
|
||||
struct i82875p_pvt *pvt = NULL;
|
||||
|
||||
debugf0(__FILE__ ": %s()\n", __func__);
|
||||
|
||||
if ((mci = edac_mc_find_mci_by_pdev(pdev)) == NULL)
|
||||
return;
|
||||
|
||||
pvt = (struct i82875p_pvt *) mci->pvt_info;
|
||||
if (pvt->ovrfl_window)
|
||||
iounmap(pvt->ovrfl_window);
|
||||
|
||||
if (pvt->ovrfl_pdev) {
|
||||
#ifdef CORRECT_BIOS
|
||||
pci_release_regions(pvt->ovrfl_pdev);
|
||||
#endif /*CORRECT_BIOS */
|
||||
pci_disable_device(pvt->ovrfl_pdev);
|
||||
pci_dev_put(pvt->ovrfl_pdev);
|
||||
}
|
||||
|
||||
if (edac_mc_del_mc(mci))
|
||||
return;
|
||||
|
||||
edac_mc_free(mci);
|
||||
}
|
||||
|
||||
|
||||
static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
|
||||
{PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
I82875P},
|
||||
{0,} /* 0 terminated list. */
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
|
||||
|
||||
|
||||
static struct pci_driver i82875p_driver = {
|
||||
.name = BS_MOD_STR,
|
||||
.probe = i82875p_init_one,
|
||||
.remove = __devexit_p(i82875p_remove_one),
|
||||
.id_table = i82875p_pci_tbl,
|
||||
};
|
||||
|
||||
|
||||
int __init i82875p_init(void)
|
||||
{
|
||||
int pci_rc;
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s()\n", __func__);
|
||||
pci_rc = pci_register_driver(&i82875p_driver);
|
||||
if (pci_rc < 0)
|
||||
return pci_rc;
|
||||
if (mci_pdev == NULL) {
|
||||
i82875p_registered = 0;
|
||||
mci_pdev =
|
||||
pci_get_device(PCI_VENDOR_ID_INTEL,
|
||||
PCI_DEVICE_ID_INTEL_82875_0, NULL);
|
||||
if (!mci_pdev) {
|
||||
debugf0("875p pci_get_device fail\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
|
||||
if (pci_rc < 0) {
|
||||
debugf0("875p init fail\n");
|
||||
pci_dev_put(mci_pdev);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void __exit i82875p_exit(void)
|
||||
{
|
||||
debugf3("MC: " __FILE__ ": %s()\n", __func__);
|
||||
|
||||
pci_unregister_driver(&i82875p_driver);
|
||||
if (!i82875p_registered) {
|
||||
i82875p_remove_one(mci_pdev);
|
||||
pci_dev_put(mci_pdev);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
module_init(i82875p_init);
|
||||
module_exit(i82875p_exit);
|
||||
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
|
||||
MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
|
||||
Reference in New Issue