drm/radeon/kms: add support for CP setup on cayman asics
Cayman asics have 3 ring buffers: ring 0 supports both gfx and compute rings 1 and 2 are compute only At the moment we only support ring 0. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
fa8198eac8
commit
0c88a02ef6
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@ -66,7 +66,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
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r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
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evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
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radeon_trace_points.o ni.o
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radeon_trace_points.o ni.o cayman_blit_shaders.o
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radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
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radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
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@ -0,0 +1,50 @@
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Alex Deucher <alexander.deucher@amd.com>
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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/*
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* evergreen cards need to use the 3D engine to blit data which requires
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* quite a bit of hw state setup. Rather than pull the whole 3D driver
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* (which normally generates the 3D state) into the DRM, we opt to use
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* statically generated state tables. The regsiter state and shaders
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* were hand generated to support blitting functionality. See the 3D
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* driver or documentation for descriptions of the registers and
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* shader instructions.
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*/
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const u32 cayman_default_state[] =
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{
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/* XXX fill in additional blit state */
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0xc0026900,
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0x00000316,
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0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
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0x00000010, /* */
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};
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const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
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@ -0,0 +1,32 @@
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef CAYMAN_BLIT_SHADERS_H
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#define CAYMAN_BLIT_SHADERS_H
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extern const u32 cayman_default_state[];
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extern const u32 cayman_default_size;
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#endif
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@ -31,6 +31,7 @@
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#include "nid.h"
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#include "atom.h"
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#include "ni_reg.h"
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#include "cayman_blit_shaders.h"
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#define EVERGREEN_PFP_UCODE_SIZE 1120
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#define EVERGREEN_PM4_UCODE_SIZE 1376
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@ -1023,3 +1024,228 @@ void cayman_pcie_gart_fini(struct radeon_device *rdev)
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radeon_gart_fini(rdev);
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}
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/*
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* CP.
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*/
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static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
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{
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if (enable)
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WREG32(CP_ME_CNTL, 0);
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else {
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rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
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WREG32(SCRATCH_UMSK, 0);
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}
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}
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static int cayman_cp_load_microcode(struct radeon_device *rdev)
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{
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const __be32 *fw_data;
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int i;
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if (!rdev->me_fw || !rdev->pfp_fw)
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return -EINVAL;
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cayman_cp_enable(rdev, false);
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fw_data = (const __be32 *)rdev->pfp_fw->data;
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WREG32(CP_PFP_UCODE_ADDR, 0);
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for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
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WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
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WREG32(CP_PFP_UCODE_ADDR, 0);
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fw_data = (const __be32 *)rdev->me_fw->data;
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WREG32(CP_ME_RAM_WADDR, 0);
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for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
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WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
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WREG32(CP_PFP_UCODE_ADDR, 0);
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WREG32(CP_ME_RAM_WADDR, 0);
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WREG32(CP_ME_RAM_RADDR, 0);
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return 0;
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}
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static int cayman_cp_start(struct radeon_device *rdev)
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{
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int r, i;
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r = radeon_ring_lock(rdev, 7);
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if (r) {
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DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
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return r;
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}
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radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
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radeon_ring_write(rdev, 0x1);
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radeon_ring_write(rdev, 0x0);
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radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1);
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radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, 0);
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radeon_ring_unlock_commit(rdev);
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cayman_cp_enable(rdev, true);
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r = radeon_ring_lock(rdev, cayman_default_size + 15);
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if (r) {
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DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
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return r;
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}
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/* setup clear context state */
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radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
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for (i = 0; i < cayman_default_size; i++)
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radeon_ring_write(rdev, cayman_default_state[i]);
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radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
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/* set clear context state */
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radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
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radeon_ring_write(rdev, 0);
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/* SQ_VTX_BASE_VTX_LOC */
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radeon_ring_write(rdev, 0xc0026f00);
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radeon_ring_write(rdev, 0x00000000);
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radeon_ring_write(rdev, 0x00000000);
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radeon_ring_write(rdev, 0x00000000);
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/* Clear consts */
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radeon_ring_write(rdev, 0xc0036f00);
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radeon_ring_write(rdev, 0x00000bc4);
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radeon_ring_write(rdev, 0xffffffff);
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radeon_ring_write(rdev, 0xffffffff);
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radeon_ring_write(rdev, 0xffffffff);
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radeon_ring_unlock_commit(rdev);
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/* XXX init other rings */
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return 0;
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}
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int cayman_cp_resume(struct radeon_device *rdev)
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{
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u32 tmp;
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u32 rb_bufsz;
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int r;
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/* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
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WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
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SOFT_RESET_PA |
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SOFT_RESET_SH |
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SOFT_RESET_VGT |
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SOFT_RESET_SX));
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RREG32(GRBM_SOFT_RESET);
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mdelay(15);
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WREG32(GRBM_SOFT_RESET, 0);
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RREG32(GRBM_SOFT_RESET);
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WREG32(CP_SEM_WAIT_TIMER, 0x4);
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/* Set the write pointer delay */
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WREG32(CP_RB_WPTR_DELAY, 0);
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WREG32(CP_DEBUG, (1 << 27));
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/* ring 0 - compute and gfx */
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/* Set ring buffer size */
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rb_bufsz = drm_order(rdev->cp.ring_size / 8);
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tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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#ifdef __BIG_ENDIAN
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tmp |= BUF_SWAP_32BIT;
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#endif
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WREG32(CP_RB0_CNTL, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
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WREG32(CP_RB0_WPTR, 0);
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/* set the wb address wether it's enabled or not */
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WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
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WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
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WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
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if (rdev->wb.enabled)
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WREG32(SCRATCH_UMSK, 0xff);
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else {
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tmp |= RB_NO_UPDATE;
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WREG32(SCRATCH_UMSK, 0);
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}
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mdelay(1);
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WREG32(CP_RB0_CNTL, tmp);
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WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);
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rdev->cp.rptr = RREG32(CP_RB0_RPTR);
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rdev->cp.wptr = RREG32(CP_RB0_WPTR);
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/* ring1 - compute only */
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/* Set ring buffer size */
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rb_bufsz = drm_order(rdev->cp1.ring_size / 8);
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tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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#ifdef __BIG_ENDIAN
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tmp |= BUF_SWAP_32BIT;
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#endif
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WREG32(CP_RB1_CNTL, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
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WREG32(CP_RB1_WPTR, 0);
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/* set the wb address wether it's enabled or not */
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WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
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WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
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mdelay(1);
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WREG32(CP_RB1_CNTL, tmp);
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WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);
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rdev->cp1.rptr = RREG32(CP_RB1_RPTR);
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rdev->cp1.wptr = RREG32(CP_RB1_WPTR);
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/* ring2 - compute only */
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/* Set ring buffer size */
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rb_bufsz = drm_order(rdev->cp2.ring_size / 8);
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tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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#ifdef __BIG_ENDIAN
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tmp |= BUF_SWAP_32BIT;
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#endif
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WREG32(CP_RB2_CNTL, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
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WREG32(CP_RB2_WPTR, 0);
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/* set the wb address wether it's enabled or not */
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WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
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WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
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mdelay(1);
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WREG32(CP_RB2_CNTL, tmp);
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WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);
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rdev->cp2.rptr = RREG32(CP_RB2_RPTR);
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rdev->cp2.wptr = RREG32(CP_RB2_WPTR);
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/* start the rings */
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cayman_cp_start(rdev);
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rdev->cp.ready = true;
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rdev->cp1.ready = true;
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rdev->cp2.ready = true;
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/* this only test cp0 */
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r = radeon_ring_test(rdev);
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if (r) {
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rdev->cp.ready = false;
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rdev->cp1.ready = false;
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rdev->cp2.ready = false;
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return r;
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}
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return 0;
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}
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@ -205,6 +205,24 @@
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#define SOFT_RESET_VGT (1 << 14)
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#define SOFT_RESET_IA (1 << 15)
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#define SCRATCH_REG0 0x8500
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#define SCRATCH_REG1 0x8504
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#define SCRATCH_REG2 0x8508
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#define SCRATCH_REG3 0x850C
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#define SCRATCH_REG4 0x8510
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#define SCRATCH_REG5 0x8514
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#define SCRATCH_REG6 0x8518
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#define SCRATCH_REG7 0x851C
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#define SCRATCH_UMSK 0x8540
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#define SCRATCH_ADDR 0x8544
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#define CP_SEM_WAIT_TIMER 0x85BC
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#define CP_ME_CNTL 0x86D8
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#define CP_ME_HALT (1 << 28)
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#define CP_PFP_HALT (1 << 26)
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#define CP_RB2_RPTR 0x86f8
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#define CP_RB1_RPTR 0x86fc
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#define CP_RB0_RPTR 0x8700
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#define CP_RB_WPTR_DELAY 0x8704
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#define CP_MEQ_THRESHOLDS 0x8764
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#define MEQ1_START(x) ((x) << 0)
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#define MEQ2_START(x) ((x) << 8)
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@ -363,5 +381,155 @@
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#define ACK_FLUSH_CTL(x) ((x) << 6)
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#define SYNC_FLUSH_CTL (1 << 8)
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#define CP_RB0_BASE 0xC100
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#define CP_RB0_CNTL 0xC104
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#define RB_BUFSZ(x) ((x) << 0)
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#define RB_BLKSZ(x) ((x) << 8)
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#define RB_NO_UPDATE (1 << 27)
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#define RB_RPTR_WR_ENA (1 << 31)
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#define BUF_SWAP_32BIT (2 << 16)
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#define CP_RB0_RPTR_ADDR 0xC10C
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#define CP_RB0_RPTR_ADDR_HI 0xC110
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#define CP_RB0_WPTR 0xC114
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#define CP_RB1_BASE 0xC180
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#define CP_RB1_CNTL 0xC184
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#define CP_RB1_RPTR_ADDR 0xC188
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#define CP_RB1_RPTR_ADDR_HI 0xC18C
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#define CP_RB1_WPTR 0xC190
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#define CP_RB2_BASE 0xC194
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#define CP_RB2_CNTL 0xC198
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#define CP_RB2_RPTR_ADDR 0xC19C
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#define CP_RB2_RPTR_ADDR_HI 0xC1A0
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#define CP_RB2_WPTR 0xC1A4
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#define CP_PFP_UCODE_ADDR 0xC150
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#define CP_PFP_UCODE_DATA 0xC154
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#define CP_ME_RAM_RADDR 0xC158
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#define CP_ME_RAM_WADDR 0xC15C
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#define CP_ME_RAM_DATA 0xC160
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#define CP_DEBUG 0xC1FC
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/*
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* PM4
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*/
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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(((reg) >> 2) & 0xFFFF) | \
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((n) & 0x3FFF) << 16)
|
||||
#define CP_PACKET2 0x80000000
|
||||
#define PACKET2_PAD_SHIFT 0
|
||||
#define PACKET2_PAD_MASK (0x3fffffff << 0)
|
||||
|
||||
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
|
||||
|
||||
#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
|
||||
(((op) & 0xFF) << 8) | \
|
||||
((n) & 0x3FFF) << 16)
|
||||
|
||||
/* Packet 3 types */
|
||||
#define PACKET3_NOP 0x10
|
||||
#define PACKET3_SET_BASE 0x11
|
||||
#define PACKET3_CLEAR_STATE 0x12
|
||||
#define PACKET3_INDEX_BUFFER_SIZE 0x13
|
||||
#define PACKET3_DEALLOC_STATE 0x14
|
||||
#define PACKET3_DISPATCH_DIRECT 0x15
|
||||
#define PACKET3_DISPATCH_INDIRECT 0x16
|
||||
#define PACKET3_INDIRECT_BUFFER_END 0x17
|
||||
#define PACKET3_SET_PREDICATION 0x20
|
||||
#define PACKET3_REG_RMW 0x21
|
||||
#define PACKET3_COND_EXEC 0x22
|
||||
#define PACKET3_PRED_EXEC 0x23
|
||||
#define PACKET3_DRAW_INDIRECT 0x24
|
||||
#define PACKET3_DRAW_INDEX_INDIRECT 0x25
|
||||
#define PACKET3_INDEX_BASE 0x26
|
||||
#define PACKET3_DRAW_INDEX_2 0x27
|
||||
#define PACKET3_CONTEXT_CONTROL 0x28
|
||||
#define PACKET3_DRAW_INDEX_OFFSET 0x29
|
||||
#define PACKET3_INDEX_TYPE 0x2A
|
||||
#define PACKET3_DRAW_INDEX 0x2B
|
||||
#define PACKET3_DRAW_INDEX_AUTO 0x2D
|
||||
#define PACKET3_DRAW_INDEX_IMMD 0x2E
|
||||
#define PACKET3_NUM_INSTANCES 0x2F
|
||||
#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
|
||||
#define PACKET3_INDIRECT_BUFFER 0x32
|
||||
#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
|
||||
#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
|
||||
#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
|
||||
#define PACKET3_WRITE_DATA 0x37
|
||||
#define PACKET3_MEM_SEMAPHORE 0x39
|
||||
#define PACKET3_MPEG_INDEX 0x3A
|
||||
#define PACKET3_WAIT_REG_MEM 0x3C
|
||||
#define PACKET3_MEM_WRITE 0x3D
|
||||
#define PACKET3_SURFACE_SYNC 0x43
|
||||
# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
|
||||
# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
|
||||
# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
|
||||
# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
|
||||
# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
|
||||
# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
|
||||
# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
|
||||
# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
|
||||
# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
|
||||
# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
|
||||
# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
|
||||
# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
|
||||
# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
|
||||
# define PACKET3_FULL_CACHE_ENA (1 << 20)
|
||||
# define PACKET3_TC_ACTION_ENA (1 << 23)
|
||||
# define PACKET3_CB_ACTION_ENA (1 << 25)
|
||||
# define PACKET3_DB_ACTION_ENA (1 << 26)
|
||||
# define PACKET3_SH_ACTION_ENA (1 << 27)
|
||||
# define PACKET3_SX_ACTION_ENA (1 << 28)
|
||||
#define PACKET3_ME_INITIALIZE 0x44
|
||||
#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
|
||||
#define PACKET3_COND_WRITE 0x45
|
||||
#define PACKET3_EVENT_WRITE 0x46
|
||||
#define PACKET3_EVENT_WRITE_EOP 0x47
|
||||
#define PACKET3_EVENT_WRITE_EOS 0x48
|
||||
#define PACKET3_PREAMBLE_CNTL 0x4A
|
||||
# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
|
||||
# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
|
||||
#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
|
||||
#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
|
||||
#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
|
||||
#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
|
||||
#define PACKET3_ONE_REG_WRITE 0x57
|
||||
#define PACKET3_SET_CONFIG_REG 0x68
|
||||
#define PACKET3_SET_CONFIG_REG_START 0x00008000
|
||||
#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
|
||||
#define PACKET3_SET_CONTEXT_REG 0x69
|
||||
#define PACKET3_SET_CONTEXT_REG_START 0x00028000
|
||||
#define PACKET3_SET_CONTEXT_REG_END 0x00029000
|
||||
#define PACKET3_SET_ALU_CONST 0x6A
|
||||
/* alu const buffers only; no reg file */
|
||||
#define PACKET3_SET_BOOL_CONST 0x6B
|
||||
#define PACKET3_SET_BOOL_CONST_START 0x0003a500
|
||||
#define PACKET3_SET_BOOL_CONST_END 0x0003a518
|
||||
#define PACKET3_SET_LOOP_CONST 0x6C
|
||||
#define PACKET3_SET_LOOP_CONST_START 0x0003a200
|
||||
#define PACKET3_SET_LOOP_CONST_END 0x0003a500
|
||||
#define PACKET3_SET_RESOURCE 0x6D
|
||||
#define PACKET3_SET_RESOURCE_START 0x00030000
|
||||
#define PACKET3_SET_RESOURCE_END 0x00038000
|
||||
#define PACKET3_SET_SAMPLER 0x6E
|
||||
#define PACKET3_SET_SAMPLER_START 0x0003c000
|
||||
#define PACKET3_SET_SAMPLER_END 0x0003c600
|
||||
#define PACKET3_SET_CTL_CONST 0x6F
|
||||
#define PACKET3_SET_CTL_CONST_START 0x0003cff0
|
||||
#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
|
||||
#define PACKET3_SET_RESOURCE_OFFSET 0x70
|
||||
#define PACKET3_SET_ALU_CONST_VS 0x71
|
||||
#define PACKET3_SET_ALU_CONST_DI 0x72
|
||||
#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
|
||||
#define PACKET3_SET_RESOURCE_INDIRECT 0x74
|
||||
#define PACKET3_SET_APPEND_CNT 0x75
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -664,6 +664,8 @@ struct radeon_wb {
|
|||
|
||||
#define RADEON_WB_SCRATCH_OFFSET 0
|
||||
#define RADEON_WB_CP_RPTR_OFFSET 1024
|
||||
#define RADEON_WB_CP1_RPTR_OFFSET 1280
|
||||
#define RADEON_WB_CP2_RPTR_OFFSET 1536
|
||||
#define R600_WB_IH_WPTR_OFFSET 2048
|
||||
#define R600_WB_EVENT_OFFSET 3072
|
||||
|
||||
|
|
@ -1186,6 +1188,9 @@ struct radeon_device {
|
|||
struct radeon_mman mman;
|
||||
struct radeon_fence_driver fence_drv;
|
||||
struct radeon_cp cp;
|
||||
/* cayman compute rings */
|
||||
struct radeon_cp cp1;
|
||||
struct radeon_cp cp2;
|
||||
struct radeon_ib_pool ib_pool;
|
||||
struct radeon_irq irq;
|
||||
struct radeon_asic *asic;
|
||||
|
|
|
|||
Reference in New Issue