ath5k: Update register list
* Update list of registers * Use updated register macros inside hw.c, initvals.c and debug.c Changes-licensed-under: ISC Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Nick Kossifidis
John W. Linville
parent
00b1304c4c
commit
0bacdf303f
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@ -129,7 +129,7 @@ static struct reg regs[] = {
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REG_STRUCT_INIT(AR5K_CPC1),
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REG_STRUCT_INIT(AR5K_CPC2),
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REG_STRUCT_INIT(AR5K_CPC3),
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REG_STRUCT_INIT(AR5K_CPCORN),
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REG_STRUCT_INIT(AR5K_CPCOVF),
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REG_STRUCT_INIT(AR5K_RESET_CTL),
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REG_STRUCT_INIT(AR5K_SLEEP_CTL),
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REG_STRUCT_INIT(AR5K_INTPEND),
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@ -843,27 +843,26 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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* Write some more initial register settings
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*/
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if (ah->ah_version == AR5K_AR5212) {
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ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));
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ath5k_hw_reg_write(ah, 0x0002a002, 0x982c);
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if (channel->hw_value == CHANNEL_G)
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if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)
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ath5k_hw_reg_write(ah, 0x00f80d80,
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AR5K_PHY(83));
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0x994c);
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else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)
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ath5k_hw_reg_write(ah, 0x00380140,
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AR5K_PHY(83));
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0x994c);
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else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)
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ath5k_hw_reg_write(ah, 0x00fc0ec0,
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AR5K_PHY(83));
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0x994c);
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else /* 2425 */
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ath5k_hw_reg_write(ah, 0x00fc0fc0,
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AR5K_PHY(83));
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0x994c);
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else
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ath5k_hw_reg_write(ah, 0x00000000,
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AR5K_PHY(83));
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ath5k_hw_reg_write(ah, 0x00000000, 0x994c);
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ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
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ath5k_hw_reg_write(ah, 0x0000000f, 0x8060);
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ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
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ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
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ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
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}
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@ -935,7 +934,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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return ret;
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/* Set antenna mode */
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44),
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY_ANT_CTL,
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ah->ah_antenna[ee_mode][0], 0xfffffc06);
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/*
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@ -965,15 +964,15 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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ath5k_hw_reg_write(ah,
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AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
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AR5K_PHY(0x5a));
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AR5K_PHY_NFTHRES);
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11),
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY_SETTLING,
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(ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
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0xffffc07f);
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12),
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY_GAIN,
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(ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
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0xfffc0fff);
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14),
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY_DESIRED_SIZE,
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(ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
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((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
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0xffff0000);
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@ -982,13 +981,13 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
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(ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
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(ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
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(ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
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(ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
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(ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a),
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY_RF_CTL3,
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ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19),
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY_NF,
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(ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01);
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AR5K_REG_MASKED_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 4, 0xffffff01);
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AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
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AR5K_PHY_IQ_CORR_ENABLE |
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@ -3363,11 +3362,13 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
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AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
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/* Set PHY register 0x9844 (??) */
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/* Set AR5K_PHY_SETTLING */
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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(ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 :
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(ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C,
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AR5K_PHY(17));
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(ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
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| 0x38 :
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(ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
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AR5K_PHY_SETTLING);
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/* Set Frame Control Register */
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ath5k_hw_reg_write(ah, ah->ah_turbo ?
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(AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
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@ -489,7 +489,7 @@ static const struct ath5k_ini ar5212_ini[] = {
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{ AR5K_QUEUE_TXDP(9), 0x00000000 },
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{ AR5K_DCU_FP, 0x00000000 },
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{ AR5K_DCU_TXP, 0x00000000 },
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{ AR5K_DCU_TX_FILTER, 0x00000000 },
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{ AR5K_DCU_TX_FILTER_0_BASE, 0x00000000 },
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/* Unknown table */
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{ 0x1078, 0x00000000 },
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{ 0x10b8, 0x00000000 },
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@ -679,7 +679,7 @@ static const struct ath5k_ini ar5212_ini[] = {
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{ AR5K_PHY(645), 0x00106c10 },
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{ AR5K_PHY(646), 0x009c4060 },
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{ AR5K_PHY(647), 0x1483800a },
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/* { AR5K_PHY(648), 0x018830c6 },*/ /* 2413 */
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/* { AR5K_PHY(648), 0x018830c6 },*/ /* 2413/2425 */
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{ AR5K_PHY(648), 0x01831061 },
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{ AR5K_PHY(649), 0x00000400 },
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/*{ AR5K_PHY(650), 0x000001b5 },*/
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