ARM: mv78xx0: use fixed pci i/o mapping
Move mv78xx0 PCI to fixed i/o mapping and remove io.h. This changes the PCI bus addresses from the cpu address to 0 based. It appears that there is translation h/w for this, but its untested. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Rob Herring
parent
e7adf1e0a5
commit
0b9b18e016
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@ -571,7 +571,6 @@ config ARCH_MV78XX0
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select PCI
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select NEED_MACH_IO_H
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select PLAT_ORION
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help
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Support for the following Marvell MV78xx0 series SoCs:
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@ -13,6 +13,7 @@
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <plat/addr-map.h>
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#include <mach/mv78xx0.h>
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#include "common.h"
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/*
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@ -81,7 +82,7 @@ void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
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int maj, int min)
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{
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orion_setup_cpu_win(&addr_map_cfg, window, base, size,
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TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
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TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
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}
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void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
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@ -134,11 +134,6 @@ static struct map_desc mv78xx0_io_desc[] __initdata = {
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.pfn = 0,
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.length = MV78XX0_CORE_REGS_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
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.pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
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.length = MV78XX0_PCIE_IO_SIZE * 8,
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.type = MT_DEVICE,
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}, {
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.virtual = MV78XX0_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
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@ -1,24 +0,0 @@
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/*
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* arch/arm/mach-mv78xx0/include/mach/io.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IO_H
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#define __ASM_ARCH_IO_H
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#include "mv78xx0.h"
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#define IO_SPACE_LIMIT 0xffffffff
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static inline void __iomem *__io(unsigned long addr)
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{
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return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
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+ MV78XX0_PCIE_IO_VIRT_BASE(0));
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}
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#define __io(a) __io(a)
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#endif
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@ -29,15 +29,15 @@
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*
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* virt phys size
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* fe400000 f102x000 16K core-specific peripheral registers
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* fe700000 f0800000 1M PCIe #0 I/O space
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* fe800000 f0900000 1M PCIe #1 I/O space
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* fe900000 f0a00000 1M PCIe #2 I/O space
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* fea00000 f0b00000 1M PCIe #3 I/O space
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* feb00000 f0c00000 1M PCIe #4 I/O space
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* fec00000 f0d00000 1M PCIe #5 I/O space
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* fed00000 f0e00000 1M PCIe #6 I/O space
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* fee00000 f0f00000 1M PCIe #7 I/O space
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* fef00000 f1000000 1M on-chip peripheral registers
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* fee00000 f0800000 64K PCIe #0 I/O space
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* fee10000 f0900000 64K PCIe #1 I/O space
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* fee20000 f0a00000 64K PCIe #2 I/O space
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* fee30000 f0b00000 64K PCIe #3 I/O space
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* fee40000 f0c00000 64K PCIe #4 I/O space
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* fee50000 f0d00000 64K PCIe #5 I/O space
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* fee60000 f0e00000 64K PCIe #6 I/O space
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* fee70000 f0f00000 64K PCIe #7 I/O space
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* fd000000 f1000000 1M on-chip peripheral registers
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*/
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#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
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#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
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@ -46,11 +46,10 @@
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#define MV78XX0_CORE_REGS_SIZE SZ_16K
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#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
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#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20))
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#define MV78XX0_PCIE_IO_SIZE SZ_1M
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#define MV78XX0_REGS_PHYS_BASE 0xf1000000
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#define MV78XX0_REGS_VIRT_BASE 0xfef00000
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#define MV78XX0_REGS_VIRT_BASE 0xfd000000
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#define MV78XX0_REGS_SIZE SZ_1M
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#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
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@ -15,6 +15,7 @@
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#include <asm/mach/pci.h>
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#include <plat/pcie.h>
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#include <plat/addr-map.h>
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#include <mach/mv78xx0.h>
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#include "common.h"
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struct pcie_port {
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@ -23,16 +24,13 @@ struct pcie_port {
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u8 root_bus_nr;
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void __iomem *base;
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spinlock_t conf_lock;
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char io_space_name[16];
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char mem_space_name[16];
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struct resource res[2];
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struct resource res;
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};
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static struct pcie_port pcie_port[8];
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static int num_pcie_ports;
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static struct resource pcie_io_space;
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static struct resource pcie_mem_space;
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void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
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{
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@ -40,102 +38,59 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
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*rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
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}
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u32 pcie_port_size[8] = {
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0,
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0x30000000,
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0x10000000,
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0x10000000,
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0x08000000,
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0x08000000,
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0x08000000,
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0x04000000,
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};
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static void __init mv78xx0_pcie_preinit(void)
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{
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int i;
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u32 size_each;
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u32 start;
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int win;
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int win = 0;
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pcie_io_space.name = "PCIe I/O Space";
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pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
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pcie_io_space.end =
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MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
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pcie_io_space.flags = IORESOURCE_IO;
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pcie_io_space.flags = IORESOURCE_MEM;
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if (request_resource(&iomem_resource, &pcie_io_space))
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panic("can't allocate PCIe I/O space");
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pcie_mem_space.name = "PCIe MEM Space";
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pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
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pcie_mem_space.end =
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MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
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pcie_mem_space.flags = IORESOURCE_MEM;
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if (request_resource(&iomem_resource, &pcie_mem_space))
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panic("can't allocate PCIe MEM space");
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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snprintf(pp->io_space_name, sizeof(pp->io_space_name),
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"PCIe %d.%d I/O", pp->maj, pp->min);
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pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
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pp->res[0].name = pp->io_space_name;
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pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
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pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
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pp->res[0].flags = IORESOURCE_IO;
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snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
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"PCIe %d.%d MEM", pp->maj, pp->min);
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pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
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pp->res[1].name = pp->mem_space_name;
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pp->res[1].flags = IORESOURCE_MEM;
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}
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switch (num_pcie_ports) {
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case 0:
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size_each = 0;
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break;
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case 1:
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size_each = 0x30000000;
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break;
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case 2 ... 3:
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size_each = 0x10000000;
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break;
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case 4 ... 6:
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size_each = 0x08000000;
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break;
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case 7:
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size_each = 0x04000000;
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break;
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default:
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if (num_pcie_ports > 7)
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panic("invalid number of PCIe ports");
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}
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size_each = pcie_port_size[num_pcie_ports];
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start = MV78XX0_PCIE_MEM_PHYS_BASE;
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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pp->res[1].start = start;
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pp->res[1].end = start + size_each - 1;
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snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
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"PCIe %d.%d MEM", pp->maj, pp->min);
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pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
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pp->res.name = pp->mem_space_name;
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pp->res.flags = IORESOURCE_MEM;
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pp->res.start = start;
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pp->res.end = start + size_each - 1;
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start += size_each;
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}
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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if (request_resource(&pcie_io_space, &pp->res[0]))
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panic("can't allocate PCIe I/O sub-space");
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if (request_resource(&pcie_mem_space, &pp->res[1]))
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if (request_resource(&iomem_resource, &pp->res))
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panic("can't allocate PCIe MEM sub-space");
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}
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win = 0;
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
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resource_size(&pp->res[0]),
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pp->maj, pp->min);
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mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
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resource_size(&pp->res[1]),
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mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start,
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resource_size(&pp->res),
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pp->maj, pp->min);
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mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K,
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pp->maj, pp->min);
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}
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}
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@ -156,8 +111,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
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orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
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orion_pcie_setup(pp->base);
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pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
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pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
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pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
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pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
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return 1;
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}
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@ -281,7 +237,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
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pp->root_bus_nr = -1;
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pp->base = (void __iomem *)base;
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spin_lock_init(&pp->conf_lock);
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memset(pp->res, 0, sizeof(pp->res));
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memset(&pp->res, 0, sizeof(pp->res));
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} else {
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printk("link down, ignoring\n");
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}
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