OMAP: DSS2: DSI: Fix DSI PLL power bug
OMAP3630 has a HW bug causing DSI PLL power command POWER_ON_DIV (0x3) to not work properly. The bug prevents us from enabling DSI PLL power only to HS divider block. This patch adds a dss feature for the bug and converts POWER_ON_DIV requests to POWER_ON_ALL (0x2). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -1059,6 +1059,11 @@ static int dsi_pll_power(enum dsi_pll_power_state state)
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{
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{
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int t = 0;
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int t = 0;
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/* DSI-PLL power command 0x3 is not working */
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if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
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state == DSI_PLL_POWER_ON_DIV)
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state = DSI_PLL_POWER_ON_ALL;
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REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
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REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
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/* PLL_PWR_STATUS */
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/* PLL_PWR_STATUS */
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@ -271,7 +271,7 @@ static struct omap_dss_features omap3630_dss_features = {
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FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
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FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
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FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
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FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
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FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
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FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
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FEAT_RESIZECONF,
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FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG,
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.num_mgrs = 2,
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.num_mgrs = 2,
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.num_ovls = 3,
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.num_ovls = 3,
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@ -40,6 +40,8 @@ enum dss_feat_id {
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/* Independent core clk divider */
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/* Independent core clk divider */
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FEAT_CORE_CLK_DIV = 1 << 11,
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FEAT_CORE_CLK_DIV = 1 << 11,
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FEAT_LCD_CLK_SRC = 1 << 12,
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FEAT_LCD_CLK_SRC = 1 << 12,
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/* DSI-PLL power command 0x3 is not working */
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FEAT_DSI_PLL_PWR_BUG = 1 << 13,
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};
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};
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/* DSS register field id */
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/* DSS register field id */
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