i7core_edac: Add more status functions to EDAC driver
This patch were co-authored with Aristeu Rozanski. Signed-off-by: Aristeu Sergio <arozansk@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
194a40feab
commit
0b2b7b7ec0
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@ -62,6 +62,15 @@
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/* OFFSETS for Devices 4,5 and 6 Function 0 */
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#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
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#define THREE_DIMMS_PRESENT (1 << 24)
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#define SINGLE_QUAD_RANK_PRESENT (1 << 23)
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#define QUAD_RANK_PRESENT (1 << 22)
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#define REGISTERED_DIMM (1 << 15)
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#define MC_CHANNEL_RANK_PRESENT 0x7c
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#define RANK_PRESENT_MASK 0xffff
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#define MC_CHANNEL_ADDR_MATCH 0xf0
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#define MC_CHANNEL_ERROR_MASK 0xf8
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#define MC_CHANNEL_ERROR_INJECT 0xfc
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@ -74,6 +83,46 @@
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#define NO_MASK_CACHELINE 0x00
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#define REPEAT_EN 0x01
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/* OFFSETS for Devices 4,5 and 6 Function 1 */
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#define MC_DOD_CH_DIMM0 0x48
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#define MC_DOD_CH_DIMM1 0x4c
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#define MC_DOD_CH_DIMM2 0x50
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#define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
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#define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
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#define DIMM_PRESENT_MASK (1 << 9)
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#define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
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#define NUMBANK_MASK ((1 << 8) | (1 << 7))
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#define NUMBANK(x) (((x) & NUMBANK_MASK) >> 7)
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#define NUMRANK_MASK ((1 << 6) | (1 << 5))
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#define NUMRANK(x) (((x) & NUMRANK_MASK) >> 5)
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#define NUMROW_MASK ((1 << 4) | (1 << 3))
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#define NUMROW(x) (((x) & NUMROW_MASK) >> 3)
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#define NUMCOL_MASK 3
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#define NUMCOL(x) ((x) & NUMCOL_MASK)
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#define MC_SAG_CH_0 0x80
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#define MC_SAG_CH_1 0x84
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#define MC_SAG_CH_2 0x88
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#define MC_SAG_CH_3 0x8c
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#define MC_SAG_CH_4 0x90
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#define MC_SAG_CH_5 0x94
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#define MC_SAG_CH_6 0x98
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#define MC_SAG_CH_7 0x9c
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#define MC_RIR_LIMIT_CH_0 0x40
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#define MC_RIR_LIMIT_CH_1 0x44
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#define MC_RIR_LIMIT_CH_2 0x48
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#define MC_RIR_LIMIT_CH_3 0x4C
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#define MC_RIR_LIMIT_CH_4 0x50
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#define MC_RIR_LIMIT_CH_5 0x54
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#define MC_RIR_LIMIT_CH_6 0x58
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#define MC_RIR_LIMIT_CH_7 0x5C
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#define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
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#define MC_RIR_WAY_CH 0x80
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#define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
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#define MC_RIR_WAY_RANK_MASK 0x7
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/*
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* i7core structs
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*/
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@ -99,11 +148,17 @@ struct i7core_inject {
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int channel, dimm, rank, bank, page, col;
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};
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struct i7core_channel {
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u32 ranks;
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u32 dimms;
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};
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struct i7core_pvt {
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struct pci_dev *pci_mcr; /* Dev 3:0 */
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struct pci_dev *pci_ch[NUM_CHANS][NUM_FUNCS];
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struct i7core_info info;
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struct i7core_inject inject;
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struct i7core_channel channel[NUM_CHANS];
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};
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/* Device name and register DID (Device ID) */
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@ -133,16 +188,12 @@ static struct edac_pci_ctl_info *i7core_pci;
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****************************************************************************/
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/* MC_CONTROL bits */
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#define CH2_ACTIVE(pvt) ((pvt)->info.mc_control & 1 << 10)
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#define CH1_ACTIVE(pvt) ((pvt)->info.mc_control & 1 << 9)
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#define CH0_ACTIVE(pvt) ((pvt)->info.mc_control & 1 << 8)
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#define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & 1 << (8 + ch))
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#define ECCx8(pvt) ((pvt)->info.mc_control & 1 << 1)
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/* MC_STATUS bits */
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#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & 1 << 3)
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#define CH2_DISABLED(pvt) ((pvt)->info.mc_status & 1 << 2)
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#define CH1_DISABLED(pvt) ((pvt)->info.mc_status & 1 << 1)
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#define CH0_DISABLED(pvt) ((pvt)->info.mc_status & 1 << 0)
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#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & 1 << ch)
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/* MC_MAX_DOD read functions */
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static inline int maxnumdimms(struct i7core_pvt *pvt)
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@ -189,19 +240,12 @@ static inline int maxnumcol(struct i7core_pvt *pvt)
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static int get_dimm_config(struct mem_ctl_info *mci)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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int i;
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pci_read_config_dword(pvt->pci_mcr, MC_CONTROL, &pvt->info.mc_control);
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pci_read_config_dword(pvt->pci_mcr, MC_STATUS, &pvt->info.mc_status);
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pci_read_config_dword(pvt->pci_mcr, MC_MAX_DOD, &pvt->info.max_dod);
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debugf0("Channels active [%c][%c][%c] - enabled [%c][%c][%c]\n",
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CH0_ACTIVE(pvt)?'0':'-',
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CH1_ACTIVE(pvt)?'1':'-',
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CH2_ACTIVE(pvt)?'2':'-',
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CH0_DISABLED(pvt)?'-':'0',
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CH1_DISABLED(pvt)?'-':'1',
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CH2_DISABLED(pvt)?'-':'2');
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if (ECC_ENABLED(pvt))
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debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt)?8:4);
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else
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@ -213,6 +257,38 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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debugf0("DOD Maximum rows x colums = 0x%x x 0x%x\n",
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maxnumrow(pvt), maxnumcol(pvt));
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debugf0("Memory channel configuration:\n");
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for (i = 0; i < NUM_CHANS; i++) {
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u32 data;
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if (!CH_ACTIVE(pvt, i)) {
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debugf0("Channel %i is not active\n", i);
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continue;
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}
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if (CH_DISABLED(pvt, i)) {
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debugf0("Channel %i is disabled\n", i);
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continue;
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}
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pci_read_config_dword(pvt->pci_ch[i][0],
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MC_CHANNEL_DIMM_INIT_PARAMS, &data);
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pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT)? 4 : 2;
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if (data & THREE_DIMMS_PRESENT)
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pvt->channel[i].dimms = 3;
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else if (data & SINGLE_QUAD_RANK_PRESENT)
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pvt->channel[i].dimms = 1;
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else
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pvt->channel[i].dimms = 2;
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debugf0("Channel %d (0x%08x): %d ranks, %d dimms "
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"(%sregistered)\n", i, data,
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pvt->channel[i].ranks, pvt->channel[i].dimms,
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(data & REGISTERED_DIMM)? "" : "un" );
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}
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return 0;
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}
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@ -489,7 +565,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
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if (pvt->inject.dimm < 0)
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mask |= 1l << 41;
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else {
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if (maxnumdimms(pvt) > 2)
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if (pvt->channel[pvt->inject.channel].dimms > 2)
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mask |= (pvt->inject.dimm & 0x3l) << 35;
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else
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mask |= (pvt->inject.dimm & 0x1l) << 36;
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@ -499,7 +575,7 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
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if (pvt->inject.rank < 0)
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mask |= 1l << 40;
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else {
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if (maxnumdimms(pvt) > 2)
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if (pvt->channel[pvt->inject.channel].dimms > 2)
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mask |= (pvt->inject.rank & 0x1l) << 34;
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else
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mask |= (pvt->inject.rank & 0x3l) << 34;
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@ -646,9 +722,6 @@ static int i7core_get_devices(struct mem_ctl_info *mci, int dev_idx)
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}
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pvt->pci_mcr=pdev;
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/* Get dimm basic config */
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get_dimm_config(mci);
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/* Retrieve all needed functions at MTR channel controllers */
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for (i = 0; i < NUM_CHANS; i++) {
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pdev = NULL;
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@ -672,6 +745,9 @@ static int i7core_get_devices(struct mem_ctl_info *mci, int dev_idx)
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}
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i7core_printk(KERN_INFO, "Driver loaded.\n");
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/* Get dimm basic config */
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get_dimm_config(mci);
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return 0;
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}
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