powerpc/mpic: FSL MPIC error interrupt support.
All SOC device error interrupts are muxed and delivered to the core as a single MPIC error interrupt. Currently all the device drivers requiring access to device errors have to register for the MPIC error interrupt as a shared interrupt. With this patch we add interrupt demuxing capability in the mpic driver, allowing device drivers to register for their individual error interrupts. This is achieved by handling error interrupts in a cascaded fashion. MPIC error interrupt is handled by the "error_int_handler", which subsequently demuxes it using the EISR and delivers it to the respective drivers. The error interrupt capability is dependent on the MPIC EIMR register, which was introduced in FSL MPIC version 4.1 (P4080 rev2). So, error interrupt demuxing capability is dependent on the MPIC version and can be used for versions >= 4.1. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Varun Sethi
Kumar Gala
parent
688ba1dbee
commit
0a4081641d
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@ -118,6 +118,9 @@
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#define MPIC_MAX_CPUS 32
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#define MPIC_MAX_ISU 32
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#define MPIC_MAX_ERR 32
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#define MPIC_FSL_ERR_INT 16
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/*
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* Tsi108 implementation of MPIC has many differences from the original one
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*/
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@ -270,6 +273,7 @@ struct mpic
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struct irq_chip hc_ipi;
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#endif
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struct irq_chip hc_tm;
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struct irq_chip hc_err;
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const char *name;
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/* Flags */
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unsigned int flags;
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@ -283,6 +287,8 @@ struct mpic
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/* vector numbers used for internal sources (ipi/timers) */
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unsigned int ipi_vecs[4];
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unsigned int timer_vecs[8];
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/* vector numbers used for FSL MPIC error interrupts */
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unsigned int err_int_vecs[MPIC_MAX_ERR];
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/* Spurious vector to program into unused sources */
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unsigned int spurious_vec;
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@ -306,6 +312,9 @@ struct mpic
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struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
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struct mpic_reg_bank isus[MPIC_MAX_ISU];
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/* ioremap'ed base for error interrupt registers */
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u32 __iomem *err_regs;
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/* Protected sources */
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unsigned long *protected;
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@ -370,6 +379,11 @@ struct mpic
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#define MPIC_NO_RESET 0x00004000
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/* Freescale MPIC (compatible includes "fsl,mpic") */
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#define MPIC_FSL 0x00008000
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/* Freescale MPIC supports EIMR (error interrupt mask register).
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* This flag is set for MPIC version >= 4.1 (version determined
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* from the BRR1 register).
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*/
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#define MPIC_FSL_HAS_EIMR 0x00010000
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/* MPIC HW modification ID */
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#define MPIC_REGSET_MASK 0xf0000000
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@ -15,7 +15,7 @@ obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o
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obj-$(CONFIG_PPC_PMI) += pmi.o
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obj-$(CONFIG_U3_DART) += dart_iommu.o
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obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
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obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o
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obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
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obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
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obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
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@ -0,0 +1,149 @@
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/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Author: Varun Sethi <varun.sethi@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2 of the
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* License.
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*
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*/
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mpic.h>
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#include "mpic.h"
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#define MPIC_ERR_INT_BASE 0x3900
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#define MPIC_ERR_INT_EISR 0x0000
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#define MPIC_ERR_INT_EIMR 0x0010
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static inline u32 mpic_fsl_err_read(u32 __iomem *base, unsigned int err_reg)
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{
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return in_be32(base + (err_reg >> 2));
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}
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static inline void mpic_fsl_err_write(u32 __iomem *base, u32 value)
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{
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out_be32(base + (MPIC_ERR_INT_EIMR >> 2), value);
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}
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static void fsl_mpic_mask_err(struct irq_data *d)
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{
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u32 eimr;
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struct mpic *mpic = irq_data_get_irq_chip_data(d);
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unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0];
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eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
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eimr |= (1 << (31 - src));
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mpic_fsl_err_write(mpic->err_regs, eimr);
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}
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static void fsl_mpic_unmask_err(struct irq_data *d)
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{
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u32 eimr;
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struct mpic *mpic = irq_data_get_irq_chip_data(d);
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unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0];
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eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
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eimr &= ~(1 << (31 - src));
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mpic_fsl_err_write(mpic->err_regs, eimr);
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}
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static struct irq_chip fsl_mpic_err_chip = {
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.irq_disable = fsl_mpic_mask_err,
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.irq_mask = fsl_mpic_mask_err,
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.irq_unmask = fsl_mpic_unmask_err,
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};
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int mpic_setup_error_int(struct mpic *mpic, int intvec)
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{
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int i;
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mpic->err_regs = ioremap(mpic->paddr + MPIC_ERR_INT_BASE, 0x1000);
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if (!mpic->err_regs) {
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pr_err("could not map mpic error registers\n");
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return -ENOMEM;
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}
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mpic->hc_err = fsl_mpic_err_chip;
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mpic->hc_err.name = mpic->name;
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mpic->flags |= MPIC_FSL_HAS_EIMR;
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/* allocate interrupt vectors for error interrupts */
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for (i = MPIC_MAX_ERR - 1; i >= 0; i--)
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mpic->err_int_vecs[i] = --intvec;
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return 0;
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}
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int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw)
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{
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if ((mpic->flags & MPIC_FSL_HAS_EIMR) &&
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(hw >= mpic->err_int_vecs[0] &&
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hw <= mpic->err_int_vecs[MPIC_MAX_ERR - 1])) {
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WARN_ON(mpic->flags & MPIC_SECONDARY);
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pr_debug("mpic: mapping as Error Interrupt\n");
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irq_set_chip_data(virq, mpic);
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irq_set_chip_and_handler(virq, &mpic->hc_err,
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handle_level_irq);
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return 1;
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}
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return 0;
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}
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static irqreturn_t fsl_error_int_handler(int irq, void *data)
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{
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struct mpic *mpic = (struct mpic *) data;
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u32 eisr, eimr;
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int errint;
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unsigned int cascade_irq;
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eisr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EISR);
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eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
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if (!(eisr & ~eimr))
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return IRQ_NONE;
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while (eisr) {
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errint = __builtin_clz(eisr);
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cascade_irq = irq_linear_revmap(mpic->irqhost,
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mpic->err_int_vecs[errint]);
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WARN_ON(cascade_irq == NO_IRQ);
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if (cascade_irq != NO_IRQ) {
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generic_handle_irq(cascade_irq);
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} else {
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eimr |= 1 << (31 - errint);
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mpic_fsl_err_write(mpic->err_regs, eimr);
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}
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eisr &= ~(1 << (31 - errint));
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}
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return IRQ_HANDLED;
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}
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void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
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{
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unsigned int virq;
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int ret;
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virq = irq_create_mapping(mpic->irqhost, irqnum);
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if (virq == NO_IRQ) {
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pr_err("Error interrupt setup failed\n");
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return;
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}
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/* Mask all error interrupts */
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mpic_fsl_err_write(mpic->err_regs, ~0);
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ret = request_irq(virq, fsl_error_int_handler, IRQF_NO_THREAD,
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"mpic-error-int", mpic);
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if (ret)
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pr_err("Failed to register error interrupt handler\n");
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}
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@ -1026,6 +1026,9 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
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return 0;
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}
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if (mpic_map_error_int(mpic, virq, hw))
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return 0;
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if (hw >= mpic->num_sources)
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return -EINVAL;
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@ -1085,7 +1088,16 @@ static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
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*/
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switch (intspec[2]) {
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case 0:
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case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
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break;
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case 1:
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if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
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break;
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if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
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return -EINVAL;
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*out_hwirq = mpic->err_int_vecs[intspec[3]];
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break;
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case 2:
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if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
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@ -1302,6 +1314,9 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
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if (mpic->flags & MPIC_FSL) {
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u32 brr1, version;
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int ret;
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/*
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* Yes, Freescale really did put global registers in the
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* magic per-cpu area -- and they don't even show up in the
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@ -1309,6 +1324,29 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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*/
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mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
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MPIC_CPU_THISBASE, 0x1000);
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brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
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MPIC_FSL_BRR1);
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version = brr1 & MPIC_FSL_BRR1_VER;
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/* Error interrupt mask register (EIMR) is required for
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* handling individual device error interrupts. EIMR
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* was added in MPIC version 4.1.
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*
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* Over here we reserve vector number space for error
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* interrupt vectors. This space is stolen from the
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* global vector number space, as in case of ipis
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* and timer interrupts.
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*
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* Available vector space = intvec_top - 12, where 12
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* is the number of vectors which have been consumed by
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* ipis and timer interrupts.
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*/
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if (version >= 0x401) {
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ret = mpic_setup_error_int(mpic, intvec_top - 12);
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if (ret)
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return NULL;
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}
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}
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/* Reset */
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@ -1474,6 +1512,10 @@ void __init mpic_init(struct mpic *mpic)
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num_timers = 8;
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}
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/* FSL mpic error interrupt intialization */
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if (mpic->flags & MPIC_FSL_HAS_EIMR)
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mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
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/* Initialize timers to our reserved vectors and mask them for now */
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for (i = 0; i < num_timers; i++) {
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unsigned int offset = mpic_tm_offset(mpic, i);
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@ -40,4 +40,26 @@ extern int mpic_set_affinity(struct irq_data *d,
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const struct cpumask *cpumask, bool force);
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extern void mpic_reset_core(int cpu);
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#ifdef CONFIG_FSL_SOC
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extern int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw);
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extern void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum);
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extern int mpic_setup_error_int(struct mpic *mpic, int intvec);
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#else
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static inline int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw)
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{
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return 0;
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}
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static inline void mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
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{
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return;
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}
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static inline int mpic_setup_error_int(struct mpic *mpic, int intvec)
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{
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return -1;
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}
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#endif
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#endif /* _POWERPC_SYSDEV_MPIC_H */
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