dect
/
linux-2.6
Archived
13
0
Fork 0
Code Releases Activity

staging: rtl8192e: Remove files that are not used 

For the most part, these extra files came from the previous version
of the RTL8192E driver.

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2011-08-24 19:29:57 -05:00
parent 9de9f962c7
commit 09505184ec
24 changed files with 0 additions and 29480 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
drivers/staging/rtl8192e/internal.h
View File

@ -1,93 +0,0 @@
/*
* Cryptographic API.
*
* Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
*/
#ifndef _CRYPTO_INTERNAL_H
#define _CRYPTO_INTERNAL_H
#include <linux/version.h>
#include "rtl_crypto.h"
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/init.h>
#include <linux/hardirq.h>
#include <linux/sched.h>
#include <asm/kmap_types.h>
extern enum km_type crypto_km_types[];
static inline enum km_type crypto_kmap_type(int out)
{
return crypto_km_types[(in_softirq() ? 2 : 0) + out];
}
static inline void *crypto_kmap(struct page *page, int out)
{
return kmap_atomic(page, crypto_kmap_type(out));
}
static inline void crypto_kunmap(void *vaddr, int out)
{
kunmap_atomic(vaddr, crypto_kmap_type(out));
}
static inline void crypto_yield(struct crypto_tfm *tfm)
{
if (!in_softirq())
cond_resched();
}
static inline void *crypto_tfm_ctx(struct crypto_tfm *tfm)
{
return (void *)&tfm[1];
}
struct crypto_alg *crypto_alg_lookup(const char *name);
#ifdef CONFIG_KMOD
void crypto_alg_autoload(const char *name);
struct crypto_alg *crypto_alg_mod_lookup(const char *name);
#else
static inline struct crypto_alg *crypto_alg_mod_lookup(const char *name)
{
return crypto_alg_lookup(name);
}
#endif
static inline int crypto_alloc_hmac_block(struct crypto_tfm *tfm)
{
return 0;
}
static inline void crypto_free_hmac_block(struct crypto_tfm *tfm)
{ }
#ifdef CONFIG_PROC_FS
void __init crypto_init_proc(void);
#else
static inline void crypto_init_proc(void)
{ }
#endif
int crypto_init_digest_flags(struct crypto_tfm *tfm, u32 flags);
int crypto_init_cipher_flags(struct crypto_tfm *tfm, u32 flags);
int crypto_init_compress_flags(struct crypto_tfm *tfm, u32 flags);
int crypto_init_digest_ops(struct crypto_tfm *tfm);
int crypto_init_cipher_ops(struct crypto_tfm *tfm);
int crypto_init_compress_ops(struct crypto_tfm *tfm);
void crypto_exit_digest_ops(struct crypto_tfm *tfm);
void crypto_exit_cipher_ops(struct crypto_tfm *tfm);
void crypto_exit_compress_ops(struct crypto_tfm *tfm);
#endif /* _CRYPTO_INTERNAL_H */

20
drivers/staging/rtl8192e/kmap_types.h
View File

@ -1,20 +0,0 @@
#ifndef __KMAP_TYPES_H
#define __KMAP_TYPES_H
enum km_type {
KM_BOUNCE_READ,
KM_SKB_SUNRPC_DATA,
KM_SKB_DATA_SOFTIRQ,
KM_USER0,
KM_USER1,
KM_BH_IRQ,
KM_SOFTIRQ0,
KM_SOFTIRQ1,
KM_TYPE_NR
};
#define _ASM_KMAP_TYPES_H
#endif

141
drivers/staging/rtl8192e/r8180_93cx6.c
View File

@ -1,141 +0,0 @@
/*
This files contains card eeprom (93c46 or 93c56) programming routines,
memory is addressed by 16 bits words.
This is part of rtl8180 OpenSource driver.
Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
Released under the terms of GPL (General Public Licence)
Parts of this driver are based on the GPL part of the
official realtek driver.
Parts of this driver are based on the rtl8180 driver skeleton
from Patric Schenke & Andres Salomon.
Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
We want to tanks the Authors of those projects and the Ndiswrapper
project Authors.
*/
#include "r8180_93cx6.h"
static void eprom_cs(struct r8192_priv *priv, short bit)
{
if (bit)
write_nic_byte(priv, EPROM_CMD,
(1<<EPROM_CS_SHIFT) |
read_nic_byte(priv, EPROM_CMD)); //enable EPROM
else
write_nic_byte(priv, EPROM_CMD, read_nic_byte(priv, EPROM_CMD)
&~(1<<EPROM_CS_SHIFT)); //disable EPROM
udelay(EPROM_DELAY);
}
static void eprom_ck_cycle(struct r8192_priv *priv)
{
write_nic_byte(priv, EPROM_CMD,
(1<<EPROM_CK_SHIFT) | read_nic_byte(priv, EPROM_CMD));
udelay(EPROM_DELAY);
write_nic_byte(priv, EPROM_CMD,
read_nic_byte(priv, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT));
udelay(EPROM_DELAY);
}
static void eprom_w(struct r8192_priv *priv, short bit)
{
if (bit)
write_nic_byte(priv, EPROM_CMD, (1<<EPROM_W_SHIFT) |
read_nic_byte(priv, EPROM_CMD));
else
write_nic_byte(priv, EPROM_CMD, read_nic_byte(priv, EPROM_CMD)
&~(1<<EPROM_W_SHIFT));
udelay(EPROM_DELAY);
}
static short eprom_r(struct r8192_priv *priv)
{
short bit;
bit = (read_nic_byte(priv, EPROM_CMD) & (1<<EPROM_R_SHIFT));
udelay(EPROM_DELAY);
if (bit)
return 1;
return 0;
}
static void eprom_send_bits_string(struct r8192_priv *priv, short b[], int len)
{
int i;
for (i = 0; i < len; i++) {
eprom_w(priv, b[i]);
eprom_ck_cycle(priv);
}
}
u32 eprom_read(struct r8192_priv *priv, u32 addr)
{
short read_cmd[] = {1, 1, 0};
short addr_str[8];
int i;
int addr_len;
u32 ret;
ret = 0;
//enable EPROM programming
write_nic_byte(priv, EPROM_CMD,
(EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT));
udelay(EPROM_DELAY);
if (priv->epromtype == EPROM_93c56) {
addr_str[7] = addr & 1;
addr_str[6] = addr & (1<<1);
addr_str[5] = addr & (1<<2);
addr_str[4] = addr & (1<<3);
addr_str[3] = addr & (1<<4);
addr_str[2] = addr & (1<<5);
addr_str[1] = addr & (1<<6);
addr_str[0] = addr & (1<<7);
addr_len = 8;
} else {
addr_str[5] = addr & 1;
addr_str[4] = addr & (1<<1);
addr_str[3] = addr & (1<<2);
addr_str[2] = addr & (1<<3);
addr_str[1] = addr & (1<<4);
addr_str[0] = addr & (1<<5);
addr_len = 6;
}
eprom_cs(priv, 1);
eprom_ck_cycle(priv);
eprom_send_bits_string(priv, read_cmd, 3);
eprom_send_bits_string(priv, addr_str, addr_len);
//keep chip pin D to low state while reading.
//I'm unsure if it is necessary, but anyway shouldn't hurt
eprom_w(priv, 0);
for (i = 0; i < 16; i++) {
//eeprom needs a clk cycle between writing opcode&adr
//and reading data. (eeprom outs a dummy 0)
eprom_ck_cycle(priv);
ret |= (eprom_r(priv)<<(15-i));
}
eprom_cs(priv, 0);
eprom_ck_cycle(priv);
//disable EPROM programming
write_nic_byte(priv, EPROM_CMD,
(EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT));
return ret;
}

41
drivers/staging/rtl8192e/r8180_93cx6.h
View File

@ -1,41 +0,0 @@
/* r8180_93cx6.h - 93c46 or 93c56 eeprom card programming routines
*
* This is part of rtl8187 OpenSource driver
* Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
* Released under the terms of GPL (General Public Licence)
* Parts of this driver are based on the GPL part of the official realtek driver
*
* Parts of this driver are based on the rtl8180 driver skeleton from
* Patric Schenke & Andres Salomon.
*
* Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
*
* We want to thank the authors of the above mentioned projects and to
* the authors of the Ndiswrapper project.
*/
#include "r8192E.h"
#include "r8192E_hw.h"
#define EPROM_DELAY 10
#define EPROM_ANAPARAM_ADDRLWORD 0xd
#define EPROM_ANAPARAM_ADDRHWORD 0xe
#define EPROM_RFCHIPID 0x6
#define EPROM_TXPW_BASE 0x05
#define EPROM_RFCHIPID_RTL8225U 5
#define EPROM_RF_PARAM 0x4
#define EPROM_CONFIG2 0xc
#define EPROM_VERSION 0x1E
#define MAC_ADR 0x7
#define CIS 0x18
#define EPROM_TXPW0 0x16
#define EPROM_TXPW2 0x1b
#define EPROM_TXPW1 0x3d
/* Reads a 16 bits word. */
u32 eprom_read(struct r8192_priv *priv, u32 addr);

4538
drivers/staging/rtl8192e/r8190P_hwimg.c
View File

File diff suppressed because it is too large Load Diff

51
drivers/staging/rtl8192e/r8190P_hwimg.h
View File

@ -1,51 +0,0 @@
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef __INC_HAL8190Pci_FW_IMG_H
#define __INC_HAL8190Pci_FW_IMG_H
/*Created on 2008/12/ 3, 3:26*/
#include <linux/types.h>
#define BootArrayLengthPci 344
extern u8 Rtl8190PciFwBootArray[BootArrayLengthPci];
#define MainArrayLengthPci 55388
extern u8 Rtl8190PciFwMainArray[MainArrayLengthPci];
#define DataArrayLengthPci 2960
extern u8 Rtl8190PciFwDataArray[DataArrayLengthPci];
#define PHY_REGArrayLengthPci 280
extern u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLengthPci];
#define PHY_REG_1T2RArrayLengthPci 280
extern u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPci];
#define RadioA_ArrayLengthPci 246
extern u32 Rtl8190PciRadioA_Array[RadioA_ArrayLengthPci] ;
#define RadioB_ArrayLengthPci 78
extern u32 Rtl8190PciRadioB_Array[RadioB_ArrayLengthPci] ;
#define RadioC_ArrayLengthPci 246
extern u32 Rtl8190PciRadioC_Array[RadioC_ArrayLengthPci] ;
#define RadioD_ArrayLengthPci 78
extern u32 Rtl8190PciRadioD_Array[RadioD_ArrayLengthPci] ;
#define MACPHY_ArrayLengthPci 18
extern u32 Rtl8190PciMACPHY_Array[MACPHY_ArrayLengthPci] ;
#define MACPHY_Array_PGLengthPci 21
extern u32 Rtl8190PciMACPHY_Array_PG[MACPHY_Array_PGLengthPci] ;
#define AGCTAB_ArrayLengthPci 384
extern u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLengthPci] ;
#endif

677
drivers/staging/rtl8192e/r8190_rtl8256.c
View File

@ -1,677 +0,0 @@
/*
This is part of the rtl8192 driver
released under the GPL (See file COPYING for details).
This files contains programming code for the rtl8256
radio frontend.
*Many* thanks to Realtek Corp. for their great support!
*/
#include "r8192E.h"
#include "r8192E_hw.h"
#include "r819xE_phyreg.h"
#include "r819xE_phy.h"
#include "r8190_rtl8256.h"
/*--------------------------------------------------------------------------
* Overview: set RF band width (20M or 40M)
* Input: struct net_device* dev
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
* Output: NONE
* Return: NONE
* Note: 8226 support both 20M and 40 MHz
*---------------------------------------------------------------------------*/
void PHY_SetRF8256Bandwidth(struct r8192_priv *priv, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
{
u8 eRFPath;
//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
continue;
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
if(priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later!
{
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);
//cosa add for sd3's request 01/23/2008
//rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
}
else
{
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
}
break;
case HT_CHANNEL_WIDTH_20_40:
if(priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later!
{
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff);
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1);
}
else
{
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
}
break;
default:
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
}
/*--------------------------------------------------------------------------
* Overview: Interface to config 8256
* Input: struct net_device* dev
* Output: NONE
* Return: NONE
*---------------------------------------------------------------------------*/
RT_STATUS PHY_RF8256_Config(struct r8192_priv *priv)
{
// Initialize general global value
//
RT_STATUS rtStatus = RT_STATUS_SUCCESS;
// TODO: Extend RF_PATH_C and RF_PATH_D in the future
priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
// Config BB and RF
rtStatus = phy_RF8256_Config_ParaFile(priv);
return rtStatus;
}
/*--------------------------------------------------------------------------
* Overview: Interface to config 8256
* Input: struct net_device* dev
* Output: NONE
* Return: NONE
*---------------------------------------------------------------------------*/
RT_STATUS phy_RF8256_Config_ParaFile(struct r8192_priv *priv)
{
u32 u4RegValue = 0;
u8 eRFPath;
RT_STATUS rtStatus = RT_STATUS_SUCCESS;
BB_REGISTER_DEFINITION_T *pPhyReg;
u32 RegOffSetToBeCheck = 0x3;
u32 RegValueToBeCheck = 0x7f1;
u32 RF3_Final_Value = 0;
u8 ConstRetryTimes = 5, RetryTimes = 5;
u8 ret = 0;
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
continue;
pPhyReg = &priv->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = rtl8192_QueryBBReg(priv, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF90_PATH_B :
case RF90_PATH_D:
u4RegValue = rtl8192_QueryBBReg(priv, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
rtl8192_setBBreg(priv, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
/*----Set RF_ENV output high----*/
rtl8192_setBBreg(priv, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
/* Set bit number of Address and Data for RF register */
rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
/*----Check RF block (for FPGA platform only)----*/
// TODO: this function should be removed on ASIC , Emily 2007.2.2
rtStatus = rtl8192_phy_checkBBAndRF(priv, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath);
if(rtStatus!= RT_STATUS_SUCCESS)
{
RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
}
RetryTimes = ConstRetryTimes;
RF3_Final_Value = 0;
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF90_PATH_A:
while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
{
ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_B:
while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
{
ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_C:
while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
{
ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_D:
while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
{
ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
rtl8192_setBBreg(priv, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF90_PATH_B :
case RF90_PATH_D:
rtl8192_setBBreg(priv, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(ret){
RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
}
}
RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ;
return RT_STATUS_SUCCESS;
phy_RF8256_Config_ParaFile_Fail:
RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ;
return RT_STATUS_FAILURE;
}
void PHY_SetRF8256CCKTxPower(struct r8192_priv *priv, u8 powerlevel)
{
u32 TxAGC=0;
TxAGC = powerlevel;
if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range
{
if(priv->CustomerID == RT_CID_819x_Netcore)
TxAGC = 0x22;
else
TxAGC += priv->CckPwEnl;
}
if(TxAGC > 0x24)
TxAGC = 0x24;
rtl8192_setBBreg(priv, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
}
void PHY_SetRF8256OFDMTxPower(struct r8192_priv *priv, u8 powerlevel)
{
u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
u8 index = 0;
u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
u8 byte0, byte1, byte2, byte3;
powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; //OFDM rates
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
powerBase1 = powerlevel; //MCS rates
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
for(index=0; index<6; index++)
{
writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
byte0 = (u8)(writeVal & 0x7f);
byte1 = (u8)((writeVal & 0x7f00)>>8);
byte2 = (u8)((writeVal & 0x7f0000)>>16);
byte3 = (u8)((writeVal & 0x7f000000)>>24);
if(byte0 > 0x24) // Max power index = 0x24
byte0 = 0x24;
if(byte1 > 0x24)
byte1 = 0x24;
if(byte2 > 0x24)
byte2 = 0x24;
if(byte3 > 0x24)
byte3 = 0x24;
if(index == 3)
{
writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
priv->Pwr_Track = writeVal_tmp;
}
if(priv->bDynamicTxHighPower == true) //Add by Jacken 2008/03/06 //when DM implement, add this
{
writeVal = 0x03030303;
}
else
{
writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
}
rtl8192_setBBreg(priv, RegOffset[index], 0x7f7f7f7f, writeVal);
}
}
#define MAX_DOZE_WAITING_TIMES_9x 64
static void r8192e_drain_tx_queues(struct r8192_priv *priv)
{
u8 i, QueueID;
for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
{
struct rtl8192_tx_ring *ring = &priv->tx_ring[QueueID];
if(skb_queue_len(&ring->queue) == 0)
{
QueueID++;
continue;
}
udelay(10);
i++;
if (i >= MAX_DOZE_WAITING_TIMES_9x)
{
RT_TRACE(COMP_POWER, "r8192e_drain_tx_queues() timeout queue %d\n", QueueID);
break;
}
}
}
static bool SetRFPowerState8190(struct r8192_priv *priv,
RT_RF_POWER_STATE eRFPowerState)
{
PRT_POWER_SAVE_CONTROL pPSC = &priv->PowerSaveControl;
bool bResult = true;
if (eRFPowerState == priv->eRFPowerState &&
priv->bHwRfOffAction == 0) {
bResult = false;
goto out;
}
switch( eRFPowerState )
{
case eRfOn:
// turn on RF
if ((priv->eRFPowerState == eRfOff) &&
RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
{
/*
* The current RF state is OFF and the RF OFF level
* is halting the NIC, re-initialize the NIC.
*/
if (!NicIFEnableNIC(priv)) {
RT_TRACE(COMP_ERR, "%s(): NicIFEnableNIC failed\n",__FUNCTION__);
bResult = false;
goto out;
}
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
} else {
write_nic_byte(priv, ANAPAR, 0x37);//160MHz
mdelay(1);
//enable clock 80/88 MHz
rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]
priv->bHwRfOffAction = 0;
//RF-A, RF-B
//enable RF-Chip A/B
rtl8192_setBBreg(priv, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
//analog to digital on
rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
//digital to analog on
rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
//rx antenna on
rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
//rx antenna on
rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
//analog to digital part2 on
rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
}
break;
//
// In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
// By Bruce, 2008-01-16.
//
case eRfSleep:
// HW setting had been configured with deeper mode.
if(priv->eRFPowerState == eRfOff)
break;
r8192e_drain_tx_queues(priv);
PHY_SetRtl8192eRfOff(priv);
break;
case eRfOff:
//
// Disconnect with Any AP or STA.
//
r8192e_drain_tx_queues(priv);
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
{
/* Disable all components. */
NicIFDisableNIC(priv);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
}
else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))
{
/* Normal case - IPS should go to this. */
PHY_SetRtl8192eRfOff(priv);
}
break;
default:
bResult = false;
RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState);
break;
}
if(bResult)
{
// Update current RF state variable.
priv->eRFPowerState = eRFPowerState;
}
out:
return bResult;
}
static void MgntDisconnectIBSS(struct r8192_priv *priv)
{
u8 i;
bool bFilterOutNonAssociatedBSSID = false;
priv->ieee80211->state = IEEE80211_NOLINK;
for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i]= 0x55;
priv->OpMode = RT_OP_MODE_NO_LINK;
write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
{
RT_OP_MODE OpMode = priv->OpMode;
u8 btMsr = read_nic_byte(priv, MSR);
btMsr &= 0xfc;
switch(OpMode)
{
case RT_OP_MODE_INFRASTRUCTURE:
btMsr |= MSR_LINK_MANAGED;
break;
case RT_OP_MODE_IBSS:
btMsr |= MSR_LINK_ADHOC;
// led link set separate
break;
case RT_OP_MODE_AP:
btMsr |= MSR_LINK_MASTER;
break;
default:
btMsr |= MSR_LINK_NONE;
break;
}
write_nic_byte(priv, MSR, btMsr);
}
ieee80211_stop_send_beacons(priv->ieee80211);
// If disconnect, clear RCR CBSSID bit
bFilterOutNonAssociatedBSSID = false;
{
u32 RegRCR, Type;
Type = bFilterOutNonAssociatedBSSID;
RegRCR = read_nic_dword(priv, RCR);
priv->ReceiveConfig = RegRCR;
if (Type == true)
RegRCR |= (RCR_CBSSID);
else if (Type == false)
RegRCR &= (~RCR_CBSSID);
{
write_nic_dword(priv, RCR, RegRCR);
priv->ReceiveConfig = RegRCR;
}
}
notify_wx_assoc_event(priv->ieee80211);
}
static void MlmeDisassociateRequest(struct r8192_priv *priv, u8 *asSta,
u8 asRsn)
{
u8 i;
RemovePeerTS(priv->ieee80211, asSta);
SendDisassociation( priv->ieee80211, asSta, asRsn );
if(memcpy(priv->ieee80211->current_network.bssid,asSta,6) == NULL)
{
//ShuChen TODO: change media status.
//ShuChen TODO: What to do when disassociate.
priv->ieee80211->state = IEEE80211_NOLINK;
for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22;
priv->OpMode = RT_OP_MODE_NO_LINK;
{
RT_OP_MODE OpMode = priv->OpMode;
u8 btMsr = read_nic_byte(priv, MSR);
btMsr &= 0xfc;
switch(OpMode)
{
case RT_OP_MODE_INFRASTRUCTURE:
btMsr |= MSR_LINK_MANAGED;
break;
case RT_OP_MODE_IBSS:
btMsr |= MSR_LINK_ADHOC;
// led link set separate
break;
case RT_OP_MODE_AP:
btMsr |= MSR_LINK_MASTER;
break;
default:
btMsr |= MSR_LINK_NONE;
break;
}
write_nic_byte(priv, MSR, btMsr);
}
ieee80211_disassociate(priv->ieee80211);
write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
}
}
static void MgntDisconnectAP(struct r8192_priv *priv, u8 asRsn)
{
bool bFilterOutNonAssociatedBSSID = false;
u32 RegRCR, Type;
/* If disconnect, clear RCR CBSSID bit */
bFilterOutNonAssociatedBSSID = false;
Type = bFilterOutNonAssociatedBSSID;
RegRCR = read_nic_dword(priv, RCR);
priv->ReceiveConfig = RegRCR;
if (Type == true)
RegRCR |= (RCR_CBSSID);
else if (Type == false)
RegRCR &= (~RCR_CBSSID);
write_nic_dword(priv, RCR, RegRCR);
priv->ReceiveConfig = RegRCR;
MlmeDisassociateRequest(priv, priv->ieee80211->current_network.bssid, asRsn);
priv->ieee80211->state = IEEE80211_NOLINK;
}
static bool MgntDisconnect(struct r8192_priv *priv, u8 asRsn)
{
// In adhoc mode, update beacon frame.
if( priv->ieee80211->state == IEEE80211_LINKED )
{
if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
{
MgntDisconnectIBSS(priv);
}
if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
{
// We clear key here instead of MgntDisconnectAP() because that
// MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
// e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
// used to handle disassociation related things to AP, e.g. send Disassoc
// frame to AP. 2005.01.27, by rcnjko.
MgntDisconnectAP(priv, asRsn);
}
}
return true;
}
//
// Description:
// Chang RF Power State.
// Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
//
// Assumption:
// PASSIVE LEVEL.
//
bool MgntActSet_RF_State(struct r8192_priv *priv, RT_RF_POWER_STATE StateToSet,
RT_RF_CHANGE_SOURCE ChangeSource)
{
bool bActionAllowed = false;
bool bConnectBySSID = false;
RT_RF_POWER_STATE rtState;
RT_TRACE(COMP_POWER, "===>MgntActSet_RF_State(): StateToSet(%d)\n",StateToSet);
spin_lock(&priv->rf_ps_lock);
rtState = priv->eRFPowerState;
switch(StateToSet)
{
case eRfOn:
priv->RfOffReason &= (~ChangeSource);
if (!priv->RfOffReason)
{
priv->RfOffReason = 0;
bActionAllowed = true;
if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW )
{
bConnectBySSID = true;
}
}
else
RT_TRACE(COMP_POWER, "MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", priv->RfOffReason, ChangeSource);
break;
case eRfOff:
if (priv->RfOffReason > RF_CHANGE_BY_IPS)
{
// Disconnect to current BSS when radio off. Asked by QuanTa.
MgntDisconnect(priv, disas_lv_ss);
}
priv->RfOffReason |= ChangeSource;
bActionAllowed = true;
break;
case eRfSleep:
priv->RfOffReason |= ChangeSource;
bActionAllowed = true;
break;
}
if (bActionAllowed)
{
RT_TRACE(COMP_POWER, "MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
// Config HW to the specified mode.
SetRFPowerState8190(priv, StateToSet);
}
else
{
RT_TRACE(COMP_POWER, "MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
}
// Release RF spinlock
spin_unlock(&priv->rf_ps_lock);
RT_TRACE(COMP_POWER, "<===MgntActSet_RF_State()\n");
return bActionAllowed;
}

29
drivers/staging/rtl8192e/r8190_rtl8256.h
View File

@ -1,29 +0,0 @@
/* r8190_rtl8256.h - rtl8256 radio frontend
*
* This is part of the rtl8180-sa2400 driver
* released under the GPL (See file COPYING for details).
* Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
*
* Many thanks to Realtek Corp. for their great support!
*/
#ifndef RTL8225_H
#define RTL8225_H
#define RTL819X_TOTAL_RF_PATH 2 /* for 8192E */
void PHY_SetRF8256Bandwidth(struct r8192_priv *priv,
HT_CHANNEL_WIDTH Bandwidth);
RT_STATUS PHY_RF8256_Config(struct r8192_priv *priv);
RT_STATUS phy_RF8256_Config_ParaFile(struct r8192_priv *priv);
void PHY_SetRF8256CCKTxPower(struct r8192_priv *priv, u8 powerlevel);
void PHY_SetRF8256OFDMTxPower(struct r8192_priv *priv, u8 powerlevel);
bool MgntActSet_RF_State(struct r8192_priv *priv,
RT_RF_POWER_STATE StateToSet,
RT_RF_CHANGE_SOURCE ChangeSource);
#endif /* RTL8225_H */

1148
drivers/staging/rtl8192e/r8192E.h
View File

File diff suppressed because it is too large Load Diff

5039
drivers/staging/rtl8192e/r8192E_core.c
View File

File diff suppressed because it is too large Load Diff

5039
drivers/staging/rtl8192e/r8192E_core.c.porig
View File

File diff suppressed because it is too large Load Diff

5036
drivers/staging/rtl8192e/r8192E_core.c.rej
View File

File diff suppressed because it is too large Load Diff

2554
drivers/staging/rtl8192e/r8192E_dm.c
View File

File diff suppressed because it is too large Load Diff

228
drivers/staging/rtl8192e/r8192E_dm.h
View File

@ -1,228 +0,0 @@
/*****************************************************************************
* Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved.
*
* Module: Hal819xUsbDM.h (RTL8192 Header H File)
*
*
* Note: For dynamic control definition constant structure.
*
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
* 10/04/2007 MHC Create initial version.
*
*****************************************************************************/
#ifndef __R8192UDM_H__
#define __R8192UDM_H__
#define OFDM_Table_Length 19
#define CCK_Table_length 12
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_DIG_HIGH_PWR_THRESH_HIGH 75
#define DM_DIG_HIGH_PWR_THRESH_LOW 70
#define BW_AUTO_SWITCH_HIGH_LOW 25
#define BW_AUTO_SWITCH_LOW_HIGH 30
#define DM_check_fsync_time_interval 500
#define DM_DIG_BACKOFF 12
#define DM_DIG_MAX 0x36
#define DM_DIG_MIN 0x1c
#define DM_DIG_MIN_Netcore 0x12
#define RxPathSelection_SS_TH_low 30
#define RxPathSelection_diff_TH 18
#define RateAdaptiveTH_High 50
#define RateAdaptiveTH_Low_20M 30
#define RateAdaptiveTH_Low_40M 10
#define VeryLowRSSI 15
#define CTSToSelfTHVal 35
//defined by vivi, for tx power track
#define E_FOR_TX_POWER_TRACK 300
//Dynamic Tx Power Control Threshold
#define TX_POWER_NEAR_FIELD_THRESH_HIGH 68
#define TX_POWER_NEAR_FIELD_THRESH_LOW 62
//added by amy for atheros AP
#define TX_POWER_ATHEROAP_THRESH_HIGH 78
#define TX_POWER_ATHEROAP_THRESH_LOW 72
//defined by vivi, for showing on UI. Newer firmware has changed to 0x1e0
#define Current_Tx_Rate_Reg 0x1e0//0x1b8
#define Initial_Tx_Rate_Reg 0x1e1 //0x1b9
#define Tx_Retry_Count_Reg 0x1ac
#define RegC38_TH 20
/* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
typedef struct _dynamic_initial_gain_threshold_
{
u8 dig_enable_flag;
u8 dig_algorithm;
u8 dbg_mode;
u8 dig_algorithm_switch;
long rssi_low_thresh;
long rssi_high_thresh;
long rssi_high_power_lowthresh;
long rssi_high_power_highthresh;
u8 dig_state;
u8 dig_highpwr_state;
u8 cur_connect_state;
u8 pre_connect_state;
u8 curpd_thstate;
u8 prepd_thstate;
u8 curcs_ratio_state;
u8 precs_ratio_state;
u32 pre_ig_value;
u32 cur_ig_value;
u8 backoff_val;
u8 rx_gain_range_max;
u8 rx_gain_range_min;
bool initialgain_lowerbound_state;
long rssi_val;
}dig_t;
typedef enum tag_dynamic_init_gain_state_definition
{
DM_STA_DIG_OFF = 0,
DM_STA_DIG_ON,
DM_STA_DIG_MAX
}dm_dig_sta_e;
/* 2007/10/08 MH Define RATR state. */
typedef enum tag_dynamic_ratr_state_definition
{
DM_RATR_STA_HIGH = 0,
DM_RATR_STA_MIDDLE = 1,
DM_RATR_STA_LOW = 2,
DM_RATR_STA_MAX
}dm_ratr_sta_e;
/* 2007/10/11 MH Define DIG operation type. */
typedef enum tag_dynamic_init_gain_operation_type_definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_THRESH_HIGHPWR_HIGH = 2,
DIG_TYPE_THRESH_HIGHPWR_LOW = 3,
DIG_TYPE_DBG_MODE = 4,
DIG_TYPE_RSSI = 5,
DIG_TYPE_ALGORITHM = 6,
DIG_TYPE_BACKOFF = 7,
DIG_TYPE_PWDB_FACTOR = 8,
DIG_TYPE_RX_GAIN_MIN = 9,
DIG_TYPE_RX_GAIN_MAX = 10,
DIG_TYPE_ENABLE = 20,
DIG_TYPE_DISABLE = 30,
DIG_OP_TYPE_MAX
}dm_dig_op_e;
typedef enum tag_dig_algorithm_definition
{
DIG_ALGO_BY_FALSE_ALARM = 0,
DIG_ALGO_BY_RSSI = 1,
DIG_ALGO_MAX
}dm_dig_alg_e;
typedef enum tag_dig_dbgmode_definition
{
DIG_DBG_OFF = 0,
DIG_DBG_ON = 1,
DIG_DBG_MAX
}dm_dig_dbg_e;
typedef enum tag_dig_connect_definition
{
DIG_DISCONNECT = 0,
DIG_CONNECT = 1,
DIG_CONNECT_MAX
}dm_dig_connect_e;
typedef enum tag_dig_packetdetection_threshold_definition
{
DIG_PD_AT_LOW_POWER = 0,
DIG_PD_AT_NORMAL_POWER = 1,
DIG_PD_AT_HIGH_POWER = 2,
DIG_PD_MAX
}dm_dig_pd_th_e;
typedef enum tag_dig_cck_cs_ratio_state_definition
{
DIG_CS_RATIO_LOWER = 0,
DIG_CS_RATIO_HIGHER = 1,
DIG_CS_MAX
}dm_dig_cs_ratio_e;
typedef struct _Dynamic_Rx_Path_Selection_
{
u8 Enable;
u8 DbgMode;
u8 cck_method;
u8 cck_Rx_path;
u8 SS_TH_low;
u8 diff_TH;
u8 disabledRF;
u8 reserved;
u8 rf_rssi[4];
u8 rf_enable_rssi_th[4];
long cck_pwdb_sta[4];
}DRxPathSel;
typedef enum tag_CCK_Rx_Path_Method_Definition
{
CCK_Rx_Version_1 = 0,
CCK_Rx_Version_2= 1,
CCK_Rx_Version_MAX
}DM_CCK_Rx_Path_Method;
typedef enum tag_DM_DbgMode_Definition
{
DM_DBG_OFF = 0,
DM_DBG_ON = 1,
DM_DBG_MAX
}DM_DBG_E;
typedef struct tag_Tx_Config_Cmd_Format
{
u32 Op; /* Command packet type. */
u32 Length; /* Command packet length. */
u32 Value;
}DCMD_TXCMD_T, *PDCMD_TXCMD_T;
extern dig_t dm_digtable;
extern DRxPathSel DM_RxPathSelTable;
void init_hal_dm(struct r8192_priv *priv);
void deinit_hal_dm(struct r8192_priv *priv);
void hal_dm_watchdog(struct r8192_priv *priv);
void init_rate_adaptive(struct r8192_priv *priv);
void dm_txpower_trackingcallback(struct work_struct *work);
void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
void dm_initialize_txpower_tracking(struct r8192_priv *priv);
void dm_cck_txpower_adjust(struct r8192_priv *priv, bool binch14);
#endif /*__R8192UDM_H__ */

1163
drivers/staging/rtl8192e/r8192E_wx.c
View File

File diff suppressed because it is too large Load Diff

18
drivers/staging/rtl8192e/r8192E_wx.h
View File

@ -1,18 +0,0 @@
/*
This is part of rtl8180 OpenSource driver - v 0.3
Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
Released under the terms of GPL (General Public Licence)
Parts of this driver are based on the GPL part of the official realtek driver
Parts of this driver are based on the rtl8180 driver skeleton from Patric Schenke & Andres Salomon
Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
We want to tanks the Authors of such projects and the Ndiswrapper project Authors.
*/
/* this file (will) contains wireless extension handlers*/
#ifndef R8180_WX_H
#define R8180_WX_H
extern struct iw_handler_def r8192_wx_handlers_def;
#endif

123
drivers/staging/rtl8192e/r8192_pm.c
View File

@ -1,123 +0,0 @@
/*
Power management interface routines.
Written by Mariusz Matuszek.
This code is currently just a placeholder for later work and
does not do anything useful.
This is part of rtl8180 OpenSource driver.
Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
Released under the terms of GPL (General Public Licence)
*/
#include "r8192E.h"
#include "r8192E_hw.h"
#include "r8192_pm.h"
#include "r8190_rtl8256.h"
int rtl8192E_save_state (struct pci_dev *dev, pm_message_t state)
{
printk(KERN_NOTICE "r8192E save state call (state %u).\n", state.event);
return -EAGAIN;
}
int rtl8192E_suspend (struct pci_dev *pdev, pm_message_t state)
{
struct net_device *dev = pci_get_drvdata(pdev);
struct r8192_priv *priv = ieee80211_priv(dev);
u32 ulRegRead;
RT_TRACE(COMP_POWER, "============> r8192E suspend call.\n");
if (!netif_running(dev))
goto out_pci_suspend;
if (dev->netdev_ops->ndo_stop)
dev->netdev_ops->ndo_stop(dev);
// Call MgntActSet_RF_State instead to prevent RF config race condition.
if(!priv->ieee80211->bSupportRemoteWakeUp) {
MgntActSet_RF_State(priv, eRfOff, RF_CHANGE_BY_INIT);
// 2006.11.30. System reset bit
ulRegRead = read_nic_dword(priv, CPU_GEN);
ulRegRead|=CPU_GEN_SYSTEM_RESET;
write_nic_dword(priv, CPU_GEN, ulRegRead);
} else {
//2008.06.03 for WOL
write_nic_dword(priv, WFCRC0, 0xffffffff);
write_nic_dword(priv, WFCRC1, 0xffffffff);
write_nic_dword(priv, WFCRC2, 0xffffffff);
//Write PMR register
write_nic_byte(priv, PMR, 0x5);
//Disable tx, enanble rx
write_nic_byte(priv, MacBlkCtrl, 0xa);
}
out_pci_suspend:
RT_TRACE(COMP_POWER, "r8192E support WOL call??????????????????????\n");
if(priv->ieee80211->bSupportRemoteWakeUp) {
RT_TRACE(COMP_POWER, "r8192E support WOL call!!!!!!!!!!!!!!!!!!.\n");
}
netif_device_detach(dev);
pci_save_state(pdev);
pci_disable_device(pdev);
pci_enable_wake(pdev, pci_choose_state(pdev,state),
priv->ieee80211->bSupportRemoteWakeUp?1:0);
pci_set_power_state(pdev,pci_choose_state(pdev,state));
return 0;
}
int rtl8192E_resume (struct pci_dev *pdev)
{
struct net_device *dev = pci_get_drvdata(pdev);
int err;
u32 val;
RT_TRACE(COMP_POWER, "================>r8192E resume call.\n");
pci_set_power_state(pdev, PCI_D0);
err = pci_enable_device(pdev);
if(err) {
printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
dev->name);
return err;
}
pci_restore_state(pdev);
/*
* Suspend/Resume resets the PCI configuration space, so we have to
* re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
* from interfering with C3 CPU state. pci_restore_state won't help
* here since it only restores the first 64 bytes pci config header.
*/
pci_read_config_dword(pdev, 0x40, &val);
if ((val & 0x0000ff00) != 0) {
pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
}
pci_enable_wake(pdev, PCI_D0, 0);
if(!netif_running(dev))
goto out;
netif_device_attach(dev);
if (dev->netdev_ops->ndo_open)
dev->netdev_ops->ndo_open(dev);
out:
RT_TRACE(COMP_POWER, "<================r8192E resume call.\n");
return 0;
}
int rtl8192E_enable_wake (struct pci_dev *dev, pm_message_t state, int enable)
{
printk(KERN_NOTICE "r8192E enable wake call (state %u, enable %d).\n",
state.event, enable);
return -EAGAIN;
}

24
drivers/staging/rtl8192e/r8192_pm.h
View File

@ -1,24 +0,0 @@
/*
Power management interface routines.
Written by Mariusz Matuszek.
This code is currently just a placeholder for later work and
does not do anything useful.
This is part of rtl8180 OpenSource driver.
Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
Released under the terms of GPL (General Public Licence)
*/
#ifndef R8192E_PM_H
#define R8192E_PM_H
#include <linux/types.h>
#include <linux/pci.h>
int rtl8192E_save_state (struct pci_dev *dev, pm_message_t state);
int rtl8192E_suspend (struct pci_dev *dev, pm_message_t state);
int rtl8192E_resume (struct pci_dev *dev);
int rtl8192E_enable_wake (struct pci_dev *dev, pm_message_t state, int enable);
#endif //R8192E_PM_H

444
drivers/staging/rtl8192e/r819xE_cmdpkt.c
View File

@ -1,444 +0,0 @@
/******************************************************************************
(c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
Module: r819xusb_cmdpkt.c (RTL8190 TX/RX command packet handler Source C File)
Note: The module is responsible for handling TX and RX command packet.
1. TX : Send set and query configuration command packet.
2. RX : Receive tx feedback, beacon state, query configuration
command packet.
Function:
Export:
Abbrev:
History:
Data Who Remark
05/06/2008 amy Create initial version porting from windows driver.
******************************************************************************/
#include "r8192E.h"
#include "r8192E_hw.h"
#include "r819xE_cmdpkt.h"
/*
* Driver internal module can call the API to send message to
* firmware side. For example, you can send a debug command packet.
* Or you can send a request for FW to modify RLX4181 LBUS HW bank.
* Otherwise, you can change MAC/PHT/RF register by firmware at
* run time. We do not support message more than one segment now.
*/
RT_STATUS cmpk_message_handle_tx(
struct r8192_priv *priv,
u8* code_virtual_address,
u32 packettype,
u32 buffer_len)
{
RT_STATUS rt_status = RT_STATUS_SUCCESS;
u16 frag_threshold;
u16 frag_length = 0, frag_offset = 0;
rt_firmware *pfirmware = priv->pFirmware;
struct sk_buff *skb;
unsigned char *seg_ptr;
cb_desc *tcb_desc;
u8 bLastIniPkt;
PTX_FWINFO_8190PCI pTxFwInfo = NULL;
int i;
RT_TRACE(COMP_CMDPKT,"%s(),buffer_len is %d\n",__FUNCTION__,buffer_len);
firmware_init_param(priv);
//Fragmentation might be required
frag_threshold = pfirmware->cmdpacket_frag_thresold;
do {
if((buffer_len - frag_offset) > frag_threshold) {
frag_length = frag_threshold ;
bLastIniPkt = 0;
} else {
frag_length =(u16)(buffer_len - frag_offset);
bLastIniPkt = 1;
}
/* Allocate skb buffer to contain firmware info and tx descriptor info
* add 4 to avoid packet appending overflow.
* */
skb = dev_alloc_skb(frag_length + priv->ieee80211->tx_headroom + 4);
if(skb == NULL) {
rt_status = RT_STATUS_FAILURE;
goto Failed;
}
tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc->queue_index = TXCMD_QUEUE;
tcb_desc->bCmdOrInit = packettype;
tcb_desc->bLastIniPkt = bLastIniPkt;
tcb_desc->pkt_size = frag_length;
//seg_ptr = skb_put(skb, frag_length + priv->ieee80211->tx_headroom);
seg_ptr = skb_put(skb, priv->ieee80211->tx_headroom);
pTxFwInfo = (PTX_FWINFO_8190PCI)seg_ptr;
memset(pTxFwInfo,0,sizeof(TX_FWINFO_8190PCI));
memset(pTxFwInfo,0x12,8);
seg_ptr +=sizeof(TX_FWINFO_8190PCI);
/*
* Transform from little endian to big endian
* and pending zero
*/
seg_ptr = skb_tail_pointer(skb);
for(i=0 ; i < frag_length; i+=4) {
*seg_ptr++ = ((i+0)<frag_length)?code_virtual_address[i+3]:0;
*seg_ptr++ = ((i+1)<frag_length)?code_virtual_address[i+2]:0;
*seg_ptr++ = ((i+2)<frag_length)?code_virtual_address[i+1]:0;
*seg_ptr++ = ((i+3)<frag_length)?code_virtual_address[i+0]:0;
}
skb_put(skb, i);
priv->ieee80211->softmac_hard_start_xmit(skb, priv->ieee80211);
code_virtual_address += frag_length;
frag_offset += frag_length;
}while(frag_offset < buffer_len);
Failed:
return rt_status;
}
static void cmpk_count_txstatistic(struct r8192_priv *priv, cmpk_txfb_t *pstx_fb)
{
#ifdef ENABLE_PS
RT_RF_POWER_STATE rtState;
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
// When RF is off, we should not count the packet for hw/sw synchronize
// reason, ie. there may be a duration while sw switch is changed and hw
// switch is being changed. 2006.12.04, by shien chang.
if (rtState == eRfOff)
{
return;
}
#endif
#ifdef TODO
if(pAdapter->bInHctTest)
return;
#endif
/* We can not know the packet length and transmit type: broadcast or uni
or multicast. So the relative statistics must be collected in tx
feedback info. */
if (pstx_fb->tok)
{
priv->stats.txoktotal++;
/* We can not make sure broadcast/multicast or unicast mode. */
if (pstx_fb->pkt_type != PACKET_MULTICAST &&
pstx_fb->pkt_type != PACKET_BROADCAST) {
priv->stats.txbytesunicast += pstx_fb->pkt_length;
}
}
}
/*
* The function is responsible for extract the message inside TX
* feedbck message from firmware. It will contain dedicated info in
* ws-06-0063-rtl8190-command-packet-specification. Please
* refer to chapter "TX Feedback Element". We have to read 20 bytes
* in the command packet.
*/
static void cmpk_handle_tx_feedback(struct r8192_priv *priv, u8 *pmsg)
{
cmpk_txfb_t rx_tx_fb; /* */
priv->stats.txfeedback++;
memcpy((u8*)&rx_tx_fb, pmsg, sizeof(cmpk_txfb_t));
/* Use tx feedback info to count TX statistics. */
cmpk_count_txstatistic(priv, &rx_tx_fb);
}
/*
* The function is responsible for extract the message from
* firmware. It will contain dedicated info in
* ws-07-0063-v06-rtl819x-command-packet-specification-070315.doc.
* Please refer to chapter "Interrupt Status Element".
*/
static void cmpk_handle_interrupt_status(struct r8192_priv *priv, u8 *pmsg)
{
cmpk_intr_sta_t rx_intr_status; /* */
DMESG("---> cmpk_Handle_Interrupt_Status()\n");
/* 1. Extract TX feedback info from RFD to temp structure buffer. */
/* It seems that FW use big endian(MIPS) and DRV use little endian in
windows OS. So we have to read the content byte by byte or transfer
endian type before copy the message copy. */
//rx_bcn_state.Element_ID = pMsg[0];
//rx_bcn_state.Length = pMsg[1];
rx_intr_status.length = pmsg[1];
if (rx_intr_status.length != (sizeof(cmpk_intr_sta_t) - 2))
{
DMESG("cmpk_Handle_Interrupt_Status: wrong length!\n");
return;
}
// Statistics of beacon for ad-hoc mode.
if( priv->ieee80211->iw_mode == IW_MODE_ADHOC)
{
//2 maybe need endian transform?
rx_intr_status.interrupt_status = *((u32 *)(pmsg + 4));
//rx_intr_status.InterruptStatus = N2H4BYTE(*((UINT32 *)(pMsg + 4)));
DMESG("interrupt status = 0x%x\n", rx_intr_status.interrupt_status);
if (rx_intr_status.interrupt_status & ISR_TxBcnOk)
{
priv->ieee80211->bibsscoordinator = true;
priv->stats.txbeaconokint++;
}
else if (rx_intr_status.interrupt_status & ISR_TxBcnErr)
{
priv->ieee80211->bibsscoordinator = false;
priv->stats.txbeaconerr++;
}
}
// Other informations in interrupt status we need?
DMESG("<---- cmpk_handle_interrupt_status()\n");
}
/*
* The function is responsible for extract the message from
* firmware. It will contain dedicated info in
* ws-06-0063-rtl8190-command-packet-specification. Please
* refer to chapter "Beacon State Element".
*/
static void cmpk_handle_query_config_rx(struct r8192_priv *priv, u8 *pmsg)
{
cmpk_query_cfg_t rx_query_cfg; /* */
/* 0. Display received message. */
//cmpk_Display_Message(CMPK_RX_BEACON_STATE_SIZE, pMsg);
/* 1. Extract TX feedback info from RFD to temp structure buffer. */
/* It seems that FW use big endian(MIPS) and DRV use little endian in
windows OS. So we have to read the content byte by byte or transfer
endian type before copy the message copy. */
//rx_query_cfg.Element_ID = pMsg[0];
//rx_query_cfg.Length = pMsg[1];
rx_query_cfg.cfg_action = (pmsg[4] & 0x80000000)>>31;
rx_query_cfg.cfg_type = (pmsg[4] & 0x60) >> 5;
rx_query_cfg.cfg_size = (pmsg[4] & 0x18) >> 3;
rx_query_cfg.cfg_page = (pmsg[6] & 0x0F) >> 0;
rx_query_cfg.cfg_offset = pmsg[7];
rx_query_cfg.value = (pmsg[8] << 24) | (pmsg[9] << 16) |
(pmsg[10] << 8) | (pmsg[11] << 0);
rx_query_cfg.mask = (pmsg[12] << 24) | (pmsg[13] << 16) |
(pmsg[14] << 8) | (pmsg[15] << 0);
}
/*
* Count aggregated tx status from firmwar of one type rx command
* packet element id = RX_TX_STATUS.
*/
static void cmpk_count_tx_status(struct r8192_priv *priv, cmpk_tx_status_t *pstx_status)
{
#ifdef ENABLE_PS
RT_RF_POWER_STATE rtstate;
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
// When RF is off, we should not count the packet for hw/sw synchronize
// reason, ie. there may be a duration while sw switch is changed and hw
// switch is being changed. 2006.12.04, by shien chang.
if (rtState == eRfOff)
{
return;
}
#endif
priv->stats.txfeedbackok += pstx_status->txok;
priv->stats.txoktotal += pstx_status->txok;
priv->stats.txbytesunicast += pstx_status->txuclength;
}
/*
* Firmware add a new tx feedback status to reduce rx command
* packet buffer operation load.
*/
static void cmpk_handle_tx_status(struct r8192_priv *priv, u8 *pmsg)
{
cmpk_tx_status_t rx_tx_sts; /* */
memcpy((void*)&rx_tx_sts, (void*)pmsg, sizeof(cmpk_tx_status_t));
/* 2. Use tx feedback info to count TX statistics. */
cmpk_count_tx_status(priv, &rx_tx_sts);
}
/* Firmware add a new tx rate history */
static void cmpk_handle_tx_rate_history(struct r8192_priv *priv, u8 *pmsg)
{
u8 i;
u16 length = sizeof(cmpk_tx_rahis_t);
u32 *ptemp;
#ifdef ENABLE_PS
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
// When RF is off, we should not count the packet for hw/sw synchronize
// reason, ie. there may be a duration while sw switch is changed and hw
// switch is being changed. 2006.12.04, by shien chang.
if (rtState == eRfOff)
{
return;
}
#endif
ptemp = (u32 *)pmsg;
//
// Do endian transfer to word alignment(16 bits) for windows system.
// You must do different endian transfer for linux and MAC OS
//
for (i = 0; i < (length/4); i++)
{
u16 temp1, temp2;
temp1 = ptemp[i]&0x0000FFFF;
temp2 = ptemp[i]>>16;
ptemp[i] = (temp1<<16)|temp2;
}
}
/*
* In the function, we will capture different RX command packet
* info. Every RX command packet element has different message
* length and meaning in content. We only support three type of RX
* command packet now. Please refer to document
* ws-06-0063-rtl8190-command-packet-specification.
*/
u32 cmpk_message_handle_rx(struct r8192_priv *priv, struct ieee80211_rx_stats *pstats)
{
// u32 debug_level = DBG_LOUD;
int total_length;
u8 cmd_length, exe_cnt = 0;
u8 element_id;
u8 *pcmd_buff;
RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx()\n");
/* 0. Check inpt arguments. If is is a command queue message or pointer is
null. */
if (/*(prfd->queue_id != CMPK_RX_QUEUE_ID) || */(pstats== NULL))
{
/* Print error message. */
/*RT_TRACE(COMP_SEND, DebugLevel,
("\n\r[CMPK]-->Err queue id or pointer"));*/
return 0; /* This is not a command packet. */
}
/* 1. Read received command packet message length from RFD. */
total_length = pstats->Length;
/* 2. Read virtual address from RFD. */
pcmd_buff = pstats->virtual_address;
/* 3. Read command pakcet element id and length. */
element_id = pcmd_buff[0];
/*RT_TRACE(COMP_SEND, DebugLevel,
("\n\r[CMPK]-->element ID=%d Len=%d", element_id, total_length));*/
/* 4. Check every received command packet conent according to different
element type. Because FW may aggregate RX command packet to minimize
transmit time between DRV and FW.*/
// Add a counter to prevent to locked in the loop too long
while (total_length > 0 || exe_cnt++ >100)
{
/* 2007/01/17 MH We support aggregation of different cmd in the same packet. */
element_id = pcmd_buff[0];
switch(element_id)
{
case RX_TX_FEEDBACK:
RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():RX_TX_FEEDBACK\n");
cmpk_handle_tx_feedback(priv, pcmd_buff);
cmd_length = CMPK_RX_TX_FB_SIZE;
break;
case RX_INTERRUPT_STATUS:
RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():RX_INTERRUPT_STATUS\n");
cmpk_handle_interrupt_status(priv, pcmd_buff);
cmd_length = sizeof(cmpk_intr_sta_t);
break;
case BOTH_QUERY_CONFIG:
RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():BOTH_QUERY_CONFIG\n");
cmpk_handle_query_config_rx(priv, pcmd_buff);
cmd_length = CMPK_BOTH_QUERY_CONFIG_SIZE;
break;
case RX_TX_STATUS:
RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():RX_TX_STATUS\n");
cmpk_handle_tx_status(priv, pcmd_buff);
cmd_length = CMPK_RX_TX_STS_SIZE;
break;
case RX_TX_PER_PKT_FEEDBACK:
// You must at lease add a switch case element here,
// Otherwise, we will jump to default case.
//DbgPrint("CCX Test\r\n");
RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():RX_TX_PER_PKT_FEEDBACK\n");
cmd_length = CMPK_RX_TX_FB_SIZE;
break;
case RX_TX_RATE_HISTORY:
//DbgPrint(" rx tx rate history\r\n");
RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():RX_TX_HISTORY\n");
cmpk_handle_tx_rate_history(priv, pcmd_buff);
cmd_length = CMPK_TX_RAHIS_SIZE;
break;
default:
RT_TRACE(COMP_EVENTS, "---->cmpk_message_handle_rx():unknown CMD Element\n");
return 1; /* This is a command packet. */
}
total_length -= cmd_length;
pcmd_buff += cmd_length;
} /* while (total_length > 0) */
return 1; /* This is a command packet. */
RT_TRACE(COMP_EVENTS, "<----cmpk_message_handle_rx()\n");
}

207
drivers/staging/rtl8192e/r819xE_cmdpkt.h
View File

@ -1,207 +0,0 @@
#ifndef R819XUSB_CMDPKT_H
#define R819XUSB_CMDPKT_H
/* Different command packet have dedicated message length and definition. */
#define CMPK_RX_TX_FB_SIZE sizeof(cmpk_txfb_t) //20
#define CMPK_TX_SET_CONFIG_SIZE sizeof(cmpk_set_cfg_t) //16
#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(cmpk_set_cfg_t) //16
#define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t)//
#define CMPK_RX_DBG_MSG_SIZE sizeof(cmpk_rx_dbginfo_t)//
#define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t)
/* 2008/05/08 amy For USB constant. */
#define ISR_TxBcnOk BIT27 // Transmit Beacon OK
#define ISR_TxBcnErr BIT26 // Transmit Beacon Error
#define ISR_BcnTimerIntr BIT13 // Beacon Timer Interrupt
#if 0
/* Define packet type. */
typedef enum tag_packet_type
{
PACKET_BROADCAST,
PACKET_MULTICAST,
PACKET_UNICAST,
PACKET_TYPE_MAX
}cmpk_pkt_type_e;
#endif
/* Define element ID of command packet. */
/*------------------------------Define structure----------------------------*/
/* Define different command packet structure. */
/* 1. RX side: TX feedback packet. */
typedef struct tag_cmd_pkt_tx_feedback
{
// DWORD 0
u8 element_id; /* Command packet type. */
u8 length; /* Command packet length. */
/* 2007/07/05 MH Change tx feedback info field. */
/*------TX Feedback Info Field */
u8 TID:4; /* */
u8 fail_reason:3; /* */
u8 tok:1; /* Transmit ok. */
u8 reserve1:4; /* */
u8 pkt_type:2; /* */
u8 bandwidth:1; /* */
u8 qos_pkt:1; /* */
// DWORD 1
u8 reserve2; /* */
/*------TX Feedback Info Field */
u8 retry_cnt; /* */
u16 pkt_id; /* */
// DWORD 3
u16 seq_num; /* */
u8 s_rate; /* Start rate. */
u8 f_rate; /* Final rate. */
// DWORD 4
u8 s_rts_rate; /* */
u8 f_rts_rate; /* */
u16 pkt_length; /* */
// DWORD 5
u16 reserve3; /* */
u16 duration; /* */
}cmpk_txfb_t;
/* 2. RX side: Interrupt status packet. It includes Beacon State,
Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */
typedef struct tag_cmd_pkt_interrupt_status
{
u8 element_id; /* Command packet type. */
u8 length; /* Command packet length. */
u16 reserve;
u32 interrupt_status; /* Interrupt Status. */
}cmpk_intr_sta_t;
/* 3. TX side: Set configuration packet. */
typedef struct tag_cmd_pkt_set_configuration
{
u8 element_id; /* Command packet type. */
u8 length; /* Command packet length. */
u16 reserve1; /* */
u8 cfg_reserve1:3;
u8 cfg_size:2; /* Configuration info. */
u8 cfg_type:2; /* Configuration info. */
u8 cfg_action:1; /* Configuration info. */
u8 cfg_reserve2; /* Configuration info. */
u8 cfg_page:4; /* Configuration info. */
u8 cfg_reserve3:4; /* Configuration info. */
u8 cfg_offset; /* Configuration info. */
u32 value; /* */
u32 mask; /* */
}cmpk_set_cfg_t;
/* 4. Both side : TX/RX query configuraton packet. The query structure is the
same as set configuration. */
#define cmpk_query_cfg_t cmpk_set_cfg_t
/* 5. Multi packet feedback status. */
typedef struct tag_tx_stats_feedback // PJ quick rxcmd 09042007
{
// For endian transfer --> Driver will not the same as firmware structure.
// DW 0
u16 reserve1;
u8 length; // Command packet length
u8 element_id; // Command packet type
// DW 1
u16 txfail; // Tx Fail count
u16 txok; // Tx ok count
// DW 2
u16 txmcok; // tx multicast
u16 txretry; // Tx Retry count
// DW 3
u16 txucok; // tx unicast
u16 txbcok; // tx broadcast
// DW 4
u16 txbcfail; //
u16 txmcfail; //
// DW 5
u16 reserve2; //
u16 txucfail; //
// DW 6-8
u32 txmclength;
u32 txbclength;
u32 txuclength;
// DW 9
u16 reserve3_23;
u8 reserve3_1;
u8 rate;
}__attribute__((packed)) cmpk_tx_status_t;
/* 6. Debug feedback message. */
/* 2007/10/23 MH Define RX debug message */
typedef struct tag_rx_debug_message_feedback
{
// For endian transfer --> for driver
// DW 0
u16 reserve1;
u8 length; // Command packet length
u8 element_id; // Command packet type
// DW 1-??
// Variable debug message.
}cmpk_rx_dbginfo_t;
/* 2008/03/20 MH Define transmit rate history. For big endian format. */
typedef struct tag_tx_rate_history
{
// For endian transfer --> for driver
// DW 0
u8 element_id; // Command packet type
u8 length; // Command packet length
u16 reserved1;
// DW 1-2 CCK rate counter
u16 cck[4];
// DW 3-6
u16 ofdm[8];
// DW 7-14
//UINT16 MCS_BW0_SG0[16];
// DW 15-22
//UINT16 MCS_BW1_SG0[16];
// DW 23-30
//UINT16 MCS_BW0_SG1[16];
// DW 31-38
//UINT16 MCS_BW1_SG1[16];
// DW 7-14 BW=0 SG=0
// DW 15-22 BW=1 SG=0
// DW 23-30 BW=0 SG=1
// DW 31-38 BW=1 SG=1
u16 ht_mcs[4][16];
}__attribute__((packed)) cmpk_tx_rahis_t;
typedef enum tag_command_packet_directories
{
RX_TX_FEEDBACK = 0,
RX_INTERRUPT_STATUS = 1,
TX_SET_CONFIG = 2,
BOTH_QUERY_CONFIG = 3,
RX_TX_STATUS = 4,
RX_DBGINFO_FEEDBACK = 5,
RX_TX_PER_PKT_FEEDBACK = 6,
RX_TX_RATE_HISTORY = 7,
RX_CMD_ELE_MAX
}cmpk_element_e;
u32 cmpk_message_handle_rx(struct r8192_priv *priv, struct ieee80211_rx_stats *pstats);
#endif

351
drivers/staging/rtl8192e/r819xE_firmware.c
View File

@ -1,351 +0,0 @@
/*
* Procedure: Init boot code/firmware code/data session
*
* Description: This routine will initialize firmware. If any error occurs
* during the initialization process, the routine shall terminate
* immediately and return fail.
*/
#include "r8192E.h"
#include "r8192E_hw.h"
#include <linux/firmware.h>
/* It should be double word alignment */
#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4 * (v / 4) - 8)
enum firmware_init_step {
FW_INIT_STEP0_BOOT = 0,
FW_INIT_STEP1_MAIN = 1,
FW_INIT_STEP2_DATA = 2,
};
enum opt_rst_type {
OPT_SYSTEM_RESET = 0,
OPT_FIRMWARE_RESET = 1,
};
void firmware_init_param(struct r8192_priv *priv)
{
rt_firmware *pfirmware = priv->pFirmware;
pfirmware->cmdpacket_frag_thresold =
GET_COMMAND_PACKET_FRAG_THRESHOLD(MAX_TRANSMIT_BUFFER_SIZE);
}
/*
* segment the img and use the ptr and length to remember info on each segment
*/
static bool fw_download_code(struct r8192_priv *priv, u8 *code_virtual_address,
u32 buffer_len)
{
bool rt_status = true;
u16 frag_threshold;
u16 frag_length, frag_offset = 0;
int i;
rt_firmware *pfirmware = priv->pFirmware;
struct sk_buff *skb;
unsigned char *seg_ptr;
cb_desc *tcb_desc;
u8 bLastIniPkt;
firmware_init_param(priv);
/* Fragmentation might be required */
frag_threshold = pfirmware->cmdpacket_frag_thresold;
do {
if ((buffer_len - frag_offset) > frag_threshold) {
frag_length = frag_threshold ;
bLastIniPkt = 0;
} else {
frag_length = buffer_len - frag_offset;
bLastIniPkt = 1;
}
/*
* Allocate skb buffer to contain firmware info and tx
* descriptor info add 4 to avoid packet appending overflow.
*/
skb = dev_alloc_skb(frag_length + 4);
tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc->queue_index = TXCMD_QUEUE;
tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
tcb_desc->bLastIniPkt = bLastIniPkt;
seg_ptr = skb->data;
/*
* Transform from little endian to big endian and pending zero
*/
for (i = 0; i < frag_length; i += 4) {
*seg_ptr++ = ((i+0) < frag_length) ?
code_virtual_address[i+3] : 0;
*seg_ptr++ = ((i+1) < frag_length) ?
code_virtual_address[i+2] : 0;
*seg_ptr++ = ((i+2) < frag_length) ?
code_virtual_address[i+1] : 0;
*seg_ptr++ = ((i+3) < frag_length) ?
code_virtual_address[i+0] : 0;
}
tcb_desc->txbuf_size = (u16)i;
skb_put(skb, i);
priv->ieee80211->softmac_hard_start_xmit(skb, priv->ieee80211);
code_virtual_address += frag_length;
frag_offset += frag_length;
} while (frag_offset < buffer_len);
return rt_status;
}
/*
* Check whether main code is download OK. If OK, turn on CPU
*
* CPU register locates in different page against general
* register. Switch to CPU register in the begin and switch
* back before return
*/
static bool CPUcheck_maincodeok_turnonCPU(struct r8192_priv *priv)
{
unsigned long timeout;
bool rt_status = true;
u32 CPU_status = 0;
/* Check whether put code OK */
timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) {
CPU_status = read_nic_dword(priv, CPU_GEN);
if (CPU_status & CPU_GEN_PUT_CODE_OK)
break;
msleep(2);
}
if (!(CPU_status & CPU_GEN_PUT_CODE_OK)) {
RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!\n");
goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;
} else {
RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!\n");
}
/* Turn On CPU */
CPU_status = read_nic_dword(priv, CPU_GEN);
write_nic_byte(priv, CPU_GEN,
(u8)((CPU_status | CPU_GEN_PWR_STB_CPU) & 0xff));
mdelay(1);
/* Check whether CPU boot OK */
timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) {
CPU_status = read_nic_dword(priv, CPU_GEN);
if (CPU_status & CPU_GEN_BOOT_RDY)
break;
msleep(2);
}
if (!(CPU_status & CPU_GEN_BOOT_RDY))
goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;
else
RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!\n");
return rt_status;
CPUCheckMainCodeOKAndTurnOnCPU_Fail:
RT_TRACE(COMP_ERR, "ERR in %s()\n", __func__);
rt_status = FALSE;
return rt_status;
}
static bool CPUcheck_firmware_ready(struct r8192_priv *priv)
{
unsigned long timeout;
bool rt_status = true;
u32 CPU_status = 0;
/* Check Firmware Ready */
timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) {
CPU_status = read_nic_dword(priv, CPU_GEN);
if (CPU_status & CPU_GEN_FIRM_RDY)
break;
msleep(2);
}
if (!(CPU_status & CPU_GEN_FIRM_RDY))
goto CPUCheckFirmwareReady_Fail;
else
RT_TRACE(COMP_FIRMWARE, "Download Firmware: Firmware ready!\n");
return rt_status;
CPUCheckFirmwareReady_Fail:
RT_TRACE(COMP_ERR, "ERR in %s()\n", __func__);
rt_status = false;
return rt_status;
}
bool init_firmware(struct r8192_priv *priv)
{
bool rt_status = true;
u32 file_length = 0;
u8 *mapped_file = NULL;
u32 init_step = 0;
enum opt_rst_type rst_opt = OPT_SYSTEM_RESET;
enum firmware_init_step starting_state = FW_INIT_STEP0_BOOT;
rt_firmware *pfirmware = priv->pFirmware;
const struct firmware *fw_entry;
const char *fw_name[3] = { "RTL8192E/boot.img",
"RTL8192E/main.img",
"RTL8192E/data.img"};
int rc;
RT_TRACE(COMP_FIRMWARE, " PlatformInitFirmware()==>\n");
if (pfirmware->firmware_status == FW_STATUS_0_INIT) {
/* it is called by reset */
rst_opt = OPT_SYSTEM_RESET;
starting_state = FW_INIT_STEP0_BOOT;
/* TODO: system reset */
} else if (pfirmware->firmware_status == FW_STATUS_5_READY) {
/* it is called by Initialize */
rst_opt = OPT_FIRMWARE_RESET;
starting_state = FW_INIT_STEP2_DATA;
} else {
RT_TRACE(COMP_FIRMWARE,
"PlatformInitFirmware: undefined firmware state\n");
}
/*
* Download boot, main, and data image for System reset.
* Download data image for firmware reseta
*/
for (init_step = starting_state; init_step <= FW_INIT_STEP2_DATA;
init_step++) {
/*
* Open Image file, and map file to contineous memory if open file success.
* or read image file from array. Default load from IMG file
*/
if (rst_opt == OPT_SYSTEM_RESET) {
if (pfirmware->firmware_buf_size[init_step] == 0) {
rc = request_firmware(&fw_entry,
fw_name[init_step], &priv->pdev->dev);
if (rc < 0) {
RT_TRACE(COMP_FIRMWARE, "request firmware fail!\n");
goto download_firmware_fail;
}
if (fw_entry->size > sizeof(pfirmware->firmware_buf[init_step])) {
RT_TRACE(COMP_FIRMWARE,
"img file size exceed the container buffer fail!\n");
goto download_firmware_fail;
}
if (init_step != FW_INIT_STEP1_MAIN) {
memcpy(pfirmware->firmware_buf[init_step],
fw_entry->data, fw_entry->size);
pfirmware->firmware_buf_size[init_step] = fw_entry->size;
} else {
memset(pfirmware->firmware_buf[init_step], 0, 128);
memcpy(&pfirmware->firmware_buf[init_step][128], fw_entry->data,
fw_entry->size);
pfirmware->firmware_buf_size[init_step] = fw_entry->size+128;
}
if (rst_opt == OPT_SYSTEM_RESET)
release_firmware(fw_entry);
}
mapped_file = pfirmware->firmware_buf[init_step];
file_length = pfirmware->firmware_buf_size[init_step];
} else if (rst_opt == OPT_FIRMWARE_RESET) {
/* we only need to download data.img here */
mapped_file = pfirmware->firmware_buf[init_step];
file_length = pfirmware->firmware_buf_size[init_step];
}
/* Download image file */
/* The firmware download process is just as following,
* 1. that is each packet will be segmented and inserted to the
* wait queue.
* 2. each packet segment will be put in the skb_buff packet.
* 3. each skb_buff packet data content will already include
* the firmware info and Tx descriptor info
*/
rt_status = fw_download_code(priv, mapped_file, file_length);
if (rt_status != TRUE)
goto download_firmware_fail;
switch (init_step) {
case FW_INIT_STEP0_BOOT:
/* Download boot
* initialize command descriptor.
* will set polling bit when firmware code is also
* configured
*/
pfirmware->firmware_status = FW_STATUS_1_MOVE_BOOT_CODE;
/* mdelay(1000); */
/*
* To initialize IMEM, CPU move code from 0x80000080,
* hence, we send 0x80 byte packet
*/
break;
case FW_INIT_STEP1_MAIN:
/* Download firmware code.
* Wait until Boot Ready and Turn on CPU */
pfirmware->firmware_status = FW_STATUS_2_MOVE_MAIN_CODE;
/* Check Put Code OK and Turn On CPU */
rt_status = CPUcheck_maincodeok_turnonCPU(priv);
if (rt_status != TRUE) {
RT_TRACE(COMP_FIRMWARE,
"CPUcheck_maincodeok_turnonCPU fail!\n");
goto download_firmware_fail;
}
pfirmware->firmware_status = FW_STATUS_3_TURNON_CPU;
break;
case FW_INIT_STEP2_DATA:
/* download initial data code */
pfirmware->firmware_status = FW_STATUS_4_MOVE_DATA_CODE;
mdelay(1);
rt_status = CPUcheck_firmware_ready(priv);
if (rt_status != TRUE) {
RT_TRACE(COMP_FIRMWARE,
"CPUcheck_firmware_ready fail(%d)!\n",
rt_status);
goto download_firmware_fail;
}
/* wait until data code is initialized ready.*/
pfirmware->firmware_status = FW_STATUS_5_READY;
break;
}
}
RT_TRACE(COMP_FIRMWARE, "Firmware Download Success\n");
return rt_status;
download_firmware_fail:
RT_TRACE(COMP_ERR, "ERR in %s() step %d\n", __func__, init_step);
rt_status = false;
return rt_status;
}
MODULE_FIRMWARE("RTL8192E/boot.img");
MODULE_FIRMWARE("RTL8192E/main.img");
MODULE_FIRMWARE("RTL8192E/data.img");

2225
drivers/staging/rtl8192e/r819xE_phy.c
View File

File diff suppressed because it is too large Load Diff

131
drivers/staging/rtl8192e/r819xE_phy.h
View File

@ -1,131 +0,0 @@
#ifndef _R819XU_PHY_H
#define _R819XU_PHY_H
/* Channel switch: the size of command tables for switch channel */
#define MAX_PRECMD_CNT 16
#define MAX_RFDEPENDCMD_CNT 16
#define MAX_POSTCMD_CNT 16
#define MACPHY_Array_PGLength 30
#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
#define RadioC_ArrayLength 1
#define RadioD_ArrayLength 1
#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
#define PHY_REGArrayLength 1
#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
#define PHY_REG_1T2RArrayLength 296
#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
#define AGCTAB_ArrayLength 384
#define MACPHY_ArrayLength 18
#define RadioA_ArrayLength 246
#define RadioB_ArrayLength 78
typedef enum _SwChnlCmdID {
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
CmdID_WritePortUlong,
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
} SwChnlCmdID;
/* switch channel data structure */
typedef struct _SwChnlCmd {
SwChnlCmdID CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
} __attribute__ ((packed)) SwChnlCmd;
extern u32 rtl819XMACPHY_Array_PG[];
extern u32 rtl819XPHY_REG_1T2RArray[];
extern u32 rtl819XAGCTAB_Array[];
extern u32 rtl819XRadioA_Array[];
extern u32 rtl819XRadioB_Array[];
extern u32 rtl819XRadioC_Array[];
extern u32 rtl819XRadioD_Array[];
typedef enum _HW90_BLOCK {
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
/* Don't ever use this. */
HW90_BLOCK_MAXIMUM = 4,
} HW90_BLOCK_E, *PHW90_BLOCK_E;
typedef enum _RF90_RADIO_PATH {
/* Radio paths */
RF90_PATH_A = 0,
RF90_PATH_B = 1,
RF90_PATH_C = 2,
RF90_PATH_D = 3,
/* Max RF number 92 support */
RF90_PATH_MAX
} RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
#define bMaskByte0 0xff
#define bMaskByte1 0xff00
#define bMaskByte2 0xff0000
#define bMaskByte3 0xff000000
#define bMaskHWord 0xffff0000
#define bMaskLWord 0x0000ffff
#define bMaskDWord 0xffffffff
u8 rtl8192_phy_CheckIsLegalRFPath(struct r8192_priv *priv, u32 eRFPath);
void rtl8192_setBBreg(struct r8192_priv *priv, u32 dwRegAddr,
u32 dwBitMask, u32 dwData);
u32 rtl8192_QueryBBReg(struct r8192_priv *priv, u32 dwRegAddr,
u32 dwBitMask);
void rtl8192_phy_SetRFReg(struct r8192_priv *priv,
RF90_RADIO_PATH_E eRFPath, u32 RegAddr,
u32 BitMask, u32 Data);
u32 rtl8192_phy_QueryRFReg(struct r8192_priv *priv,
RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
void rtl8192_phy_configmac(struct r8192_priv *priv);
void rtl8192_phyConfigBB(struct r8192_priv *priv, u8 ConfigType);
RT_STATUS rtl8192_phy_checkBBAndRF(struct r8192_priv *priv,
HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
RT_STATUS rtl8192_BBConfig(struct r8192_priv *priv);
void rtl8192_phy_getTxPower(struct r8192_priv *priv);
void rtl8192_phy_setTxPower(struct r8192_priv *priv, u8 channel);
RT_STATUS rtl8192_phy_RFConfig(struct r8192_priv *priv);
void rtl8192_phy_updateInitGain(struct r8192_priv *priv);
u8 rtl8192_phy_ConfigRFWithHeaderFile(struct r8192_priv *priv,
RF90_RADIO_PATH_E eRFPath);
u8 rtl8192_phy_SwChnl(struct ieee80211_device *ieee80211, u8 channel);
void rtl8192_SetBWMode(struct ieee80211_device *ieee80211,
HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
void rtl8192_SwChnl_WorkItem(struct r8192_priv *priv);
void rtl8192_SetBWModeWorkItem(struct r8192_priv *priv);
void InitialGain819xPci(struct ieee80211_device *ieee, u8 Operation);
#endif /* _R819XU_PHY_H */

160
drivers/staging/rtl8192e/readme
View File

@ -1,160 +0,0 @@
What this layer should do
- It mantain the old mechanism as alternative, so the
ipw2100 driver works with really few changes.
- Encapsulate / Decapsulate rtllib packet
- Handle fragmentation
- Optionally provide an alterantive mechanism for netif queue stop/wake,
so that the rtllib layer will pass one fragment per time instead of
one txb struct per time. so the driver can stop the queue in the middle
of a packet.
- Provide two different TX interfaces for cards that can handle management
frames on one HW queue, and data on another, and for cards that have only
one HW queue (the latter untested and very, very rough).
- Optionally provide the logic for handling IBSS/MASTER/MONITOR/BSS modes
and for the channel, essid and wap get/set wireless extension requests.
so that the driver has only to change channel when the ieee stack tell it.
- Optionally provide a scanning mechanism so that the driver has not to
worry about this, just implement the set channel calback and pass
frames to the upper layer
- Optionally provide the bss client protocol handshaking (just with open
authentication)
- Optionally provide the probe request send mechanism
- Optionally provide the bss master mode logic to handle association
protocol (only open authentication) and probe responses.
- SW wep encryption (with open authentication)
- It collects some stats
- It provides beacons to the card when it ask for them
What this layer doesn't do (yet)
- Perform shared authentication
- Have full support for master mode (the AP should loop back in the air
frames from an associated client to another. This could be done easily
with few lines of code, and it is done in my previous version of the
stach, but a table of association must be keept and a disassociation
policy must be decided and implemented.
- Handle cleanly the full ieee 802.11 protocol. In AP mode it never
disassociate clients, and it is really prone to always allow access.
In bss client mode it is a bit rough with AP deauth and disassoc requests.
- It has not any entry point to view the collected stats.
- Altought it takes care of the card supported rates in the management frame
it sends, support for rate changing on TXed packet is not complete.
- Give up once associated in bss client mode (it never detect a
signal loss condition to disassociate and restart scanning)
- Provide a mechanism for enabling the TX in monitor mode, so
userspace programs can TX raw packets.
- Provide a mechanism for cards that need that the SW take care of beacon
TX completely, in sense that the SW has to enqueue by itself beacons
to the card so it TX them (if any...)
APIs
Callback functions in the original stack has been mantained.
following has been added (from rtllib.h)
/* Softmac-generated frames (mamagement) are TXed via this
* callback if the flag IEEE_SOFTMAC_SINGLE_QUEUE is
* not set. As some cards may have different HW queues that
* one might want to use for data and management frames
* the option to have two callbacks might be useful.
* This fucntion can't sleep.
*/
int (*softmac_hard_start_xmit)(struct sk_buff *skb,
struct net_device *dev);
/* used instead of hard_start_xmit (not softmac_hard_start_xmit)
* if the IEEE_SOFTMAC_TX_QUEUE feature is used to TX data
* frames. I the option IEEE_SOFTMAC_SINGLE_QUEUE is also set
* then also management frames are sent via this callback.
* This function can't sleep.
*/
void (*softmac_data_hard_start_xmit)(struct sk_buff *skb,
struct net_device *dev);
/* stops the HW queue for DATA frames. Useful to avoid
* waste time to TX data frame when we are reassociating
* This function can sleep.
*/
void (*data_hard_stop)(struct net_device *dev);
/* OK this is complementar to data_poll_hard_stop */
void (*data_hard_resume)(struct net_device *dev);
/* ask to the driver to retune the radio .
* This function can sleep. the driver should ensure
* the radio has been swithced before return.
*/
void (*set_chan)(struct net_device *dev,short ch);
/* These are not used if the ieee stack takes care of
* scanning (IEEE_SOFTMAC_SCAN feature set).
* In this case only the set_chan is used.
*
* The syncro version is similar to the start_scan but
* does not return until all channels has been scanned.
* this is called in user context and should sleep,
* it is called in a work_queue when swithcing to ad-hoc mode
* or in behalf of iwlist scan when the card is associated
* and root user ask for a scan.
* the fucntion stop_scan should stop both the syncro and
* background scanning and can sleep.
* The fucntion start_scan should initiate the background
* scanning and can't sleep.
*/
void (*scan_syncro)(struct net_device *dev);
void (*start_scan)(struct net_device *dev);
void (*stop_scan)(struct net_device *dev);
/* indicate the driver that the link state is changed
* for example it may indicate the card is associated now.
* Driver might be interested in this to apply RX filter
* rules or simply light the LINK led
*/
void (*link_change)(struct net_device *dev);
Functions hard_data_[resume/stop] are optional and should not be used
if the driver decides to uses data+management frames enqueue in a
single HQ queue (thus using just the softmac_hard_data_start_xmit
callback).
Function that the driver can use are:
rtllib_get_beacon - this is called by the driver when
the HW needs a beacon.
rtllib_softmac_start_protocol - this should normally be called in the
driver open function
rtllib_softmac_stop_protocol - the opposite of the above
rtllib_wake_queue - this is similar to netif_wake_queue
rtllib_reset_queue - this throw away fragments pending(if any)
rtllib_stop_queue - this is similar to netif_stop_queue
known BUGS:
- When performing syncro scan (possiblily when swithcing to ad-hoc mode
and when running iwlist scan when associated) there is still an odd
behaviour.. I have not looked in this more accurately (yet).
locking:
locking is done by means of three structures.
1- ieee->lock (by means of spin_[un]lock_irq[save/restore]
2- ieee->wx_sem
3- ieee->scan_sem
the lock 1 is what protect most of the critical sections in the ieee stack.
the lock 2 is used to avoid that more than one of the SET wireless extension
handlers (as well as start/stop protocol function) are running at the same time.
the lock 1 is used when we need to modify or read the shared data in the wx handlers.
In other words the lock 2 will prevent one SET action will run across another SET
action (by make sleep the 2nd one) but allow GET actions, while the lock 1
make atomic those little shared data access in both GET and SET operation.
So get operation will be never be delayed really: they will never sleep..
Furthermore in the top of some SET operations a flag is set before acquiring
the lock. This is an help to make the previous running SET operation to
finish faster if needed (just in case the second one will totally undo the
first, so there is not need to complete the 1st really.. ).
The background scanning mechaninsm is protected by the lock 1 except for the
workqueue. this wq is here just to let the set_chan callback sleep (I thinked it
might be appreciated by USB network card driver developer). In this case the lock 3
take its turn.
Thus the stop function needs both the locks.
Funny in the syncro scan the lock 2 play its role (as both the syncro_scan
function and the stop scan function are called with this semaphore held).