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ASoC: omap-mcbsp: Configure wakeup in later phase 

Configure the WAKEUPEN register at the same time we configure the rest of
the McBSP registers.
In case of OMAP3+, if the sysclock has been reconfigured we are going to
disable McBSP for the duration of the clock change, which will reset the
McBSP registers. The WAKEUPEN register need to be configured later, so
the changes will be effective during runtime.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicrocom>
Signed-off-by: Liam Girdwood <lrg@ti.com>
This commit is contained in:
Peter Ujfalusi 2012-03-05 11:27:40 +02:00 committed by Liam Girdwood
parent 58db1dcde0
commit 08905d8ab4
1 changed files with 3 additions and 4 deletions
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7
sound/soc/omap/mcbsp.c
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@ -173,6 +173,9 @@ void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
MCBSP_WRITE(mcbsp, XCCR, config->xccr);
MCBSP_WRITE(mcbsp, RCCR, config->rccr);
}
/* Enable wakeup behavior */
if (mcbsp->pdata->has_wakeup)
MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
}
/**
@ -479,10 +482,6 @@ int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
mcbsp->pdata->ops->request(mcbsp->id - 1);
/* Enable wakeup behavior */
if (mcbsp->pdata->has_wakeup)
MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
/*
* Make sure that transmitter, receiver and sample-rate generator are
* not running before activating IRQs.