[PATCH] x86-64: Add __copy_from_user_nocache
This does user copies in fs write() into the page cache with write combining. This pushes the destination out of the CPU's cache, but allows higher bandwidth in some case. The theory is that the page cache data is usually not touched by the CPU again and it's better to not pollute the cache with it. Also it is a little faster. Signed-off-by: Andi Kleen <ak@suse.de>
This commit is contained in:
Andi Kleen
Andi Kleen
parent
ee55c0be30
commit
0812a579c9
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@ -26,6 +26,7 @@ EXPORT_SYMBOL(__put_user_4);
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EXPORT_SYMBOL(__put_user_8);
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EXPORT_SYMBOL(copy_user_generic);
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EXPORT_SYMBOL(__copy_user_nocache);
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EXPORT_SYMBOL(copy_from_user);
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EXPORT_SYMBOL(copy_to_user);
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EXPORT_SYMBOL(__copy_from_user_inatomic);
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@ -9,4 +9,4 @@ obj-y := io.o iomap_copy.o
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lib-y := csum-partial.o csum-copy.o csum-wrappers.o delay.o \
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usercopy.o getuser.o putuser.o \
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thunk.o clear_page.o copy_page.o bitstr.o bitops.o
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lib-y += memcpy.o memmove.o memset.o copy_user.o rwlock.o
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lib-y += memcpy.o memmove.o memset.o copy_user.o rwlock.o copy_user_nocache.o
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@ -0,0 +1,217 @@
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/* Copyright 2002 Andi Kleen, SuSE Labs.
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* Subject to the GNU Public License v2.
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*
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* Functions to copy from and to user space.
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*/
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#include <linux/linkage.h>
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#include <asm/dwarf2.h>
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#define FIX_ALIGNMENT 1
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#include <asm/current.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/cpufeature.h>
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/*
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* copy_user_nocache - Uncached memory copy with exception handling
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* This will force destination/source out of cache for more performance.
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*
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* Input:
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* rdi destination
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* rsi source
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* rdx count
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* rcx zero flag when 1 zero on exception
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*
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* Output:
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* eax uncopied bytes or 0 if successful.
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*/
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ENTRY(__copy_user_nocache)
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CFI_STARTPROC
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pushq %rbx
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CFI_ADJUST_CFA_OFFSET 8
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CFI_REL_OFFSET rbx, 0
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pushq %rcx /* save zero flag */
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CFI_ADJUST_CFA_OFFSET 8
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CFI_REL_OFFSET rcx, 0
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xorl %eax,%eax /* zero for the exception handler */
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#ifdef FIX_ALIGNMENT
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/* check for bad alignment of destination */
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movl %edi,%ecx
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andl $7,%ecx
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jnz .Lbad_alignment
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.Lafter_bad_alignment:
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#endif
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movq %rdx,%rcx
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movl $64,%ebx
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shrq $6,%rdx
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decq %rdx
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js .Lhandle_tail
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.p2align 4
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.Lloop:
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.Ls1: movq (%rsi),%r11
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.Ls2: movq 1*8(%rsi),%r8
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.Ls3: movq 2*8(%rsi),%r9
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.Ls4: movq 3*8(%rsi),%r10
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.Ld1: movnti %r11,(%rdi)
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.Ld2: movnti %r8,1*8(%rdi)
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.Ld3: movnti %r9,2*8(%rdi)
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.Ld4: movnti %r10,3*8(%rdi)
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.Ls5: movq 4*8(%rsi),%r11
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.Ls6: movq 5*8(%rsi),%r8
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.Ls7: movq 6*8(%rsi),%r9
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.Ls8: movq 7*8(%rsi),%r10
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.Ld5: movnti %r11,4*8(%rdi)
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.Ld6: movnti %r8,5*8(%rdi)
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.Ld7: movnti %r9,6*8(%rdi)
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.Ld8: movnti %r10,7*8(%rdi)
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dec %rdx
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leaq 64(%rsi),%rsi
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leaq 64(%rdi),%rdi
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jns .Lloop
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.p2align 4
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.Lhandle_tail:
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movl %ecx,%edx
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andl $63,%ecx
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shrl $3,%ecx
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jz .Lhandle_7
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movl $8,%ebx
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.p2align 4
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.Lloop_8:
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.Ls9: movq (%rsi),%r8
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.Ld9: movnti %r8,(%rdi)
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decl %ecx
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leaq 8(%rdi),%rdi
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leaq 8(%rsi),%rsi
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jnz .Lloop_8
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.Lhandle_7:
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movl %edx,%ecx
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andl $7,%ecx
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jz .Lende
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.p2align 4
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.Lloop_1:
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.Ls10: movb (%rsi),%bl
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.Ld10: movb %bl,(%rdi)
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incq %rdi
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incq %rsi
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decl %ecx
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jnz .Lloop_1
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CFI_REMEMBER_STATE
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.Lende:
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popq %rcx
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CFI_ADJUST_CFA_OFFSET -8
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CFI_RESTORE %rcx
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popq %rbx
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CFI_ADJUST_CFA_OFFSET -8
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CFI_RESTORE rbx
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ret
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CFI_RESTORE_STATE
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#ifdef FIX_ALIGNMENT
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/* align destination */
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.p2align 4
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.Lbad_alignment:
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movl $8,%r9d
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subl %ecx,%r9d
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movl %r9d,%ecx
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cmpq %r9,%rdx
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jz .Lhandle_7
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js .Lhandle_7
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.Lalign_1:
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.Ls11: movb (%rsi),%bl
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.Ld11: movb %bl,(%rdi)
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incq %rsi
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incq %rdi
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decl %ecx
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jnz .Lalign_1
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subq %r9,%rdx
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jmp .Lafter_bad_alignment
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#endif
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/* table sorted by exception address */
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.section __ex_table,"a"
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.align 8
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.quad .Ls1,.Ls1e
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.quad .Ls2,.Ls2e
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.quad .Ls3,.Ls3e
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.quad .Ls4,.Ls4e
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.quad .Ld1,.Ls1e
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.quad .Ld2,.Ls2e
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.quad .Ld3,.Ls3e
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.quad .Ld4,.Ls4e
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.quad .Ls5,.Ls5e
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.quad .Ls6,.Ls6e
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.quad .Ls7,.Ls7e
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.quad .Ls8,.Ls8e
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.quad .Ld5,.Ls5e
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.quad .Ld6,.Ls6e
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.quad .Ld7,.Ls7e
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.quad .Ld8,.Ls8e
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.quad .Ls9,.Le_quad
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.quad .Ld9,.Le_quad
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.quad .Ls10,.Le_byte
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.quad .Ld10,.Le_byte
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#ifdef FIX_ALIGNMENT
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.quad .Ls11,.Lzero_rest
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.quad .Ld11,.Lzero_rest
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#endif
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.quad .Le5,.Le_zero
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.previous
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/* compute 64-offset for main loop. 8 bytes accuracy with error on the
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pessimistic side. this is gross. it would be better to fix the
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interface. */
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/* eax: zero, ebx: 64 */
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.Ls1e: addl $8,%eax
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.Ls2e: addl $8,%eax
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.Ls3e: addl $8,%eax
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.Ls4e: addl $8,%eax
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.Ls5e: addl $8,%eax
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.Ls6e: addl $8,%eax
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.Ls7e: addl $8,%eax
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.Ls8e: addl $8,%eax
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addq %rbx,%rdi /* +64 */
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subq %rax,%rdi /* correct destination with computed offset */
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shlq $6,%rdx /* loop counter * 64 (stride length) */
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addq %rax,%rdx /* add offset to loopcnt */
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andl $63,%ecx /* remaining bytes */
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addq %rcx,%rdx /* add them */
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jmp .Lzero_rest
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/* exception on quad word loop in tail handling */
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/* ecx: loopcnt/8, %edx: length, rdi: correct */
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.Le_quad:
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shll $3,%ecx
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andl $7,%edx
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addl %ecx,%edx
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/* edx: bytes to zero, rdi: dest, eax:zero */
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.Lzero_rest:
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cmpl $0,(%rsp) /* zero flag set? */
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jz .Le_zero
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movq %rdx,%rcx
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.Le_byte:
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xorl %eax,%eax
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.Le5: rep
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stosb
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/* when there is another exception while zeroing the rest just return */
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.Le_zero:
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movq %rdx,%rax
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jmp .Lende
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CFI_ENDPROC
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ENDPROC(__copy_user_nocache)
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@ -367,4 +367,18 @@ __copy_to_user_inatomic(void __user *dst, const void *src, unsigned size)
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return copy_user_generic((__force void *)dst, src, size);
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}
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#define ARCH_HAS_NOCACHE_UACCESS 1
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extern long __copy_user_nocache(void *dst, const void __user *src, unsigned size, int zerorest);
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static inline int __copy_from_user_nocache(void *dst, const void __user *src, unsigned size)
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{
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might_sleep();
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return __copy_user_nocache(dst, (__force void *)src, size, 1);
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}
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static inline int __copy_from_user_inatomic_nocache(void *dst, const void __user *src, unsigned size)
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{
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return __copy_user_nocache(dst, (__force void *)src, size, 0);
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}
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#endif /* __X86_64_UACCESS_H */
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