ARM: mach-shmobile: sh7372 generic suspend/resume support
Convert the sh7372 Core Standby code to make use of the new generic ARM cpu suspend/resume code. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This commit is contained in:
Magnus Damm
Rafael J. Wysocki
parent
0aa2a22169
commit
06b841666a
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@ -35,8 +35,7 @@ extern void sh7372_add_standard_devices(void);
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extern void sh7372_clock_init(void);
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extern void sh7372_pinmux_init(void);
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extern void sh7372_pm_init(void);
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extern void sh7372_cpu_suspend(void);
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extern void sh7372_cpu_resume(void);
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extern void sh7372_resume_core_standby(void);
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extern struct clk sh7372_extal1_clk;
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extern struct clk sh7372_extal2_clk;
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@ -21,6 +21,7 @@
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/tlbflush.h>
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#include <asm/suspend.h>
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#include <mach/common.h>
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#include <mach/sh7372.h>
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@ -152,30 +153,25 @@ struct sh7372_pm_domain sh7372_a3sg = {
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#endif /* CONFIG_PM */
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static int sh7372_do_idle_core_standby(unsigned long unused)
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{
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cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
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return 0;
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}
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static void sh7372_enter_core_standby(void)
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{
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void __iomem *smfram = (void __iomem *)SMFRAM;
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/* set reset vector, translate 4k */
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__raw_writel(__pa(sh7372_resume_core_standby), SBAR);
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__raw_writel(0, APARMBAREA);
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__raw_writel(0, APARMBAREA); /* translate 4k */
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__raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
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__raw_writel(0x10, SYSTBCR); /* enable core standby */
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/* enter sleep mode with SYSTBCR to 0x10 */
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__raw_writel(0x10, SYSTBCR);
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cpu_suspend(0, sh7372_do_idle_core_standby);
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__raw_writel(0, SYSTBCR);
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__raw_writel(0, smfram + 0x3c); /* clear page table address */
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sh7372_cpu_suspend();
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cpu_init();
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/* if page table address is non-NULL then we have been powered down */
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if (__raw_readl(smfram + 0x3c)) {
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__raw_writel(__raw_readl(smfram + 0x40),
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__va(__raw_readl(smfram + 0x3c)));
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flush_tlb_all();
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set_cr(__raw_readl(smfram + 0x38));
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}
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__raw_writel(0, SYSTBCR); /* disable core standby */
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__raw_writel(0, SBAR); /* disable reset vector translation */
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/* disable reset vector translation */
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__raw_writel(0, SBAR);
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}
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#ifdef CONFIG_CPU_IDLE
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@ -30,231 +30,13 @@
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/memory.h>
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#include <asm/assembler.h>
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#define SMFRAM 0xe6a70000
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.align
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kernel_flush:
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.word v7_flush_dcache_all
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.align 3
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ENTRY(sh7372_cpu_suspend)
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stmfd sp!, {r0-r12, lr} @ save registers on stack
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ldr r8, =SMFRAM
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mov r4, sp @ Store sp
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mrs r5, spsr @ Store spsr
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mov r6, lr @ Store lr
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stmia r8!, {r4-r6}
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mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
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mrc p15, 0, r5, c2, c0, 0 @ TTBR0
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mrc p15, 0, r6, c2, c0, 1 @ TTBR1
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mrc p15, 0, r7, c2, c0, 2 @ TTBCR
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stmia r8!, {r4-r7}
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mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
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mrc p15, 0, r5, c10, c2, 0 @ PRRR
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mrc p15, 0, r6, c10, c2, 1 @ NMRR
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stmia r8!,{r4-r6}
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mrc p15, 0, r4, c13, c0, 1 @ Context ID
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mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
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mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
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mrs r7, cpsr @ Store current cpsr
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stmia r8!, {r4-r7}
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mrc p15, 0, r4, c1, c0, 0 @ save control register
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stmia r8!, {r4}
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/*
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* jump out to kernel flush routine
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* - reuse that code is better
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* - it executes in a cached space so is faster than refetch per-block
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* - should be faster and will change with kernel
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* - 'might' have to copy address, load and jump to it
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* Flush all data from the L1 data cache before disabling
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* SCTLR.C bit.
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*/
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ldr r1, kernel_flush
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mov lr, pc
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bx r1
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/*
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* Clear the SCTLR.C bit to prevent further data cache
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* allocation. Clearing SCTLR.C would make all the data accesses
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* strongly ordered and would not hit the cache.
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #(1 << 2) @ Disable the C bit
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mcr p15, 0, r0, c1, c0, 0
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isb
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/*
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* Invalidate L1 data cache. Even though only invalidate is
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* necessary exported flush API is used here. Doing clean
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* on already clean cache would be almost NOP.
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*/
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ldr r1, kernel_flush
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blx r1
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/*
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* The kernel doesn't interwork: v7_flush_dcache_all in particluar will
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* always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
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* This sequence switches back to ARM. Note that .align may insert a
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* nop: bx pc needs to be word-aligned in order to work.
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*/
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THUMB( .thumb )
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THUMB( .align )
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THUMB( bx pc )
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THUMB( nop )
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.arm
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/* Data memory barrier and Data sync barrier */
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dsb
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dmb
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/*
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* ===================================
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* == WFI instruction => Enter idle ==
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* ===================================
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*/
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wfi @ wait for interrupt
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/*
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* ===================================
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* == Resume path for non-OFF modes ==
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* ===================================
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*/
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mrc p15, 0, r0, c1, c0, 0
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tst r0, #(1 << 2) @ Check C bit enabled?
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orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
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mcreq p15, 0, r0, c1, c0, 0
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isb
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/*
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* ===================================
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* == Exit point from non-OFF modes ==
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* ===================================
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*/
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ldmfd sp!, {r0-r12, pc} @ restore regs and return
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.pool
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.align 12
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.text
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.global sh7372_cpu_resume
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sh7372_cpu_resume:
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mov r1, #0
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/*
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* Invalidate all instruction caches to PoU
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* and flush branch target cache
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*/
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mcr p15, 0, r1, c7, c5, 0
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ldr r3, =SMFRAM
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ldmia r3!, {r4-r6}
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mov sp, r4 @ Restore sp
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msr spsr_cxsf, r5 @ Restore spsr
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mov lr, r6 @ Restore lr
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ldmia r3!, {r4-r7}
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mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
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mcr p15, 0, r5, c2, c0, 0 @ TTBR0
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mcr p15, 0, r6, c2, c0, 1 @ TTBR1
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mcr p15, 0, r7, c2, c0, 2 @ TTBCR
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ldmia r3!,{r4-r6}
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mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
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mcr p15, 0, r5, c10, c2, 0 @ PRRR
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mcr p15, 0, r6, c10, c2, 1 @ NMRR
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ldmia r3!,{r4-r7}
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mcr p15, 0, r4, c13, c0, 1 @ Context ID
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mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
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mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
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msr cpsr, r7 @ store cpsr
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/* Starting to enable MMU here */
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mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
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/* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
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and r7, #0x7
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cmp r7, #0x0
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beq usettbr0
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ttbr_error:
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/*
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* More work needs to be done to support N[0:2] value other than 0
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* So looping here so that the error can be detected
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*/
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b ttbr_error
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.align
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cache_pred_disable_mask:
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.word 0xFFFFE7FB
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ttbrbit_mask:
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.word 0xFFFFC000
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table_index_mask:
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.word 0xFFF00000
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table_entry:
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.word 0x00000C02
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usettbr0:
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mrc p15, 0, r2, c2, c0, 0
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ldr r5, ttbrbit_mask
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and r2, r5
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mov r4, pc
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ldr r5, table_index_mask
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and r4, r5 @ r4 = 31 to 20 bits of pc
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/* Extract the value to be written to table entry */
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ldr r6, table_entry
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/* r6 has the value to be written to table entry */
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add r6, r6, r4
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/* Getting the address of table entry to modify */
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lsr r4, #18
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/* r2 has the location which needs to be modified */
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add r2, r4
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ldr r4, [r2]
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str r6, [r2] /* modify the table entry */
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mov r7, r6
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mov r5, r2
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mov r6, r4
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/* r5 = original page table address */
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/* r6 = original page table data */
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
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mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
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mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
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mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
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/*
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* Restore control register. This enables the MMU.
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* The caches and prediction are not enabled here, they
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* will be enabled after restoring the MMU table entry.
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*/
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ldmia r3!, {r4}
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stmia r3!, {r5} /* save original page table address */
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stmia r3!, {r6} /* save original page table data */
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stmia r3!, {r7} /* save modified page table data */
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ldr r2, cache_pred_disable_mask
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and r4, r2
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mcr p15, 0, r4, c1, c0, 0
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dsb
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isb
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ldr r0, =restoremmu_on
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bx r0
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/*
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* ==============================
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* == Exit point from OFF mode ==
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* ==============================
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*/
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restoremmu_on:
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ldmfd sp!, {r0-r12, pc} @ restore regs and return
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.global sh7372_resume_core_standby
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sh7372_resume_core_standby:
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ldr pc, 1f
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1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
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