USB: EHCI: ASPM quirk of ISOC on AMD SB800
When ASPM PM Feature is enabled on UMI link, devices that use ISOC stream of data transfer may be exposed to longer latency causing less than optimal per- formance of the device. The longer latencies are normal and are due to link wake time coming out of low power state which happens frequently to save power when the link is not active. The following code will make exception for certain features of ASPM to be by passed and keep the logic normal state only when the ISOC device is connected and active. This change will allow the device to run at optimal performance yet minimize the impact on overall power savings. Signed-off-by: Alex He <alex.he@amd.com> Acked-by: David Brownell <dbrownell@users.sourceforge.net> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alex He
Greg Kroah-Hartman
parent
66921edd7d
commit
05570297ec
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@ -114,6 +114,9 @@ MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n");
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#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
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/* for ASPM quirk of ISOC on AMD SB800 */
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static struct pci_dev *amd_nb_dev;
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/*-------------------------------------------------------------------------*/
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#include "ehci.h"
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@ -529,6 +532,11 @@ static void ehci_stop (struct usb_hcd *hcd)
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spin_unlock_irq (&ehci->lock);
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ehci_mem_cleanup (ehci);
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if (amd_nb_dev) {
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pci_dev_put(amd_nb_dev);
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amd_nb_dev = NULL;
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}
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#ifdef EHCI_STATS
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ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
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ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
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@ -44,6 +44,35 @@ static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
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return 0;
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}
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static int ehci_quirk_amd_SB800(struct ehci_hcd *ehci)
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{
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struct pci_dev *amd_smbus_dev;
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u8 rev = 0;
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amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
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if (!amd_smbus_dev)
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return 0;
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pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
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if (rev < 0x40) {
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pci_dev_put(amd_smbus_dev);
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amd_smbus_dev = NULL;
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return 0;
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}
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if (!amd_nb_dev)
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amd_nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
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if (!amd_nb_dev)
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ehci_err(ehci, "QUIRK: unable to get AMD NB device\n");
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ehci_info(ehci, "QUIRK: Enable AMD SB800 L1 fix\n");
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pci_dev_put(amd_smbus_dev);
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amd_smbus_dev = NULL;
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return 1;
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}
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/* called during probe() after chip reset completes */
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static int ehci_pci_setup(struct usb_hcd *hcd)
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{
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@ -102,6 +131,9 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
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/* cache this readonly data; minimize chip reads */
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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if (ehci_quirk_amd_SB800(ehci))
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ehci->amd_l1_fix = 1;
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retval = ehci_halt(ehci);
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if (retval)
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return retval;
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@ -1583,6 +1583,63 @@ itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
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*hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
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}
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#define AB_REG_BAR_LOW 0xe0
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#define AB_REG_BAR_HIGH 0xe1
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#define AB_INDX(addr) ((addr) + 0x00)
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#define AB_DATA(addr) ((addr) + 0x04)
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#define NB_PCIE_INDX_ADDR 0xe0
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#define NB_PCIE_INDX_DATA 0xe4
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#define NB_PIF0_PWRDOWN_0 0x01100012
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#define NB_PIF0_PWRDOWN_1 0x01100013
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static void ehci_quirk_amd_L1(struct ehci_hcd *ehci, int disable)
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{
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u32 addr, addr_low, addr_high, val;
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outb_p(AB_REG_BAR_LOW, 0xcd6);
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addr_low = inb_p(0xcd7);
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outb_p(AB_REG_BAR_HIGH, 0xcd6);
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addr_high = inb_p(0xcd7);
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addr = addr_high << 8 | addr_low;
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outl_p(0x30, AB_INDX(addr));
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outl_p(0x40, AB_DATA(addr));
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outl_p(0x34, AB_INDX(addr));
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val = inl_p(AB_DATA(addr));
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if (disable) {
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val &= ~0x8;
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val |= (1 << 4) | (1 << 9);
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} else {
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val |= 0x8;
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val &= ~((1 << 4) | (1 << 9));
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}
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outl_p(val, AB_DATA(addr));
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if (amd_nb_dev) {
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addr = NB_PIF0_PWRDOWN_0;
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pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_ADDR, addr);
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pci_read_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, &val);
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if (disable)
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val &= ~(0x3f << 7);
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else
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val |= 0x3f << 7;
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pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, val);
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addr = NB_PIF0_PWRDOWN_1;
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pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_ADDR, addr);
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pci_read_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, &val);
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if (disable)
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val &= ~(0x3f << 7);
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else
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val |= 0x3f << 7;
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pci_write_config_dword(amd_nb_dev, NB_PCIE_INDX_DATA, val);
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}
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return;
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}
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/* fit urb's itds into the selected schedule slot; activate as needed */
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static int
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itd_link_urb (
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@ -1609,6 +1666,12 @@ itd_link_urb (
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urb->interval,
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next_uframe >> 3, next_uframe & 0x7);
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}
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if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
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if (ehci->amd_l1_fix == 1)
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ehci_quirk_amd_L1(ehci, 1);
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}
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ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
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/* fill iTDs uframe by uframe */
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@ -1733,6 +1796,11 @@ itd_complete (
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(void) disable_periodic(ehci);
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ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
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if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
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if (ehci->amd_l1_fix == 1)
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ehci_quirk_amd_L1(ehci, 0);
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}
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if (unlikely(list_is_singular(&stream->td_list))) {
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ehci_to_hcd(ehci)->self.bandwidth_allocated
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-= stream->bandwidth;
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@ -2018,6 +2086,12 @@ sitd_link_urb (
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(next_uframe >> 3) & (ehci->periodic_size - 1),
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stream->interval, hc32_to_cpu(ehci, stream->splits));
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}
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if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
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if (ehci->amd_l1_fix == 1)
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ehci_quirk_amd_L1(ehci, 1);
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}
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ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
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/* fill sITDs frame by frame */
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@ -2118,6 +2192,11 @@ sitd_complete (
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(void) disable_periodic(ehci);
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ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
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if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
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if (ehci->amd_l1_fix == 1)
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ehci_quirk_amd_L1(ehci, 0);
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}
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if (list_is_singular(&stream->td_list)) {
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ehci_to_hcd(ehci)->self.bandwidth_allocated
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-= stream->bandwidth;
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@ -130,6 +130,7 @@ struct ehci_hcd { /* one per controller */
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unsigned has_amcc_usb23:1;
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unsigned need_io_watchdog:1;
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unsigned broken_periodic:1;
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unsigned amd_l1_fix:1;
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unsigned fs_i_thresh:1; /* Intel iso scheduling */
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/* required for usb32 quirk */
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