[ARM] OMAP: wait for pwrdm transition after clk_enable()
Enabling clock in a disabled power domain causes the power domain to be turned on. However, the power transition is not always finished when clk_enable() returns and this randomly crashes the kernel when an interrupt happens right after the clk_enable, and the kernel tries to read the irq status register for that domain. Why the irq status register is inaccessible, I don't know. Also it doesn't seem to be related to the module being not powered up, but to the transition itself. The same could perhaps happen after clk_disable also, but I have not witnessed that. The problem affects at least dss, cam and sgx clocks. This change waits for the transition to be finished before returning from omap2_clkdm_clk_enable(). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -568,6 +568,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
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else
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omap2_clkdm_wakeup(clkdm);
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pwrdm_wait_transition(clkdm->pwrdm.ptr);
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return 0;
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}
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