cxgb3: simplify port type struct and usage
Second step in overall phy layer reorganization. Clean up the port_type_info structure. Support coextistence of clause 22 and clause 45 MDIO devices. Select the type of MDIO transaction on a per transaction basis. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Divy Le Ray
David S. Miller
parent
78e4689e90
commit
044979827e
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@ -54,7 +54,6 @@ struct port_info {
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struct adapter *adapter;
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struct vlan_group *vlan_grp;
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struct sge_qset *qs;
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const struct port_type_info *port_type;
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u8 port_id;
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u8 rx_csum_offload;
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u8 nqsets;
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@ -282,6 +281,7 @@ int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb);
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void t3_os_ext_intr_handler(struct adapter *adapter);
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void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
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int speed, int duplex, int fc);
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void t3_os_phymod_changed(struct adapter *adap, int port_id);
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void t3_sge_start(struct adapter *adap);
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void t3_sge_stop(struct adapter *adap);
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@ -122,7 +122,9 @@ static struct cphy_ops ael1002_ops = {
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int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops)
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{
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cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops);
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cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops,
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SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
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"10GBASE-R");
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ael100x_txon(phy);
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return 0;
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}
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@ -178,7 +180,9 @@ static struct cphy_ops ael1006_ops = {
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int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops)
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{
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cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops);
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cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops,
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SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
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"10GBASE-SR");
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ael100x_txon(phy);
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return 0;
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}
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@ -198,7 +202,9 @@ int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter,
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{
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unsigned int stat;
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cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops);
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cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops,
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SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP,
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"10GBASE-CX4");
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/*
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* Some cards where the PHY is supposed to be at address 0 actually
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@ -256,6 +262,8 @@ static struct cphy_ops xaui_direct_ops = {
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int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops)
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{
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cphy_init(phy, adapter, phy_addr, &xaui_direct_ops, mdio_ops);
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cphy_init(phy, adapter, phy_addr, &xaui_direct_ops, mdio_ops,
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SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP,
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"10GBASE-CX4");
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return 0;
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}
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@ -193,8 +193,6 @@ struct mdio_ops {
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struct adapter_info {
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unsigned char nports; /* # of ports */
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unsigned char phy_base_addr; /* MDIO PHY base address */
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unsigned char mdien;
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unsigned char mdiinv;
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unsigned int gpio_out; /* GPIO output settings */
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unsigned int gpio_intr; /* GPIO IRQ enable mask */
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unsigned long caps; /* adapter capabilities */
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@ -202,13 +200,6 @@ struct adapter_info {
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const char *desc; /* product description */
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};
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struct port_type_info {
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int (*phy_prep)(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *ops);
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unsigned int caps;
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const char *desc;
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};
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struct mc5_stats {
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unsigned long parity_err;
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unsigned long active_rgn_full;
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@ -548,7 +539,6 @@ enum {
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/* PHY operations */
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struct cphy_ops {
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void (*destroy)(struct cphy *phy);
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int (*reset)(struct cphy *phy, int wait);
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int (*intr_enable)(struct cphy *phy);
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@ -569,8 +559,10 @@ struct cphy_ops {
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/* A PHY instance */
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struct cphy {
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int addr; /* PHY address */
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int addr; /* PHY address */
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unsigned int caps; /* PHY capabilities */
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struct adapter *adapter; /* associated adapter */
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const char *desc; /* PHY description */
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unsigned long fifo_errors; /* FIFO over/under-flows */
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const struct cphy_ops *ops; /* PHY operations */
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int (*mdio_read)(struct adapter *adapter, int phy_addr, int mmd_addr,
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@ -595,10 +587,13 @@ static inline int mdio_write(struct cphy *phy, int mmd, int reg,
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/* Convenience initializer */
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static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
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int phy_addr, struct cphy_ops *phy_ops,
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const struct mdio_ops *mdio_ops)
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const struct mdio_ops *mdio_ops,
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unsigned int caps, const char *desc)
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{
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phy->adapter = adapter;
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phy->addr = phy_addr;
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phy->caps = caps;
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phy->adapter = adapter;
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phy->desc = desc;
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phy->ops = phy_ops;
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if (mdio_ops) {
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phy->mdio_read = mdio_ops->read;
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@ -2368,7 +2368,7 @@ static void check_link_status(struct adapter *adapter)
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struct net_device *dev = adapter->port[i];
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struct port_info *p = netdev_priv(dev);
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if (!(p->port_type->caps & SUPPORTED_IRQ) && netif_running(dev))
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if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev))
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t3_link_changed(adapter, i);
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}
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}
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@ -2731,7 +2731,7 @@ static void __devinit print_port_info(struct adapter *adap,
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if (!test_bit(i, &adap->registered_device_map))
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continue;
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printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n",
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dev->name, ai->desc, pi->port_type->desc,
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dev->name, ai->desc, pi->phy.desc,
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is_offload(adap) ? "R" : "", adap->params.rev, buf,
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(adap->flags & USING_MSIX) ? " MSI-X" :
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(adap->flags & USING_MSI) ? " MSI" : "");
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@ -194,21 +194,18 @@ int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
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static void mi1_init(struct adapter *adap, const struct adapter_info *ai)
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{
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u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;
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u32 val = F_PREEN | V_MDIINV(ai->mdiinv) | V_MDIEN(ai->mdien) |
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V_CLKDIV(clkdiv);
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u32 val = F_PREEN | V_CLKDIV(clkdiv);
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if (!(ai->caps & SUPPORTED_10000baseT_Full))
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val |= V_ST(1);
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t3_write_reg(adap, A_MI1_CFG, val);
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}
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#define MDIO_ATTEMPTS 10
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#define MDIO_ATTEMPTS 20
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/*
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* MI1 read/write operations for direct-addressed PHYs.
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* MI1 read/write operations for clause 22 PHYs.
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*/
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static int mi1_read(struct adapter *adapter, int phy_addr, int mmd_addr,
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int reg_addr, unsigned int *valp)
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static int t3_mi1_read(struct adapter *adapter, int phy_addr, int mmd_addr,
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int reg_addr, unsigned int *valp)
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{
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int ret;
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u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
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@ -217,16 +214,17 @@ static int mi1_read(struct adapter *adapter, int phy_addr, int mmd_addr,
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return -EINVAL;
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mutex_lock(&adapter->mdio_lock);
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t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
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t3_write_reg(adapter, A_MI1_ADDR, addr);
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t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
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ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
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ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
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if (!ret)
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*valp = t3_read_reg(adapter, A_MI1_DATA);
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mutex_unlock(&adapter->mdio_lock);
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return ret;
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}
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static int mi1_write(struct adapter *adapter, int phy_addr, int mmd_addr,
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static int t3_mi1_write(struct adapter *adapter, int phy_addr, int mmd_addr,
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int reg_addr, unsigned int val)
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{
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int ret;
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@ -236,19 +234,37 @@ static int mi1_write(struct adapter *adapter, int phy_addr, int mmd_addr,
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return -EINVAL;
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mutex_lock(&adapter->mdio_lock);
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t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
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t3_write_reg(adapter, A_MI1_ADDR, addr);
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t3_write_reg(adapter, A_MI1_DATA, val);
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t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
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ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
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ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
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mutex_unlock(&adapter->mdio_lock);
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return ret;
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}
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static const struct mdio_ops mi1_mdio_ops = {
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mi1_read,
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mi1_write
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t3_mi1_read,
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t3_mi1_write
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};
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/*
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* Performs the address cycle for clause 45 PHYs.
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* Must be called with the MDIO_LOCK held.
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*/
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static int mi1_wr_addr(struct adapter *adapter, int phy_addr, int mmd_addr,
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int reg_addr)
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{
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u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
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t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
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t3_write_reg(adapter, A_MI1_ADDR, addr);
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t3_write_reg(adapter, A_MI1_DATA, reg_addr);
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t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
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return t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
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MDIO_ATTEMPTS, 10);
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}
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/*
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* MI1 read/write operations for indirect-addressed PHYs.
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*/
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@ -256,17 +272,13 @@ static int mi1_ext_read(struct adapter *adapter, int phy_addr, int mmd_addr,
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int reg_addr, unsigned int *valp)
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{
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int ret;
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u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
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mutex_lock(&adapter->mdio_lock);
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t3_write_reg(adapter, A_MI1_ADDR, addr);
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t3_write_reg(adapter, A_MI1_DATA, reg_addr);
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t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
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ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
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ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr);
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if (!ret) {
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t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3));
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ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
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MDIO_ATTEMPTS, 20);
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MDIO_ATTEMPTS, 10);
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if (!ret)
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*valp = t3_read_reg(adapter, A_MI1_DATA);
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}
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@ -278,18 +290,14 @@ static int mi1_ext_write(struct adapter *adapter, int phy_addr, int mmd_addr,
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int reg_addr, unsigned int val)
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{
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int ret;
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u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
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mutex_lock(&adapter->mdio_lock);
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t3_write_reg(adapter, A_MI1_ADDR, addr);
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t3_write_reg(adapter, A_MI1_DATA, reg_addr);
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t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
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ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 20);
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ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr);
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if (!ret) {
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t3_write_reg(adapter, A_MI1_DATA, val);
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t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
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ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
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MDIO_ATTEMPTS, 20);
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MDIO_ATTEMPTS, 10);
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}
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mutex_unlock(&adapter->mdio_lock);
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return ret;
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@ -435,22 +443,22 @@ int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex)
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}
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static const struct adapter_info t3_adap_info[] = {
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{2, 0, 0, 0,
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{2, 0,
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F_GPIO2_OEN | F_GPIO4_OEN |
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F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
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0,
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&mi1_mdio_ops, "Chelsio PE9000"},
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{2, 0, 0, 0,
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{2, 0,
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F_GPIO2_OEN | F_GPIO4_OEN |
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F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
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0,
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&mi1_mdio_ops, "Chelsio T302"},
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{1, 0, 0, 0,
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{1, 0,
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F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
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F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
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0, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
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&mi1_mdio_ext_ops, "Chelsio T310"},
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{2, 0, 0, 0,
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{2, 0,
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F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
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F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
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F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0,
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@ -467,28 +475,22 @@ const struct adapter_info *t3_get_adapter_info(unsigned int id)
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return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
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}
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#define CAPS_1G (SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full | \
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SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII)
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#define CAPS_10G (SUPPORTED_10000baseT_Full | SUPPORTED_AUI)
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static const struct port_type_info port_types[] = {
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{NULL},
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{t3_ael1002_phy_prep, CAPS_10G | SUPPORTED_FIBRE,
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"10GBASE-XR"},
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{t3_vsc8211_phy_prep, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
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"10/100/1000BASE-T"},
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{NULL, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
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"10/100/1000BASE-T"},
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{t3_xaui_direct_phy_prep, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4"},
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{NULL, CAPS_10G, "10GBASE-KX4"},
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{t3_qt2045_phy_prep, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4"},
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{t3_ael1006_phy_prep, CAPS_10G | SUPPORTED_FIBRE,
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"10GBASE-SR"},
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{NULL, CAPS_10G | SUPPORTED_TP, "10GBASE-CX4"},
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struct port_type_info {
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int (*phy_prep)(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *ops);
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};
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#undef CAPS_1G
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#undef CAPS_10G
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static const struct port_type_info port_types[] = {
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{ NULL },
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{ t3_ael1002_phy_prep },
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{ t3_vsc8211_phy_prep },
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{ NULL},
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{ t3_xaui_direct_phy_prep },
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{ NULL },
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{ t3_qt2045_phy_prep },
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{ t3_ael1006_phy_prep },
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{ NULL },
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};
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#define VPD_ENTRY(name, len) \
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u8 name##_kword[2]; u8 name##_len; u8 name##_data[len]
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@ -1691,7 +1693,7 @@ int t3_phy_intr_handler(struct adapter *adapter)
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mask = gpi - (gpi & (gpi - 1));
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gpi -= mask;
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if (!(p->port_type->caps & SUPPORTED_IRQ))
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if (!(p->phy.caps & SUPPORTED_IRQ))
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continue;
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if (cause & mask) {
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@ -3556,7 +3558,7 @@ int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
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int reset)
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{
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int ret;
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unsigned int i, j = 0;
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unsigned int i, j = -1;
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get_pci_mode(adapter, &adapter->params.pci);
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@ -3620,19 +3622,18 @@ int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
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for_each_port(adapter, i) {
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u8 hw_addr[6];
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const struct port_type_info *pti;
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struct port_info *p = adap2pinfo(adapter, i);
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while (!adapter->params.vpd.port_type[j])
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++j;
|
||||
while (!adapter->params.vpd.port_type[++j])
|
||||
;
|
||||
|
||||
p->port_type = &port_types[adapter->params.vpd.port_type[j]];
|
||||
ret = p->port_type->phy_prep(&p->phy, adapter,
|
||||
ai->phy_base_addr + j,
|
||||
ai->mdio_ops);
|
||||
pti = &port_types[adapter->params.vpd.port_type[j]];
|
||||
ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
|
||||
ai->mdio_ops);
|
||||
if (ret)
|
||||
return ret;
|
||||
mac_prep(&p->mac, adapter, j);
|
||||
++j;
|
||||
|
||||
/*
|
||||
* The VPD EEPROM stores the base Ethernet address for the
|
||||
|
|
@ -3646,9 +3647,9 @@ int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
|
|||
ETH_ALEN);
|
||||
memcpy(adapter->port[i]->perm_addr, hw_addr,
|
||||
ETH_ALEN);
|
||||
init_link_config(&p->link_config, p->port_type->caps);
|
||||
init_link_config(&p->link_config, p->phy.caps);
|
||||
p->phy.ops->power_down(&p->phy, 1);
|
||||
if (!(p->port_type->caps & SUPPORTED_IRQ))
|
||||
if (!(p->phy.caps & SUPPORTED_IRQ))
|
||||
adapter->params.linkpoll_period = 10;
|
||||
}
|
||||
|
||||
|
|
@ -3664,7 +3665,7 @@ void t3_led_ready(struct adapter *adapter)
|
|||
int t3_replay_prep_adapter(struct adapter *adapter)
|
||||
{
|
||||
const struct adapter_info *ai = adapter->params.info;
|
||||
unsigned int i, j = 0;
|
||||
unsigned int i, j = -1;
|
||||
int ret;
|
||||
|
||||
early_hw_init(adapter, ai);
|
||||
|
|
@ -3673,17 +3674,17 @@ int t3_replay_prep_adapter(struct adapter *adapter)
|
|||
return ret;
|
||||
|
||||
for_each_port(adapter, i) {
|
||||
const struct port_type_info *pti;
|
||||
struct port_info *p = adap2pinfo(adapter, i);
|
||||
while (!adapter->params.vpd.port_type[j])
|
||||
++j;
|
||||
|
||||
ret = p->port_type->phy_prep(&p->phy, adapter,
|
||||
ai->phy_base_addr + j,
|
||||
ai->mdio_ops);
|
||||
while (!adapter->params.vpd.port_type[++j])
|
||||
;
|
||||
|
||||
pti = &port_types[adapter->params.vpd.port_type[j]];
|
||||
ret = pti->phy_prep(&p->phy, adapter, p->phy.addr, NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
p->phy.ops->power_down(&p->phy, 1);
|
||||
++j;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -224,6 +224,9 @@ static struct cphy_ops vsc8211_ops = {
|
|||
int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
|
||||
int phy_addr, const struct mdio_ops *mdio_ops)
|
||||
{
|
||||
cphy_init(phy, adapter, phy_addr, &vsc8211_ops, mdio_ops);
|
||||
cphy_init(phy, adapter, phy_addr, &vsc8211_ops, mdio_ops,
|
||||
SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full |
|
||||
SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII |
|
||||
SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T");
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Reference in New Issue