[SPARC64]: Fix sabre pci controllers with new probing scheme.
The SIMBA APB bridge is strange, it is a PCI bridge but it lacks some standard OF properties, in particular it lacks a 'ranges' property. What you have to do is read the IO and MEM range registers in the APB bridge to determine the ranges handled by each bridge. So fill in the bus resources by doing that. Since we now handle this quirk in the generic PCI and OF device probing layers, we can flat out eliminate all of that code from the sabre pci controller driver. In fact we can thus eliminate completely another quirk of the sabre driver. It tried to make the two APB bridges look like PBMs but that makes zero sense now (and it's questionable whether it ever made sense). So now just use pbm_A and probe the whole PCI hierarchy using that as the root. This simplification allows many future cleanups to occur. Also, I've found yet another quirk that needs to be worked around while testing this. You can't use the 'class-code' OF firmware property, especially for IDE controllers. We have to read the value out of PCI config space or else we'll see the value the device was showing before it was programmed into native mode. I'm starting to think it might be wise to just read all of the values out of PCI config space instead of using the OF properties. :-/ Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
David S. Miller
parent
a378fd0ee8
commit
01f94c4a6c
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@ -317,6 +317,11 @@ static unsigned int of_bus_default_get_flags(const u32 *addr)
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static int of_bus_pci_match(struct device_node *np)
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{
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if (!strcmp(np->type, "pci") || !strcmp(np->type, "pciex")) {
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char *model = of_get_property(np, "model", NULL);
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if (model && !strcmp(model, "SUNW,simba"))
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return 0;
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/* Do not do PCI specific frobbing if the
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* PCI bridge lacks a ranges property. We
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* want to pass it through up to the next
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@ -332,6 +337,21 @@ static int of_bus_pci_match(struct device_node *np)
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return 0;
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}
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static int of_bus_simba_match(struct device_node *np)
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{
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char *model = of_get_property(np, "model", NULL);
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if (model && !strcmp(model, "SUNW,simba"))
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return 1;
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return 0;
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}
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static int of_bus_simba_map(u32 *addr, const u32 *range,
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int na, int ns, int pna)
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{
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return 0;
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}
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static void of_bus_pci_count_cells(struct device_node *np,
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int *addrc, int *sizec)
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{
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@ -436,6 +456,15 @@ static struct of_bus of_busses[] = {
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.map = of_bus_pci_map,
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.get_flags = of_bus_pci_get_flags,
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},
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/* SIMBA */
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{
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.name = "simba",
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.addr_prop_name = "assigned-addresses",
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.match = of_bus_simba_match,
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.count_cells = of_bus_pci_count_cells,
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.map = of_bus_simba_map,
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.get_flags = of_bus_pci_get_flags,
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},
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/* SBUS */
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{
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.name = "sbus",
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@ -26,6 +26,7 @@
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#include <asm/ebus.h>
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#include <asm/isa.h>
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#include <asm/prom.h>
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#include <asm/apb.h>
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#include "pci_impl.h"
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@ -372,6 +373,7 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
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struct dev_archdata *sd;
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struct pci_dev *dev;
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const char *type;
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u32 class;
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dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
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if (!dev)
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@ -409,7 +411,15 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
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sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
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dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
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dev->class = of_getintprop_default(node, "class-code", 0);
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/* dev->class = of_getintprop_default(node, "class-code", 0); */
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/* We can't actually use the firmware value, we have to read what
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* is in the register right now. One reason is that in the case
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* of IDE interfaces the firmware can sample the value before the
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* the IDE interface is programmed into native mode.
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*/
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
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dev->class = class >> 8;
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printk(" class: 0x%x\n", dev->class);
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@ -440,6 +450,53 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
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return dev;
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}
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static void __init apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
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{
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u32 idx, first, last;
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first = 8;
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last = 0;
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for (idx = 0; idx < 8; idx++) {
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if ((map & (1 << idx)) != 0) {
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if (first > idx)
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first = idx;
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if (last < idx)
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last = idx;
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}
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}
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*first_p = first;
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*last_p = last;
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}
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/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
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* a proper 'ranges' property.
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*/
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static void __init apb_fake_ranges(struct pci_dev *dev,
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struct pci_bus *bus,
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struct pci_pbm_info *pbm)
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{
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struct resource *res;
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u32 first, last;
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u8 map;
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pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
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apb_calc_first_last(map, &first, &last);
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res = bus->resource[0];
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res->start = (first << 21);
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res->end = (last << 21) + ((1 << 21) - 1);
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res->flags = IORESOURCE_IO;
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pbm->parent->resource_adjust(dev, res, &pbm->io_space);
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pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
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apb_calc_first_last(map, &first, &last);
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res = bus->resource[1];
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res->start = (first << 21);
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res->end = (last << 21) + ((1 << 21) - 1);
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res->flags = IORESOURCE_MEM;
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pbm->parent->resource_adjust(dev, res, &pbm->mem_space);
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}
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static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
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struct device_node *node,
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struct pci_bus *bus);
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@ -452,7 +509,7 @@ void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
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{
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struct pci_bus *bus;
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const u32 *busrange, *ranges;
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int len, i;
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int len, i, simba;
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struct resource *res;
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unsigned int flags;
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u64 size;
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@ -467,10 +524,16 @@ void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
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return;
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}
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ranges = of_get_property(node, "ranges", &len);
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simba = 0;
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if (ranges == NULL) {
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printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
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node->full_name);
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return;
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char *model = of_get_property(node, "model", NULL);
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if (model && !strcmp(model, "SUNW,simba")) {
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simba = 1;
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} else {
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printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
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node->full_name);
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return;
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}
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}
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bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
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@ -484,7 +547,7 @@ void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
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bus->subordinate = busrange[1];
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bus->bridge_ctl = 0;
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/* parse ranges property */
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/* parse ranges property, or cook one up by hand for Simba */
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/* PCI #address-cells == 3 and #size-cells == 2 always */
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res = &dev->resource[PCI_BRIDGE_RESOURCES];
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for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
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@ -492,6 +555,10 @@ void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
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bus->resource[i] = res;
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++res;
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}
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if (simba) {
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apb_fake_ranges(dev, bus, pbm);
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goto simba_cont;
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}
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i = 1;
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for (; len >= 32; len -= 32, ranges += 8) {
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struct resource *root;
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@ -529,6 +596,7 @@ void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
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*/
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pbm->parent->resource_adjust(dev, res, root);
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}
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simba_cont:
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sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
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bus->number);
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printk(" bus name: %s\n", bus->name);
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@ -254,9 +254,6 @@ static int __sabre_out_of_range(struct pci_pbm_info *pbm,
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return 0;
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return ((pbm->parent == 0) ||
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((pbm == &pbm->parent->pbm_B) &&
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(bus == pbm->pci_first_busno) &&
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PCI_SLOT(devfn) > 8) ||
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((pbm == &pbm->parent->pbm_A) &&
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(bus == pbm->pci_first_busno) &&
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PCI_SLOT(devfn) > 8));
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@ -800,12 +797,10 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
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if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
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sabre_check_iommu_error(p, afsr, afar);
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pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
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pci_scan_for_target_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
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}
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if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA)) {
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if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
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pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
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pci_scan_for_master_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
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}
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/* For excessive retries, SABRE/PBM will abort the device
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* and there is no way to specifically check for excessive
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* retries in the config space status registers. So what
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@ -813,10 +808,8 @@ static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
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* abort events.
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*/
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if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR)) {
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if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
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pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
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pci_scan_for_parity_error(p, &p->pbm_B, p->pbm_B.pci_bus);
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}
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return IRQ_HANDLED;
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}
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@ -935,44 +928,33 @@ static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
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struct pci_dev *pdev;
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list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
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if (pdev->vendor == PCI_VENDOR_ID_SUN &&
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pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
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u32 word32;
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u16 word16;
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sabre_read_pci_cfg(pdev->bus, pdev->devfn,
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PCI_COMMAND, 2, &word32);
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word16 = (u16) word32;
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pci_read_config_word(pdev, PCI_COMMAND, &word16);
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word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
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PCI_COMMAND_IO;
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word32 = (u32) word16;
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sabre_write_pci_cfg(pdev->bus, pdev->devfn,
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PCI_COMMAND, 2, word32);
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pci_write_config_word(pdev, PCI_COMMAND, word16);
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/* Status register bits are "write 1 to clear". */
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sabre_write_pci_cfg(pdev->bus, pdev->devfn,
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PCI_STATUS, 2, 0xffff);
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sabre_write_pci_cfg(pdev->bus, pdev->devfn,
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PCI_SEC_STATUS, 2, 0xffff);
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pci_write_config_word(pdev, PCI_STATUS, 0xffff);
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pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
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/* Use a primary/seconday latency timer value
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* of 64.
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*/
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sabre_write_pci_cfg(pdev->bus, pdev->devfn,
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PCI_LATENCY_TIMER, 1, 64);
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sabre_write_pci_cfg(pdev->bus, pdev->devfn,
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PCI_SEC_LATENCY_TIMER, 1, 64);
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
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pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
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/* Enable reporting/forwarding of master aborts,
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* parity, and SERR.
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*/
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sabre_write_pci_cfg(pdev->bus, pdev->devfn,
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PCI_BRIDGE_CONTROL, 1,
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(PCI_BRIDGE_CTL_PARITY |
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PCI_BRIDGE_CTL_SERR |
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PCI_BRIDGE_CTL_MASTER_ABORT));
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pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
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(PCI_BRIDGE_CTL_PARITY |
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PCI_BRIDGE_CTL_SERR |
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PCI_BRIDGE_CTL_MASTER_ABORT));
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}
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}
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}
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@ -980,16 +962,13 @@ static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
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static void sabre_scan_bus(struct pci_controller_info *p)
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{
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static int once;
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struct pci_bus *sabre_bus, *pbus;
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struct pci_pbm_info *pbm;
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int sabres_scanned;
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struct pci_bus *pbus;
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/* The APB bridge speaks to the Sabre host PCI bridge
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* at 66Mhz, but the front side of APB runs at 33Mhz
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* for both segments.
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*/
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p->pbm_A.is_66mhz_capable = 0;
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p->pbm_B.is_66mhz_capable = 0;
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/* This driver has not been verified to handle
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* multiple SABREs yet, so trap this.
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@ -1003,36 +982,13 @@ static void sabre_scan_bus(struct pci_controller_info *p)
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}
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once++;
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sabre_bus = pci_scan_one_pbm(&p->pbm_A);
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if (!sabre_bus)
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pbus = pci_scan_one_pbm(&p->pbm_A);
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if (!pbus)
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return;
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sabre_root_bus = sabre_bus;
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sabre_root_bus = pbus;
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apb_init(p, sabre_bus);
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sabres_scanned = 0;
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list_for_each_entry(pbus, &sabre_bus->children, node) {
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if (pbus->number == p->pbm_A.pci_first_busno) {
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pbm = &p->pbm_A;
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} else if (pbus->number == p->pbm_B.pci_first_busno) {
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pbm = &p->pbm_B;
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} else
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continue;
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sabres_scanned++;
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pbus->sysdata = pbm;
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pbm->pci_bus = pbus;
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}
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if (!sabres_scanned) {
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/* Hummingbird, no APBs. */
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pbm = &p->pbm_A;
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sabre_bus->sysdata = pbm;
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pbm->pci_bus = sabre_bus;
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}
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apb_init(p, pbus);
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sabre_register_error_handlers(p);
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}
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@ -1089,213 +1045,54 @@ static void sabre_iommu_init(struct pci_controller_info *p,
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sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
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}
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static void pbm_register_toplevel_resources(struct pci_controller_info *p,
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struct pci_pbm_info *pbm)
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{
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char *name = pbm->name;
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unsigned long ibase = p->pbm_A.controller_regs + SABRE_IOSPACE;
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unsigned long mbase = p->pbm_A.controller_regs + SABRE_MEMSPACE;
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unsigned int devfn;
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unsigned long first, last, i;
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u8 *addr, map;
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sprintf(name, "SABRE%d PBM%c",
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p->index,
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(pbm == &p->pbm_A ? 'A' : 'B'));
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pbm->io_space.name = pbm->mem_space.name = name;
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devfn = PCI_DEVFN(1, (pbm == &p->pbm_A) ? 0 : 1);
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addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_IO_ADDRESS_MAP);
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map = 0;
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pci_config_read8(addr, &map);
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first = 8;
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last = 0;
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for (i = 0; i < 8; i++) {
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if ((map & (1 << i)) != 0) {
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if (first > i)
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first = i;
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if (last < i)
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last = i;
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}
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}
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pbm->io_space.start = ibase + (first << 21UL);
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pbm->io_space.end = ibase + (last << 21UL) + ((1 << 21UL) - 1);
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pbm->io_space.flags = IORESOURCE_IO;
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addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_MEM_ADDRESS_MAP);
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map = 0;
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pci_config_read8(addr, &map);
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first = 8;
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last = 0;
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for (i = 0; i < 8; i++) {
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if ((map & (1 << i)) != 0) {
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if (first > i)
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first = i;
|
||||
if (last < i)
|
||||
last = i;
|
||||
}
|
||||
}
|
||||
pbm->mem_space.start = mbase + (first << 29UL);
|
||||
pbm->mem_space.end = mbase + (last << 29UL) + ((1 << 29UL) - 1);
|
||||
pbm->mem_space.flags = IORESOURCE_MEM;
|
||||
|
||||
if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
|
||||
prom_printf("Cannot register PBM-%c's IO space.\n",
|
||||
(pbm == &p->pbm_A ? 'A' : 'B'));
|
||||
prom_halt();
|
||||
}
|
||||
if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
|
||||
prom_printf("Cannot register PBM-%c's MEM space.\n",
|
||||
(pbm == &p->pbm_A ? 'A' : 'B'));
|
||||
prom_halt();
|
||||
}
|
||||
|
||||
/* Register legacy regions if this PBM covers that area. */
|
||||
if (pbm->io_space.start == ibase &&
|
||||
pbm->mem_space.start == mbase)
|
||||
pci_register_legacy_regions(&pbm->io_space,
|
||||
&pbm->mem_space);
|
||||
}
|
||||
|
||||
static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 dma_start, u32 dma_end)
|
||||
{
|
||||
struct pci_pbm_info *pbm;
|
||||
struct device_node *node;
|
||||
struct property *prop;
|
||||
u32 *busrange;
|
||||
int len, simbas_found;
|
||||
struct resource *rp;
|
||||
|
||||
simbas_found = 0;
|
||||
node = dp->child;
|
||||
while (node != NULL) {
|
||||
if (strcmp(node->name, "pci"))
|
||||
goto next_pci;
|
||||
pbm = &p->pbm_A;
|
||||
pbm->name = dp->full_name;
|
||||
printk("%s: SABRE PCI Bus Module\n", pbm->name);
|
||||
|
||||
prop = of_find_property(node, "model", NULL);
|
||||
if (!prop || strncmp(prop->value, "SUNW,simba", prop->length))
|
||||
goto next_pci;
|
||||
pbm->chip_type = PBM_CHIP_TYPE_SABRE;
|
||||
pbm->parent = p;
|
||||
pbm->prom_node = dp;
|
||||
pbm->pci_first_slot = 1;
|
||||
pbm->pci_first_busno = p->pci_first_busno;
|
||||
pbm->pci_last_busno = p->pci_last_busno;
|
||||
|
||||
simbas_found++;
|
||||
pbm->io_space.name = pbm->mem_space.name = pbm->name;
|
||||
|
||||
prop = of_find_property(node, "bus-range", NULL);
|
||||
busrange = prop->value;
|
||||
if (busrange[0] == 1)
|
||||
pbm = &p->pbm_B;
|
||||
else
|
||||
pbm = &p->pbm_A;
|
||||
pbm->io_space.start = p->pbm_A.controller_regs + SABRE_IOSPACE;
|
||||
pbm->io_space.end = pbm->io_space.start + (1UL << 24) - 1UL;
|
||||
pbm->io_space.flags = IORESOURCE_IO;
|
||||
|
||||
pbm->name = node->full_name;
|
||||
printk("%s: SABRE PCI Bus Module\n", pbm->name);
|
||||
pbm->mem_space.start = (p->pbm_A.controller_regs + SABRE_MEMSPACE);
|
||||
pbm->mem_space.end = (pbm->mem_space.start + ((1UL << 32UL) - 1UL));
|
||||
pbm->mem_space.flags = IORESOURCE_MEM;
|
||||
|
||||
pbm->chip_type = PBM_CHIP_TYPE_SABRE;
|
||||
pbm->parent = p;
|
||||
pbm->prom_node = node;
|
||||
pbm->pci_first_slot = 1;
|
||||
pbm->pci_first_busno = busrange[0];
|
||||
pbm->pci_last_busno = busrange[1];
|
||||
|
||||
prop = of_find_property(node, "ranges", &len);
|
||||
if (prop) {
|
||||
pbm->pbm_ranges = prop->value;
|
||||
pbm->num_pbm_ranges =
|
||||
(len / sizeof(struct linux_prom_pci_ranges));
|
||||
} else {
|
||||
pbm->num_pbm_ranges = 0;
|
||||
}
|
||||
|
||||
prop = of_find_property(node, "interrupt-map", &len);
|
||||
if (prop) {
|
||||
pbm->pbm_intmap = prop->value;
|
||||
pbm->num_pbm_intmap =
|
||||
(len / sizeof(struct linux_prom_pci_intmap));
|
||||
|
||||
prop = of_find_property(node, "interrupt-map-mask",
|
||||
NULL);
|
||||
pbm->pbm_intmask = prop->value;
|
||||
} else {
|
||||
pbm->num_pbm_intmap = 0;
|
||||
}
|
||||
|
||||
pbm_register_toplevel_resources(p, pbm);
|
||||
|
||||
next_pci:
|
||||
node = node->sibling;
|
||||
if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
|
||||
prom_printf("Cannot register Sabre's IO space.\n");
|
||||
prom_halt();
|
||||
}
|
||||
if (simbas_found == 0) {
|
||||
struct resource *rp;
|
||||
|
||||
/* No APBs underneath, probably this is a hummingbird
|
||||
* system.
|
||||
*/
|
||||
pbm = &p->pbm_A;
|
||||
pbm->parent = p;
|
||||
pbm->prom_node = dp;
|
||||
pbm->pci_first_busno = p->pci_first_busno;
|
||||
pbm->pci_last_busno = p->pci_last_busno;
|
||||
|
||||
prop = of_find_property(dp, "ranges", &len);
|
||||
if (prop) {
|
||||
pbm->pbm_ranges = prop->value;
|
||||
pbm->num_pbm_ranges =
|
||||
(len / sizeof(struct linux_prom_pci_ranges));
|
||||
} else {
|
||||
pbm->num_pbm_ranges = 0;
|
||||
}
|
||||
|
||||
prop = of_find_property(dp, "interrupt-map", &len);
|
||||
if (prop) {
|
||||
pbm->pbm_intmap = prop->value;
|
||||
pbm->num_pbm_intmap =
|
||||
(len / sizeof(struct linux_prom_pci_intmap));
|
||||
|
||||
prop = of_find_property(dp, "interrupt-map-mask",
|
||||
NULL);
|
||||
pbm->pbm_intmask = prop->value;
|
||||
} else {
|
||||
pbm->num_pbm_intmap = 0;
|
||||
}
|
||||
|
||||
pbm->name = dp->full_name;
|
||||
printk("%s: SABRE PCI Bus Module\n", pbm->name);
|
||||
|
||||
pbm->io_space.name = pbm->mem_space.name = pbm->name;
|
||||
|
||||
/* Hack up top-level resources. */
|
||||
pbm->io_space.start = p->pbm_A.controller_regs + SABRE_IOSPACE;
|
||||
pbm->io_space.end = pbm->io_space.start + (1UL << 24) - 1UL;
|
||||
pbm->io_space.flags = IORESOURCE_IO;
|
||||
|
||||
pbm->mem_space.start =
|
||||
(p->pbm_A.controller_regs + SABRE_MEMSPACE);
|
||||
pbm->mem_space.end =
|
||||
(pbm->mem_space.start + ((1UL << 32UL) - 1UL));
|
||||
pbm->mem_space.flags = IORESOURCE_MEM;
|
||||
|
||||
if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
|
||||
prom_printf("Cannot register Hummingbird's IO space.\n");
|
||||
prom_halt();
|
||||
}
|
||||
if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
|
||||
prom_printf("Cannot register Hummingbird's MEM space.\n");
|
||||
prom_halt();
|
||||
}
|
||||
|
||||
rp = kmalloc(sizeof(*rp), GFP_KERNEL);
|
||||
if (!rp) {
|
||||
prom_printf("Cannot allocate IOMMU resource.\n");
|
||||
prom_halt();
|
||||
}
|
||||
rp->name = "IOMMU";
|
||||
rp->start = pbm->mem_space.start + (unsigned long) dma_start;
|
||||
rp->end = pbm->mem_space.start + (unsigned long) dma_end - 1UL;
|
||||
rp->flags = IORESOURCE_BUSY;
|
||||
request_resource(&pbm->mem_space, rp);
|
||||
|
||||
pci_register_legacy_regions(&pbm->io_space,
|
||||
&pbm->mem_space);
|
||||
if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
|
||||
prom_printf("Cannot register Sabre's MEM space.\n");
|
||||
prom_halt();
|
||||
}
|
||||
|
||||
rp = kmalloc(sizeof(*rp), GFP_KERNEL);
|
||||
if (!rp) {
|
||||
prom_printf("Cannot allocate IOMMU resource.\n");
|
||||
prom_halt();
|
||||
}
|
||||
rp->name = "IOMMU";
|
||||
rp->start = pbm->mem_space.start + (unsigned long) dma_start;
|
||||
rp->end = pbm->mem_space.start + (unsigned long) dma_end - 1UL;
|
||||
rp->flags = IORESOURCE_BUSY;
|
||||
request_resource(&pbm->mem_space, rp);
|
||||
|
||||
pci_register_legacy_regions(&pbm->io_space,
|
||||
&pbm->mem_space);
|
||||
}
|
||||
|
||||
void sabre_init(struct device_node *dp, char *model_name)
|
||||
|
|
@ -1303,7 +1100,6 @@ void sabre_init(struct device_node *dp, char *model_name)
|
|||
struct linux_prom64_registers *pr_regs;
|
||||
struct pci_controller_info *p;
|
||||
struct pci_iommu *iommu;
|
||||
struct property *prop;
|
||||
int tsbsize;
|
||||
u32 *busrange;
|
||||
u32 *vdma;
|
||||
|
|
@ -1314,13 +1110,9 @@ void sabre_init(struct device_node *dp, char *model_name)
|
|||
if (!strcmp(model_name, "pci108e,a001"))
|
||||
hummingbird_p = 1;
|
||||
else if (!strcmp(model_name, "SUNW,sabre")) {
|
||||
prop = of_find_property(dp, "compatible", NULL);
|
||||
if (prop) {
|
||||
const char *compat = prop->value;
|
||||
|
||||
if (!strcmp(compat, "pci108e,a001"))
|
||||
hummingbird_p = 1;
|
||||
}
|
||||
const char *compat = of_get_property(dp, "compatible", NULL);
|
||||
if (compat && !strcmp(compat, "pci108e,a001"))
|
||||
hummingbird_p = 1;
|
||||
if (!hummingbird_p) {
|
||||
struct device_node *dp;
|
||||
|
||||
|
|
@ -1344,18 +1136,14 @@ void sabre_init(struct device_node *dp, char *model_name)
|
|||
prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
|
||||
prom_halt();
|
||||
}
|
||||
p->pbm_A.iommu = p->pbm_B.iommu = iommu;
|
||||
p->pbm_A.iommu = iommu;
|
||||
|
||||
upa_portid = 0xff;
|
||||
prop = of_find_property(dp, "upa-portid", NULL);
|
||||
if (prop)
|
||||
upa_portid = *(u32 *) prop->value;
|
||||
upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
|
||||
|
||||
p->next = pci_controller_root;
|
||||
pci_controller_root = p;
|
||||
|
||||
p->pbm_A.portid = upa_portid;
|
||||
p->pbm_B.portid = upa_portid;
|
||||
p->index = pci_num_controllers++;
|
||||
p->pbms_same_domain = 1;
|
||||
p->scan_bus = sabre_scan_bus;
|
||||
|
|
@ -1367,14 +1155,12 @@ void sabre_init(struct device_node *dp, char *model_name)
|
|||
* Map in SABRE register set and report the presence of this SABRE.
|
||||
*/
|
||||
|
||||
prop = of_find_property(dp, "reg", NULL);
|
||||
pr_regs = prop->value;
|
||||
pr_regs = of_get_property(dp, "reg", NULL);
|
||||
|
||||
/*
|
||||
* First REG in property is base of entire SABRE register space.
|
||||
*/
|
||||
p->pbm_A.controller_regs = pr_regs[0].phys_addr;
|
||||
p->pbm_B.controller_regs = pr_regs[0].phys_addr;
|
||||
|
||||
/* Clear interrupts */
|
||||
|
||||
|
|
@ -1392,11 +1178,10 @@ void sabre_init(struct device_node *dp, char *model_name)
|
|||
SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
|
||||
|
||||
/* Now map in PCI config space for entire SABRE. */
|
||||
p->pbm_A.config_space = p->pbm_B.config_space =
|
||||
p->pbm_A.config_space =
|
||||
(p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
|
||||
|
||||
prop = of_find_property(dp, "virtual-dma", NULL);
|
||||
vdma = prop->value;
|
||||
vdma = of_get_property(dp, "virtual-dma", NULL);
|
||||
|
||||
dma_mask = vdma[0];
|
||||
switch(vdma[1]) {
|
||||
|
|
@ -1420,8 +1205,7 @@ void sabre_init(struct device_node *dp, char *model_name)
|
|||
|
||||
sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
|
||||
|
||||
prop = of_find_property(dp, "bus-range", NULL);
|
||||
busrange = prop->value;
|
||||
busrange = of_get_property(dp, "bus-range", NULL);
|
||||
p->pci_first_busno = busrange[0];
|
||||
p->pci_last_busno = busrange[1];
|
||||
|
||||
|
|
|
|||
Reference in New Issue