2006-05-24 00:35:34 +00:00
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/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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/*
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* This driver supports an Intel I/OAT DMA engine, which does asynchronous
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* copy operations.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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2006-05-24 00:37:58 +00:00
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#include <linux/dma-mapping.h>
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2006-05-24 00:35:34 +00:00
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#include "ioatdma.h"
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#include "ioatdma_io.h"
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#include "ioatdma_registers.h"
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#include "ioatdma_hw.h"
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#define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
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#define to_ioat_device(dev) container_of(dev, struct ioat_device, common)
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#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
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/* internal functions */
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static int __devinit ioat_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
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static void __devexit ioat_remove(struct pci_dev *pdev);
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static int enumerate_dma_channels(struct ioat_device *device)
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{
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u8 xfercap_scale;
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u32 xfercap;
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int i;
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struct ioat_dma_chan *ioat_chan;
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device->common.chancnt = ioatdma_read8(device, IOAT_CHANCNT_OFFSET);
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xfercap_scale = ioatdma_read8(device, IOAT_XFERCAP_OFFSET);
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xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
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for (i = 0; i < device->common.chancnt; i++) {
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ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
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if (!ioat_chan) {
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device->common.chancnt = i;
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break;
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}
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ioat_chan->device = device;
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ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
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ioat_chan->xfercap = xfercap;
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spin_lock_init(&ioat_chan->cleanup_lock);
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spin_lock_init(&ioat_chan->desc_lock);
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INIT_LIST_HEAD(&ioat_chan->free_desc);
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INIT_LIST_HEAD(&ioat_chan->used_desc);
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/* This should be made common somewhere in dmaengine.c */
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ioat_chan->common.device = &device->common;
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ioat_chan->common.client = NULL;
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list_add_tail(&ioat_chan->common.device_node,
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&device->common.channels);
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}
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return device->common.chancnt;
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}
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static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
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struct ioat_dma_chan *ioat_chan,
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int flags)
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{
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struct ioat_dma_descriptor *desc;
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struct ioat_desc_sw *desc_sw;
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struct ioat_device *ioat_device;
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dma_addr_t phys;
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ioat_device = to_ioat_device(ioat_chan->common.device);
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desc = pci_pool_alloc(ioat_device->dma_pool, flags, &phys);
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if (unlikely(!desc))
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return NULL;
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desc_sw = kzalloc(sizeof(*desc_sw), flags);
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if (unlikely(!desc_sw)) {
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pci_pool_free(ioat_device->dma_pool, desc, phys);
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return NULL;
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}
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memset(desc, 0, sizeof(*desc));
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desc_sw->hw = desc;
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desc_sw->phys = phys;
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return desc_sw;
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}
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#define INITIAL_IOAT_DESC_COUNT 128
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static void ioat_start_null_desc(struct ioat_dma_chan *ioat_chan);
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/* returns the actual number of allocated descriptors */
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static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
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struct ioat_desc_sw *desc = NULL;
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u16 chanctrl;
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u32 chanerr;
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int i;
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LIST_HEAD(tmp_list);
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/*
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* In-use bit automatically set by reading chanctrl
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* If 0, we got it, if 1, someone else did
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*/
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chanctrl = ioatdma_chan_read16(ioat_chan, IOAT_CHANCTRL_OFFSET);
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if (chanctrl & IOAT_CHANCTRL_CHANNEL_IN_USE)
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return -EBUSY;
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/* Setup register to interrupt and write completion status on error */
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chanctrl = IOAT_CHANCTRL_CHANNEL_IN_USE |
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IOAT_CHANCTRL_ERR_INT_EN |
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IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
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IOAT_CHANCTRL_ERR_COMPLETION_EN;
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ioatdma_chan_write16(ioat_chan, IOAT_CHANCTRL_OFFSET, chanctrl);
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chanerr = ioatdma_chan_read32(ioat_chan, IOAT_CHANERR_OFFSET);
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if (chanerr) {
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printk("IOAT: CHANERR = %x, clearing\n", chanerr);
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ioatdma_chan_write32(ioat_chan, IOAT_CHANERR_OFFSET, chanerr);
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}
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/* Allocate descriptors */
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for (i = 0; i < INITIAL_IOAT_DESC_COUNT; i++) {
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desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
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if (!desc) {
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printk(KERN_ERR "IOAT: Only %d initial descriptors\n", i);
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break;
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}
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list_add_tail(&desc->node, &tmp_list);
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}
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spin_lock_bh(&ioat_chan->desc_lock);
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list_splice(&tmp_list, &ioat_chan->free_desc);
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spin_unlock_bh(&ioat_chan->desc_lock);
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/* allocate a completion writeback area */
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/* doing 2 32bit writes to mmio since 1 64b write doesn't work */
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ioat_chan->completion_virt =
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pci_pool_alloc(ioat_chan->device->completion_pool,
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GFP_KERNEL,
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&ioat_chan->completion_addr);
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memset(ioat_chan->completion_virt, 0,
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sizeof(*ioat_chan->completion_virt));
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ioatdma_chan_write32(ioat_chan, IOAT_CHANCMP_OFFSET_LOW,
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((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF);
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ioatdma_chan_write32(ioat_chan, IOAT_CHANCMP_OFFSET_HIGH,
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((u64) ioat_chan->completion_addr) >> 32);
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ioat_start_null_desc(ioat_chan);
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return i;
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}
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static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
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static void ioat_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
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struct ioat_device *ioat_device = to_ioat_device(chan->device);
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struct ioat_desc_sw *desc, *_desc;
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u16 chanctrl;
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int in_use_descs = 0;
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ioat_dma_memcpy_cleanup(ioat_chan);
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ioatdma_chan_write8(ioat_chan, IOAT_CHANCMD_OFFSET, IOAT_CHANCMD_RESET);
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spin_lock_bh(&ioat_chan->desc_lock);
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list_for_each_entry_safe(desc, _desc, &ioat_chan->used_desc, node) {
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in_use_descs++;
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list_del(&desc->node);
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pci_pool_free(ioat_device->dma_pool, desc->hw, desc->phys);
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kfree(desc);
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}
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list_for_each_entry_safe(desc, _desc, &ioat_chan->free_desc, node) {
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list_del(&desc->node);
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pci_pool_free(ioat_device->dma_pool, desc->hw, desc->phys);
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kfree(desc);
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}
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spin_unlock_bh(&ioat_chan->desc_lock);
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pci_pool_free(ioat_device->completion_pool,
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ioat_chan->completion_virt,
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ioat_chan->completion_addr);
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/* one is ok since we left it on there on purpose */
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if (in_use_descs > 1)
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printk(KERN_ERR "IOAT: Freeing %d in use descriptors!\n",
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in_use_descs - 1);
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ioat_chan->last_completion = ioat_chan->completion_addr = 0;
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/* Tell hw the chan is free */
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chanctrl = ioatdma_chan_read16(ioat_chan, IOAT_CHANCTRL_OFFSET);
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chanctrl &= ~IOAT_CHANCTRL_CHANNEL_IN_USE;
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ioatdma_chan_write16(ioat_chan, IOAT_CHANCTRL_OFFSET, chanctrl);
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}
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/**
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* do_ioat_dma_memcpy - actual function that initiates a IOAT DMA transaction
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* @chan: IOAT DMA channel handle
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* @dest: DMA destination address
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* @src: DMA source address
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* @len: transaction length in bytes
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*/
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static dma_cookie_t do_ioat_dma_memcpy(struct ioat_dma_chan *ioat_chan,
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dma_addr_t dest,
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dma_addr_t src,
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size_t len)
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{
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struct ioat_desc_sw *first;
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struct ioat_desc_sw *prev;
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struct ioat_desc_sw *new;
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dma_cookie_t cookie;
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LIST_HEAD(new_chain);
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u32 copy;
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size_t orig_len;
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dma_addr_t orig_src, orig_dst;
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unsigned int desc_count = 0;
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unsigned int append = 0;
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if (!ioat_chan || !dest || !src)
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return -EFAULT;
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if (!len)
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return ioat_chan->common.cookie;
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orig_len = len;
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orig_src = src;
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orig_dst = dest;
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first = NULL;
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prev = NULL;
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spin_lock_bh(&ioat_chan->desc_lock);
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while (len) {
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if (!list_empty(&ioat_chan->free_desc)) {
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new = to_ioat_desc(ioat_chan->free_desc.next);
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list_del(&new->node);
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} else {
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/* try to get another desc */
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new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
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/* will this ever happen? */
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/* TODO add upper limit on these */
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BUG_ON(!new);
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}
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copy = min((u32) len, ioat_chan->xfercap);
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new->hw->size = copy;
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new->hw->ctl = 0;
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new->hw->src_addr = src;
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new->hw->dst_addr = dest;
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new->cookie = 0;
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/* chain together the physical address list for the HW */
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if (!first)
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first = new;
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else
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prev->hw->next = (u64) new->phys;
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prev = new;
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len -= copy;
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dest += copy;
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src += copy;
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list_add_tail(&new->node, &new_chain);
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desc_count++;
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}
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new->hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
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new->hw->next = 0;
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/* cookie incr and addition to used_list must be atomic */
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cookie = ioat_chan->common.cookie;
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cookie++;
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if (cookie < 0)
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cookie = 1;
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ioat_chan->common.cookie = new->cookie = cookie;
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pci_unmap_addr_set(new, src, orig_src);
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pci_unmap_addr_set(new, dst, orig_dst);
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pci_unmap_len_set(new, src_len, orig_len);
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pci_unmap_len_set(new, dst_len, orig_len);
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/* write address into NextDescriptor field of last desc in chain */
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to_ioat_desc(ioat_chan->used_desc.prev)->hw->next = first->phys;
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list_splice_init(&new_chain, ioat_chan->used_desc.prev);
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ioat_chan->pending += desc_count;
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if (ioat_chan->pending >= 20) {
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append = 1;
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ioat_chan->pending = 0;
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}
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spin_unlock_bh(&ioat_chan->desc_lock);
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if (append)
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ioatdma_chan_write8(ioat_chan,
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IOAT_CHANCMD_OFFSET,
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IOAT_CHANCMD_APPEND);
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return cookie;
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}
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/**
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* ioat_dma_memcpy_buf_to_buf - wrapper that takes src & dest bufs
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* @chan: IOAT DMA channel handle
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* @dest: DMA destination address
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* @src: DMA source address
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* @len: transaction length in bytes
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*/
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static dma_cookie_t ioat_dma_memcpy_buf_to_buf(struct dma_chan *chan,
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void *dest,
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void *src,
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size_t len)
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{
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dma_addr_t dest_addr;
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dma_addr_t src_addr;
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struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
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dest_addr = pci_map_single(ioat_chan->device->pdev,
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dest, len, PCI_DMA_FROMDEVICE);
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src_addr = pci_map_single(ioat_chan->device->pdev,
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src, len, PCI_DMA_TODEVICE);
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return do_ioat_dma_memcpy(ioat_chan, dest_addr, src_addr, len);
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}
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/**
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* ioat_dma_memcpy_buf_to_pg - wrapper, copying from a buf to a page
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|
|
* @chan: IOAT DMA channel handle
|
|
|
|
* @page: pointer to the page to copy to
|
|
|
|
* @offset: offset into that page
|
|
|
|
* @src: DMA source address
|
|
|
|
* @len: transaction length in bytes
|
|
|
|
*/
|
|
|
|
|
|
|
|
static dma_cookie_t ioat_dma_memcpy_buf_to_pg(struct dma_chan *chan,
|
|
|
|
struct page *page,
|
|
|
|
unsigned int offset,
|
|
|
|
void *src,
|
|
|
|
size_t len)
|
|
|
|
{
|
|
|
|
dma_addr_t dest_addr;
|
|
|
|
dma_addr_t src_addr;
|
|
|
|
struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
|
|
|
|
|
|
|
|
dest_addr = pci_map_page(ioat_chan->device->pdev,
|
|
|
|
page, offset, len, PCI_DMA_FROMDEVICE);
|
|
|
|
src_addr = pci_map_single(ioat_chan->device->pdev,
|
|
|
|
src, len, PCI_DMA_TODEVICE);
|
|
|
|
|
|
|
|
return do_ioat_dma_memcpy(ioat_chan, dest_addr, src_addr, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ioat_dma_memcpy_pg_to_pg - wrapper, copying between two pages
|
|
|
|
* @chan: IOAT DMA channel handle
|
|
|
|
* @dest_pg: pointer to the page to copy to
|
|
|
|
* @dest_off: offset into that page
|
|
|
|
* @src_pg: pointer to the page to copy from
|
|
|
|
* @src_off: offset into that page
|
|
|
|
* @len: transaction length in bytes. This is guaranteed to not make a copy
|
|
|
|
* across a page boundary.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static dma_cookie_t ioat_dma_memcpy_pg_to_pg(struct dma_chan *chan,
|
|
|
|
struct page *dest_pg,
|
|
|
|
unsigned int dest_off,
|
|
|
|
struct page *src_pg,
|
|
|
|
unsigned int src_off,
|
|
|
|
size_t len)
|
|
|
|
{
|
|
|
|
dma_addr_t dest_addr;
|
|
|
|
dma_addr_t src_addr;
|
|
|
|
struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
|
|
|
|
|
|
|
|
dest_addr = pci_map_page(ioat_chan->device->pdev,
|
|
|
|
dest_pg, dest_off, len, PCI_DMA_FROMDEVICE);
|
|
|
|
src_addr = pci_map_page(ioat_chan->device->pdev,
|
|
|
|
src_pg, src_off, len, PCI_DMA_TODEVICE);
|
|
|
|
|
|
|
|
return do_ioat_dma_memcpy(ioat_chan, dest_addr, src_addr, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ioat_dma_memcpy_issue_pending - push potentially unrecognoized appended descriptors to hw
|
|
|
|
* @chan: DMA channel handle
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void ioat_dma_memcpy_issue_pending(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
|
|
|
|
|
|
|
|
if (ioat_chan->pending != 0) {
|
|
|
|
ioat_chan->pending = 0;
|
|
|
|
ioatdma_chan_write8(ioat_chan,
|
|
|
|
IOAT_CHANCMD_OFFSET,
|
|
|
|
IOAT_CHANCMD_APPEND);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *chan)
|
|
|
|
{
|
|
|
|
unsigned long phys_complete;
|
|
|
|
struct ioat_desc_sw *desc, *_desc;
|
|
|
|
dma_cookie_t cookie = 0;
|
|
|
|
|
|
|
|
prefetch(chan->completion_virt);
|
|
|
|
|
|
|
|
if (!spin_trylock(&chan->cleanup_lock))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* The completion writeback can happen at any time,
|
|
|
|
so reads by the driver need to be atomic operations
|
|
|
|
The descriptor physical addresses are limited to 32-bits
|
|
|
|
when the CPU can only do a 32-bit mov */
|
|
|
|
|
|
|
|
#if (BITS_PER_LONG == 64)
|
|
|
|
phys_complete =
|
|
|
|
chan->completion_virt->full & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
|
|
|
|
#else
|
|
|
|
phys_complete = chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if ((chan->completion_virt->full & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
|
|
|
|
IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
|
|
|
|
printk("IOAT: Channel halted, chanerr = %x\n",
|
|
|
|
ioatdma_chan_read32(chan, IOAT_CHANERR_OFFSET));
|
|
|
|
|
|
|
|
/* TODO do something to salvage the situation */
|
|
|
|
}
|
|
|
|
|
|
|
|
if (phys_complete == chan->last_completion) {
|
|
|
|
spin_unlock(&chan->cleanup_lock);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_bh(&chan->desc_lock);
|
|
|
|
list_for_each_entry_safe(desc, _desc, &chan->used_desc, node) {
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Incoming DMA requests may use multiple descriptors, due to
|
|
|
|
* exceeding xfercap, perhaps. If so, only the last one will
|
|
|
|
* have a cookie, and require unmapping.
|
|
|
|
*/
|
|
|
|
if (desc->cookie) {
|
|
|
|
cookie = desc->cookie;
|
|
|
|
|
|
|
|
/* yes we are unmapping both _page and _single alloc'd
|
|
|
|
regions with unmap_page. Is this *really* that bad?
|
|
|
|
*/
|
|
|
|
pci_unmap_page(chan->device->pdev,
|
|
|
|
pci_unmap_addr(desc, dst),
|
|
|
|
pci_unmap_len(desc, dst_len),
|
|
|
|
PCI_DMA_FROMDEVICE);
|
|
|
|
pci_unmap_page(chan->device->pdev,
|
|
|
|
pci_unmap_addr(desc, src),
|
|
|
|
pci_unmap_len(desc, src_len),
|
|
|
|
PCI_DMA_TODEVICE);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (desc->phys != phys_complete) {
|
|
|
|
/* a completed entry, but not the last, so cleanup */
|
|
|
|
list_del(&desc->node);
|
|
|
|
list_add_tail(&desc->node, &chan->free_desc);
|
|
|
|
} else {
|
|
|
|
/* last used desc. Do not remove, so we can append from
|
|
|
|
it, but don't look at it next time, either */
|
|
|
|
desc->cookie = 0;
|
|
|
|
|
|
|
|
/* TODO check status bits? */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_bh(&chan->desc_lock);
|
|
|
|
|
|
|
|
chan->last_completion = phys_complete;
|
|
|
|
if (cookie != 0)
|
|
|
|
chan->completed_cookie = cookie;
|
|
|
|
|
|
|
|
spin_unlock(&chan->cleanup_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ioat_dma_is_complete - poll the status of a IOAT DMA transaction
|
|
|
|
* @chan: IOAT DMA channel handle
|
|
|
|
* @cookie: DMA transaction identifier
|
|
|
|
*/
|
|
|
|
|
|
|
|
static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
|
|
|
|
dma_cookie_t cookie,
|
|
|
|
dma_cookie_t *done,
|
|
|
|
dma_cookie_t *used)
|
|
|
|
{
|
|
|
|
struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
|
|
|
|
dma_cookie_t last_used;
|
|
|
|
dma_cookie_t last_complete;
|
|
|
|
enum dma_status ret;
|
|
|
|
|
|
|
|
last_used = chan->cookie;
|
|
|
|
last_complete = ioat_chan->completed_cookie;
|
|
|
|
|
|
|
|
if (done)
|
|
|
|
*done= last_complete;
|
|
|
|
if (used)
|
|
|
|
*used = last_used;
|
|
|
|
|
|
|
|
ret = dma_async_is_complete(cookie, last_complete, last_used);
|
|
|
|
if (ret == DMA_SUCCESS)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ioat_dma_memcpy_cleanup(ioat_chan);
|
|
|
|
|
|
|
|
last_used = chan->cookie;
|
|
|
|
last_complete = ioat_chan->completed_cookie;
|
|
|
|
|
|
|
|
if (done)
|
|
|
|
*done= last_complete;
|
|
|
|
if (used)
|
|
|
|
*used = last_used;
|
|
|
|
|
|
|
|
return dma_async_is_complete(cookie, last_complete, last_used);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PCI API */
|
|
|
|
|
|
|
|
static struct pci_device_id ioat_pci_tbl[] = {
|
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT) },
|
|
|
|
{ 0, }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_driver ioat_pci_drv = {
|
|
|
|
.name = "ioatdma",
|
|
|
|
.id_table = ioat_pci_tbl,
|
|
|
|
.probe = ioat_probe,
|
|
|
|
.remove = __devexit_p(ioat_remove),
|
|
|
|
};
|
|
|
|
|
|
|
|
static irqreturn_t ioat_do_interrupt(int irq, void *data, struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
struct ioat_device *instance = data;
|
|
|
|
unsigned long attnstatus;
|
|
|
|
u8 intrctrl;
|
|
|
|
|
|
|
|
intrctrl = ioatdma_read8(instance, IOAT_INTRCTRL_OFFSET);
|
|
|
|
|
|
|
|
if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
|
|
|
|
ioatdma_write8(instance, IOAT_INTRCTRL_OFFSET, intrctrl);
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
attnstatus = ioatdma_read32(instance, IOAT_ATTNSTATUS_OFFSET);
|
|
|
|
|
|
|
|
printk(KERN_ERR "ioatdma error: interrupt! status %lx\n", attnstatus);
|
|
|
|
|
|
|
|
ioatdma_write8(instance, IOAT_INTRCTRL_OFFSET, intrctrl);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ioat_start_null_desc(struct ioat_dma_chan *ioat_chan)
|
|
|
|
{
|
|
|
|
struct ioat_desc_sw *desc;
|
|
|
|
|
|
|
|
spin_lock_bh(&ioat_chan->desc_lock);
|
|
|
|
|
|
|
|
if (!list_empty(&ioat_chan->free_desc)) {
|
|
|
|
desc = to_ioat_desc(ioat_chan->free_desc.next);
|
|
|
|
list_del(&desc->node);
|
|
|
|
} else {
|
|
|
|
/* try to get another desc */
|
|
|
|
spin_unlock_bh(&ioat_chan->desc_lock);
|
|
|
|
desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
|
|
|
|
spin_lock_bh(&ioat_chan->desc_lock);
|
|
|
|
/* will this ever happen? */
|
|
|
|
BUG_ON(!desc);
|
|
|
|
}
|
|
|
|
|
|
|
|
desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
|
|
|
|
desc->hw->next = 0;
|
|
|
|
|
|
|
|
list_add_tail(&desc->node, &ioat_chan->used_desc);
|
|
|
|
spin_unlock_bh(&ioat_chan->desc_lock);
|
|
|
|
|
|
|
|
#if (BITS_PER_LONG == 64)
|
|
|
|
ioatdma_chan_write64(ioat_chan, IOAT_CHAINADDR_OFFSET, desc->phys);
|
|
|
|
#else
|
|
|
|
ioatdma_chan_write32(ioat_chan,
|
|
|
|
IOAT_CHAINADDR_OFFSET_LOW,
|
|
|
|
(u32) desc->phys);
|
|
|
|
ioatdma_chan_write32(ioat_chan, IOAT_CHAINADDR_OFFSET_HIGH, 0);
|
|
|
|
#endif
|
|
|
|
ioatdma_chan_write8(ioat_chan, IOAT_CHANCMD_OFFSET, IOAT_CHANCMD_START);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Perform a IOAT transaction to verify the HW works.
|
|
|
|
*/
|
|
|
|
#define IOAT_TEST_SIZE 2000
|
|
|
|
|
|
|
|
static int ioat_self_test(struct ioat_device *device)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
u8 *src;
|
|
|
|
u8 *dest;
|
|
|
|
struct dma_chan *dma_chan;
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, SLAB_KERNEL);
|
|
|
|
if (!src)
|
|
|
|
return -ENOMEM;
|
|
|
|
dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, SLAB_KERNEL);
|
|
|
|
if (!dest) {
|
|
|
|
kfree(src);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fill in src buffer */
|
|
|
|
for (i = 0; i < IOAT_TEST_SIZE; i++)
|
|
|
|
src[i] = (u8)i;
|
|
|
|
|
|
|
|
/* Start copy, using first DMA channel */
|
|
|
|
dma_chan = container_of(device->common.channels.next,
|
|
|
|
struct dma_chan,
|
|
|
|
device_node);
|
|
|
|
if (ioat_dma_alloc_chan_resources(dma_chan) < 1) {
|
|
|
|
err = -ENODEV;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
cookie = ioat_dma_memcpy_buf_to_buf(dma_chan, dest, src, IOAT_TEST_SIZE);
|
|
|
|
ioat_dma_memcpy_issue_pending(dma_chan);
|
|
|
|
msleep(1);
|
|
|
|
|
|
|
|
if (ioat_dma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
|
|
|
|
printk(KERN_ERR "ioatdma: Self-test copy timed out, disabling\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
if (memcmp(src, dest, IOAT_TEST_SIZE)) {
|
|
|
|
printk(KERN_ERR "ioatdma: Self-test copy failed compare, disabling\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto free_resources;
|
|
|
|
}
|
|
|
|
|
|
|
|
free_resources:
|
|
|
|
ioat_dma_free_chan_resources(dma_chan);
|
|
|
|
out:
|
|
|
|
kfree(src);
|
|
|
|
kfree(dest);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __devinit ioat_probe(struct pci_dev *pdev,
|
|
|
|
const struct pci_device_id *ent)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
unsigned long mmio_start, mmio_len;
|
|
|
|
void *reg_base;
|
|
|
|
struct ioat_device *device;
|
|
|
|
|
|
|
|
err = pci_enable_device(pdev);
|
|
|
|
if (err)
|
|
|
|
goto err_enable_device;
|
|
|
|
|
|
|
|
err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
|
|
|
|
if (err)
|
|
|
|
err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
|
|
|
if (err)
|
|
|
|
goto err_set_dma_mask;
|
|
|
|
|
|
|
|
err = pci_request_regions(pdev, ioat_pci_drv.name);
|
|
|
|
if (err)
|
|
|
|
goto err_request_regions;
|
|
|
|
|
|
|
|
mmio_start = pci_resource_start(pdev, 0);
|
|
|
|
mmio_len = pci_resource_len(pdev, 0);
|
|
|
|
|
|
|
|
reg_base = ioremap(mmio_start, mmio_len);
|
|
|
|
if (!reg_base) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto err_ioremap;
|
|
|
|
}
|
|
|
|
|
|
|
|
device = kzalloc(sizeof(*device), GFP_KERNEL);
|
|
|
|
if (!device) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto err_kzalloc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* DMA coherent memory pool for DMA descriptor allocations */
|
|
|
|
device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
|
|
|
|
sizeof(struct ioat_dma_descriptor), 64, 0);
|
|
|
|
if (!device->dma_pool) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto err_dma_pool;
|
|
|
|
}
|
|
|
|
|
|
|
|
device->completion_pool = pci_pool_create("completion_pool", pdev, sizeof(u64), SMP_CACHE_BYTES, SMP_CACHE_BYTES);
|
|
|
|
if (!device->completion_pool) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto err_completion_pool;
|
|
|
|
}
|
|
|
|
|
|
|
|
device->pdev = pdev;
|
|
|
|
pci_set_drvdata(pdev, device);
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
if (pci_enable_msi(pdev) == 0) {
|
|
|
|
device->msi = 1;
|
|
|
|
} else {
|
|
|
|
device->msi = 0;
|
|
|
|
}
|
|
|
|
#endif
|
2006-07-02 02:29:38 +00:00
|
|
|
err = request_irq(pdev->irq, &ioat_do_interrupt, IRQF_SHARED, "ioat",
|
2006-05-24 00:35:34 +00:00
|
|
|
device);
|
|
|
|
if (err)
|
|
|
|
goto err_irq;
|
|
|
|
|
|
|
|
device->reg_base = reg_base;
|
|
|
|
|
|
|
|
ioatdma_write8(device, IOAT_INTRCTRL_OFFSET, IOAT_INTRCTRL_MASTER_INT_EN);
|
|
|
|
pci_set_master(pdev);
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&device->common.channels);
|
|
|
|
enumerate_dma_channels(device);
|
|
|
|
|
|
|
|
device->common.device_alloc_chan_resources = ioat_dma_alloc_chan_resources;
|
|
|
|
device->common.device_free_chan_resources = ioat_dma_free_chan_resources;
|
|
|
|
device->common.device_memcpy_buf_to_buf = ioat_dma_memcpy_buf_to_buf;
|
|
|
|
device->common.device_memcpy_buf_to_pg = ioat_dma_memcpy_buf_to_pg;
|
|
|
|
device->common.device_memcpy_pg_to_pg = ioat_dma_memcpy_pg_to_pg;
|
|
|
|
device->common.device_memcpy_complete = ioat_dma_is_complete;
|
|
|
|
device->common.device_memcpy_issue_pending = ioat_dma_memcpy_issue_pending;
|
|
|
|
printk(KERN_INFO "Intel(R) I/OAT DMA Engine found, %d channels\n",
|
|
|
|
device->common.chancnt);
|
|
|
|
|
|
|
|
err = ioat_self_test(device);
|
|
|
|
if (err)
|
|
|
|
goto err_self_test;
|
|
|
|
|
|
|
|
dma_async_device_register(&device->common);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_self_test:
|
|
|
|
err_irq:
|
|
|
|
pci_pool_destroy(device->completion_pool);
|
|
|
|
err_completion_pool:
|
|
|
|
pci_pool_destroy(device->dma_pool);
|
|
|
|
err_dma_pool:
|
|
|
|
kfree(device);
|
|
|
|
err_kzalloc:
|
|
|
|
iounmap(reg_base);
|
|
|
|
err_ioremap:
|
|
|
|
pci_release_regions(pdev);
|
|
|
|
err_request_regions:
|
|
|
|
err_set_dma_mask:
|
|
|
|
pci_disable_device(pdev);
|
|
|
|
err_enable_device:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __devexit ioat_remove(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct ioat_device *device;
|
|
|
|
struct dma_chan *chan, *_chan;
|
|
|
|
struct ioat_dma_chan *ioat_chan;
|
|
|
|
|
|
|
|
device = pci_get_drvdata(pdev);
|
|
|
|
dma_async_device_unregister(&device->common);
|
|
|
|
|
|
|
|
free_irq(device->pdev->irq, device);
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
if (device->msi)
|
|
|
|
pci_disable_msi(device->pdev);
|
|
|
|
#endif
|
|
|
|
pci_pool_destroy(device->dma_pool);
|
|
|
|
pci_pool_destroy(device->completion_pool);
|
|
|
|
iounmap(device->reg_base);
|
|
|
|
pci_release_regions(pdev);
|
|
|
|
pci_disable_device(pdev);
|
|
|
|
list_for_each_entry_safe(chan, _chan, &device->common.channels, device_node) {
|
|
|
|
ioat_chan = to_ioat_chan(chan);
|
|
|
|
list_del(&chan->device_node);
|
|
|
|
kfree(ioat_chan);
|
|
|
|
}
|
|
|
|
kfree(device);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* MODULE API */
|
|
|
|
MODULE_VERSION("1.7");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Intel Corporation");
|
|
|
|
|
|
|
|
static int __init ioat_init_module(void)
|
|
|
|
{
|
|
|
|
/* it's currently unsafe to unload this module */
|
|
|
|
/* if forced, worst case is that rmmod hangs */
|
2006-06-26 07:10:46 +00:00
|
|
|
__unsafe(THIS_MODULE);
|
2006-05-24 00:35:34 +00:00
|
|
|
|
2006-07-04 02:28:13 +00:00
|
|
|
return pci_module_init(&ioat_pci_drv);
|
2006-05-24 00:35:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
module_init(ioat_init_module);
|
|
|
|
|
|
|
|
static void __exit ioat_exit_module(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&ioat_pci_drv);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_exit(ioat_exit_module);
|