208 lines
4.7 KiB
C
208 lines
4.7 KiB
C
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/*
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* Copyright (C) Michel D<EFBFBD>nzer <michdaen@iiic.ethz.ch>
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*
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* APUS PCI routines.
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*
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* Currently, only B/CVisionPPC cards (Permedia2) are supported.
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*
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* Thanks to Geert Uytterhoeven for the idea:
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* Read values from given config space(s) for the first devices, -1 otherwise
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*
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*/
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#ifdef CONFIG_AMIGA
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include "apus_pci.h"
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/* These definitions are mostly adapted from pm2fb.c */
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#undef APUS_PCI_MASTER_DEBUG
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#ifdef APUS_PCI_MASTER_DEBUG
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#define DPRINTK(a,b...) printk(KERN_DEBUG "apus_pci: %s: " a, __FUNCTION__ , ## b)
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#else
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#define DPRINTK(a,b...)
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#endif
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/*
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* The _DEFINITIVE_ memory mapping/unmapping functions.
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* This is due to the fact that they're changing soooo often...
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*/
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#define DEFW() wmb()
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#define DEFR() rmb()
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#define DEFRW() mb()
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#define DEVNO(d) ((d)>>3)
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#define FNNO(d) ((d)&7)
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extern unsigned long powerup_PCI_present;
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static struct pci_controller *apus_hose;
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void *pci_io_base(unsigned int bus)
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{
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return 0;
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}
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int
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apus_pcibios_read_config(struct pci_bus *bus, int devfn, int offset,
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int len, u32 *val)
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{
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int fnno = FNNO(devfn);
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int devno = DEVNO(devfn);
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volatile unsigned char *cfg_data;
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if (bus->number > 0 || devno != 1) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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/* base address + function offset + offset ^ endianness conversion */
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/* XXX the fnno<<5 bit seems wacky -- paulus */
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cfg_data = apus_hose->cfg_data + (fnno<<5) + (offset ^ (len - 1));
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switch (len) {
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case 1:
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*val = readb(cfg_data);
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break;
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case 2:
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*val = readw(cfg_data);
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break;
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default:
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*val = readl(cfg_data);
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break;
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}
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DPRINTK("read b: 0x%x, d: 0x%x, f: 0x%x, o: 0x%x, l: %d, v: 0x%x\n",
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bus->number, devfn>>3, devfn&7, offset, len, *val);
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return PCIBIOS_SUCCESSFUL;
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}
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int
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apus_pcibios_write_config(struct pci_bus *bus, int devfn, int offset,
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int len, u32 *val)
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{
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int fnno = FNNO(devfn);
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int devno = DEVNO(devfn);
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volatile unsigned char *cfg_data;
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if (bus->number > 0 || devno != 1) {
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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/* base address + function offset + offset ^ endianness conversion */
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/* XXX the fnno<<5 bit seems wacky -- paulus */
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cfg_data = apus_hose->cfg_data + (fnno<<5) + (offset ^ (len - 1));
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switch (len) {
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case 1:
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writeb(val, cfg_data); DEFW();
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break;
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case 2:
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writew(val, cfg_data); DEFW();
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break;
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default:
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writel(val, cfg_data); DEFW();
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break;
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}
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DPRINTK("write b: 0x%x, d: 0x%x, f: 0x%x, o: 0x%x, l: %d, v: 0x%x\n",
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bus->number, devfn>>3, devfn&7, offset, len, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops apus_pci_ops = {
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apus_pcibios_read_config,
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apus_pcibios_write_config
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};
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static struct resource pci_mem = { "B/CVisionPPC PCI mem", CVPPC_FB_APERTURE_ONE, CVPPC_PCI_CONFIG, IORESOURCE_MEM };
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void __init
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apus_pcibios_fixup(void)
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{
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/* struct pci_dev *dev = pci_find_slot(0, 1<<3);
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unsigned int reg, val, offset;*/
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/* FIXME: interrupt? */
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/*dev->interrupt = xxx;*/
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request_resource(&iomem_resource, &pci_mem);
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printk("%s: PCI mem resource requested\n", __FUNCTION__);
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}
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static void __init apus_pcibios_fixup_bus(struct pci_bus *bus)
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{
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bus->resource[1] = &pci_mem;
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}
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/*
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* This is from pm2fb.c again
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*
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* Check if PCI (B/CVisionPPC) is available, initialize it and set up
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* the pcibios_* pointers
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*/
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void __init
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apus_setup_pci_ptrs(void)
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{
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if (!powerup_PCI_present) {
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DPRINTK("no PCI bridge detected\n");
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return;
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}
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DPRINTK("Phase5 B/CVisionPPC PCI bridge detected.\n");
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apus_hose = pcibios_alloc_controller();
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if (!apus_hose) {
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printk("apus_pci: Can't allocate PCI controller structure\n");
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return;
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}
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if (!(apus_hose->cfg_data = ioremap(CVPPC_PCI_CONFIG, 256))) {
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printk("apus_pci: unable to map PCI config region\n");
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return;
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}
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if (!(apus_hose->cfg_addr = ioremap(CSPPC_PCI_BRIDGE, 256))) {
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printk("apus_pci: unable to map PCI bridge\n");
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return;
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}
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writel(CSPPCF_BRIDGE_BIG_ENDIAN, apus_hose->cfg_addr + CSPPC_BRIDGE_ENDIAN);
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DEFW();
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writel(CVPPC_REGS_REGION, apus_hose->cfg_data+ PCI_BASE_ADDRESS_0);
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DEFW();
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writel(CVPPC_FB_APERTURE_ONE, apus_hose->cfg_data + PCI_BASE_ADDRESS_1);
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DEFW();
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writel(CVPPC_FB_APERTURE_TWO, apus_hose->cfg_data + PCI_BASE_ADDRESS_2);
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DEFW();
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writel(CVPPC_ROM_ADDRESS, apus_hose->cfg_data + PCI_ROM_ADDRESS);
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DEFW();
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writel(0xef000000 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER, apus_hose->cfg_data + PCI_COMMAND);
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DEFW();
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apus_hose->first_busno = 0;
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apus_hose->last_busno = 0;
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apus_hose->ops = &apus_pci_ops;
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ppc_md.pcibios_fixup = apus_pcibios_fixup;
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ppc_md.pcibios_fixup_bus = apus_pcibios_fixup_bus;
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return;
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}
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#endif /* CONFIG_AMIGA */
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